1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_PRAMC.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_PRAMC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_PRAMC_H_) /* Check if memory map has not been already included */ 58 #define S32K344_PRAMC_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- PRAMC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup PRAMC_Peripheral_Access_Layer PRAMC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** PRAMC - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t PRCR1; /**< Platform RAM Configuration register 1, offset: 0x0 */ 74 } PRAMC_Type, *PRAMC_MemMapPtr; 75 76 /** Number of instances of the PRAMC module. */ 77 #define PRAMC_INSTANCE_COUNT (2u) 78 79 /* PRAMC - Peripheral instance base addresses */ 80 /** Peripheral PRAMC_0 base address */ 81 #define IP_PRAMC_0_BASE (0x40264000u) 82 /** Peripheral PRAMC_0 base pointer */ 83 #define IP_PRAMC_0 ((PRAMC_Type *)IP_PRAMC_0_BASE) 84 /** Peripheral PRAMC_1 base address */ 85 #define IP_PRAMC_1_BASE (0x40464000u) 86 /** Peripheral PRAMC_1 base pointer */ 87 #define IP_PRAMC_1 ((PRAMC_Type *)IP_PRAMC_1_BASE) 88 /** Array initializer of PRAMC peripheral base addresses */ 89 #define IP_PRAMC_BASE_ADDRS { IP_PRAMC_0_BASE, IP_PRAMC_1_BASE } 90 /** Array initializer of PRAMC peripheral base pointers */ 91 #define IP_PRAMC_BASE_PTRS { IP_PRAMC_0, IP_PRAMC_1 } 92 93 /* ---------------------------------------------------------------------------- 94 -- PRAMC Register Masks 95 ---------------------------------------------------------------------------- */ 96 97 /*! 98 * @addtogroup PRAMC_Register_Masks PRAMC Register Masks 99 * @{ 100 */ 101 102 /*! @name PRCR1 - Platform RAM Configuration register 1 */ 103 /*! @{ */ 104 105 #define PRAMC_PRCR1_FT_DIS_MASK (0x1U) 106 #define PRAMC_PRCR1_FT_DIS_SHIFT (0U) 107 #define PRAMC_PRCR1_FT_DIS_WIDTH (1U) 108 #define PRAMC_PRCR1_FT_DIS(x) (((uint32_t)(((uint32_t)(x)) << PRAMC_PRCR1_FT_DIS_SHIFT)) & PRAMC_PRCR1_FT_DIS_MASK) 109 110 #define PRAMC_PRCR1_P0_BO_DIS_MASK (0x40U) 111 #define PRAMC_PRCR1_P0_BO_DIS_SHIFT (6U) 112 #define PRAMC_PRCR1_P0_BO_DIS_WIDTH (1U) 113 #define PRAMC_PRCR1_P0_BO_DIS(x) (((uint32_t)(((uint32_t)(x)) << PRAMC_PRCR1_P0_BO_DIS_SHIFT)) & PRAMC_PRCR1_P0_BO_DIS_MASK) 114 /*! @} */ 115 116 /*! 117 * @} 118 */ /* end of group PRAMC_Register_Masks */ 119 120 /*! 121 * @} 122 */ /* end of group PRAMC_Peripheral_Access_Layer */ 123 124 #endif /* #if !defined(S32K344_PRAMC_H_) */ 125
