1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_PIT.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_PIT 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_PIT_H_) /* Check if memory map has not been already included */ 58 #define S32K344_PIT_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- PIT Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer 68 * @{ 69 */ 70 71 /** PIT - Size of Registers Arrays */ 72 #define PIT_TIMER_COUNT 4u 73 74 /** PIT - Register Layout Typedef */ 75 typedef struct { 76 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ 77 uint8_t RESERVED_0[220]; 78 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */ 79 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */ 80 uint8_t RESERVED_1[4]; 81 __IO uint32_t RTI_LDVAL_STAT; /**< RTI Timer Load Value Sync Status Register, offset: 0xEC */ 82 __IO uint32_t RTI_LDVAL; /**< Timer Load Value Register, offset: 0xF0 */ 83 __I uint32_t RTI_CVAL; /**< Current Timer Value Register, offset: 0xF4 */ 84 __IO uint32_t RTI_TCTRL; /**< Timer Control Register, offset: 0xF8 */ 85 __IO uint32_t RTI_TFLG; /**< Timer Flag Register, offset: 0xFC */ 86 struct { /* offset: 0x100, array step: 0x10 */ 87 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ 88 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ 89 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ 90 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ 91 } TIMER[PIT_TIMER_COUNT]; 92 } PIT_Type, *PIT_MemMapPtr; 93 94 /** Number of instances of the PIT module. */ 95 #define PIT_INSTANCE_COUNT (3u) 96 97 /* PIT - Peripheral instance base addresses */ 98 /** Peripheral PIT_0 base address */ 99 #define IP_PIT_0_BASE (0x400B0000u) 100 /** Peripheral PIT_0 base pointer */ 101 #define IP_PIT_0 ((PIT_Type *)IP_PIT_0_BASE) 102 /** Peripheral PIT_1 base address */ 103 #define IP_PIT_1_BASE (0x400B4000u) 104 /** Peripheral PIT_1 base pointer */ 105 #define IP_PIT_1 ((PIT_Type *)IP_PIT_1_BASE) 106 /** Peripheral PIT_2 base address */ 107 #define IP_PIT_2_BASE (0x402FC000u) 108 /** Peripheral PIT_2 base pointer */ 109 #define IP_PIT_2 ((PIT_Type *)IP_PIT_2_BASE) 110 /** Array initializer of PIT peripheral base addresses */ 111 #define IP_PIT_BASE_ADDRS { IP_PIT_0_BASE, IP_PIT_1_BASE, IP_PIT_2_BASE } 112 /** Array initializer of PIT peripheral base pointers */ 113 #define IP_PIT_BASE_PTRS { IP_PIT_0, IP_PIT_1, IP_PIT_2 } 114 115 /* ---------------------------------------------------------------------------- 116 -- PIT Register Masks 117 ---------------------------------------------------------------------------- */ 118 119 /*! 120 * @addtogroup PIT_Register_Masks PIT Register Masks 121 * @{ 122 */ 123 124 /*! @name MCR - PIT Module Control Register */ 125 /*! @{ */ 126 127 #define PIT_MCR_FRZ_MASK (0x1U) 128 #define PIT_MCR_FRZ_SHIFT (0U) 129 #define PIT_MCR_FRZ_WIDTH (1U) 130 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) 131 132 #define PIT_MCR_MDIS_MASK (0x2U) 133 #define PIT_MCR_MDIS_SHIFT (1U) 134 #define PIT_MCR_MDIS_WIDTH (1U) 135 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) 136 137 #define PIT_MCR_MDIS_RTI_MASK (0x4U) 138 #define PIT_MCR_MDIS_RTI_SHIFT (2U) 139 #define PIT_MCR_MDIS_RTI_WIDTH (1U) 140 #define PIT_MCR_MDIS_RTI(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_RTI_SHIFT)) & PIT_MCR_MDIS_RTI_MASK) 141 /*! @} */ 142 143 /*! @name LTMR64H - PIT Upper Lifetime Timer Register */ 144 /*! @{ */ 145 146 #define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU) 147 #define PIT_LTMR64H_LTH_SHIFT (0U) 148 #define PIT_LTMR64H_LTH_WIDTH (32U) 149 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK) 150 /*! @} */ 151 152 /*! @name LTMR64L - PIT Lower Lifetime Timer Register */ 153 /*! @{ */ 154 155 #define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU) 156 #define PIT_LTMR64L_LTL_SHIFT (0U) 157 #define PIT_LTMR64L_LTL_WIDTH (32U) 158 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK) 159 /*! @} */ 160 161 /*! @name RTI_LDVAL_STAT - RTI Timer Load Value Sync Status Register */ 162 /*! @{ */ 163 164 #define PIT_RTI_LDVAL_STAT_RT_STAT_MASK (0x1U) 165 #define PIT_RTI_LDVAL_STAT_RT_STAT_SHIFT (0U) 166 #define PIT_RTI_LDVAL_STAT_RT_STAT_WIDTH (1U) 167 #define PIT_RTI_LDVAL_STAT_RT_STAT(x) (((uint32_t)(((uint32_t)(x)) << PIT_RTI_LDVAL_STAT_RT_STAT_SHIFT)) & PIT_RTI_LDVAL_STAT_RT_STAT_MASK) 168 /*! @} */ 169 170 /*! @name RTI_LDVAL - Timer Load Value Register */ 171 /*! @{ */ 172 173 #define PIT_RTI_LDVAL_TSV_MASK (0xFFFFFFFFU) 174 #define PIT_RTI_LDVAL_TSV_SHIFT (0U) 175 #define PIT_RTI_LDVAL_TSV_WIDTH (32U) 176 #define PIT_RTI_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_RTI_LDVAL_TSV_SHIFT)) & PIT_RTI_LDVAL_TSV_MASK) 177 /*! @} */ 178 179 /*! @name RTI_CVAL - Current Timer Value Register */ 180 /*! @{ */ 181 182 #define PIT_RTI_CVAL_TVL_MASK (0xFFFFFFFFU) 183 #define PIT_RTI_CVAL_TVL_SHIFT (0U) 184 #define PIT_RTI_CVAL_TVL_WIDTH (32U) 185 #define PIT_RTI_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_RTI_CVAL_TVL_SHIFT)) & PIT_RTI_CVAL_TVL_MASK) 186 /*! @} */ 187 188 /*! @name RTI_TCTRL - Timer Control Register */ 189 /*! @{ */ 190 191 #define PIT_RTI_TCTRL_TEN_MASK (0x1U) 192 #define PIT_RTI_TCTRL_TEN_SHIFT (0U) 193 #define PIT_RTI_TCTRL_TEN_WIDTH (1U) 194 #define PIT_RTI_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_RTI_TCTRL_TEN_SHIFT)) & PIT_RTI_TCTRL_TEN_MASK) 195 196 #define PIT_RTI_TCTRL_TIE_MASK (0x2U) 197 #define PIT_RTI_TCTRL_TIE_SHIFT (1U) 198 #define PIT_RTI_TCTRL_TIE_WIDTH (1U) 199 #define PIT_RTI_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_RTI_TCTRL_TIE_SHIFT)) & PIT_RTI_TCTRL_TIE_MASK) 200 201 #define PIT_RTI_TCTRL_CHN_MASK (0x4U) 202 #define PIT_RTI_TCTRL_CHN_SHIFT (2U) 203 #define PIT_RTI_TCTRL_CHN_WIDTH (1U) 204 #define PIT_RTI_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_RTI_TCTRL_CHN_SHIFT)) & PIT_RTI_TCTRL_CHN_MASK) 205 /*! @} */ 206 207 /*! @name RTI_TFLG - Timer Flag Register */ 208 /*! @{ */ 209 210 #define PIT_RTI_TFLG_TIF_MASK (0x1U) 211 #define PIT_RTI_TFLG_TIF_SHIFT (0U) 212 #define PIT_RTI_TFLG_TIF_WIDTH (1U) 213 #define PIT_RTI_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_RTI_TFLG_TIF_SHIFT)) & PIT_RTI_TFLG_TIF_MASK) 214 /*! @} */ 215 216 /*! @name LDVAL - Timer Load Value Register */ 217 /*! @{ */ 218 219 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) 220 #define PIT_LDVAL_TSV_SHIFT (0U) 221 #define PIT_LDVAL_TSV_WIDTH (32U) 222 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) 223 /*! @} */ 224 225 /*! @name CVAL - Current Timer Value Register */ 226 /*! @{ */ 227 228 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) 229 #define PIT_CVAL_TVL_SHIFT (0U) 230 #define PIT_CVAL_TVL_WIDTH (32U) 231 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) 232 /*! @} */ 233 234 /*! @name TCTRL - Timer Control Register */ 235 /*! @{ */ 236 237 #define PIT_TCTRL_TEN_MASK (0x1U) 238 #define PIT_TCTRL_TEN_SHIFT (0U) 239 #define PIT_TCTRL_TEN_WIDTH (1U) 240 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) 241 242 #define PIT_TCTRL_TIE_MASK (0x2U) 243 #define PIT_TCTRL_TIE_SHIFT (1U) 244 #define PIT_TCTRL_TIE_WIDTH (1U) 245 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) 246 247 #define PIT_TCTRL_CHN_MASK (0x4U) 248 #define PIT_TCTRL_CHN_SHIFT (2U) 249 #define PIT_TCTRL_CHN_WIDTH (1U) 250 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) 251 /*! @} */ 252 253 /*! @name TFLG - Timer Flag Register */ 254 /*! @{ */ 255 256 #define PIT_TFLG_TIF_MASK (0x1U) 257 #define PIT_TFLG_TIF_SHIFT (0U) 258 #define PIT_TFLG_TIF_WIDTH (1U) 259 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) 260 /*! @} */ 261 262 /*! 263 * @} 264 */ /* end of group PIT_Register_Masks */ 265 266 /*! 267 * @} 268 */ /* end of group PIT_Peripheral_Access_Layer */ 269 270 #endif /* #if !defined(S32K344_PIT_H_) */ 271
