1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_PFLASH.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_PFLASH 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_PFLASH_H_) /* Check if memory map has not been already included */ 58 #define S32K344_PFLASH_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- PFLASH Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup PFLASH_Peripheral_Access_Layer PFLASH Peripheral Access Layer 68 * @{ 69 */ 70 71 /** PFLASH - Size of Registers Arrays */ 72 #define PFLASH_PFCRI_COUNT 2u 73 #define PFLASH_PFCBLKI_SPELOCK_COUNT 5u 74 #define PFLASH_U_PFCBLKI_SPELOCK_COUNT 1u 75 #define PFLASH_PFCBLKI_SSPELOCK_COUNT 4u 76 #define PFLASH_PFCBLKI_SETSLOCK_COUNT 5u 77 #define PFLASH_U_PFCBLKI_SETSLOCK_COUNT 1u 78 #define PFLASH_PFCBLKI_SSETSLOCK_COUNT 4u 79 #define PFLASH_PFCBLKI_LOCKMASTER_S_COUNT 5u 80 #define PFLASH_PFCBLKI_LOCKMASTER_S_PFCBLKI_LOCKMASTER_SJ_COUNT 8u 81 #define PFLASH_U_PFCBLKI_LOCKMASTER_S_COUNT 1u 82 #define PFLASH_PFCBLKI_LOCKMASTER_SS_PFCBLKI_LOCKMASTER_SSJ_COUNT 3u 83 #define PFLASH_PFCBLKI_LOCKMASTER_SS_COUNT 4u 84 85 /** PFLASH - Register Layout Typedef */ 86 typedef struct { 87 __IO uint32_t PFCR[PFLASH_PFCRI_COUNT]; /**< Platform Flash Memory Configuration 0..Platform Flash Memory Configuration 1, array offset: 0x0, array step: 0x4 */ 88 uint8_t RESERVED_0[8]; 89 __IO uint32_t PFCR4; /**< Platform Flash Memory Configuration 4, offset: 0x10 */ 90 __IO uint32_t PFAPR; /**< Platform Flash Memory Access Protection, offset: 0x14 */ 91 uint8_t RESERVED_1[744]; 92 __IO uint32_t PFCPGM_PEADR_L; /**< Platform Flash Memory Program Erase Address Logical, offset: 0x300 */ 93 __I uint32_t PFCPGM_PEADR_P; /**< Platform Flash Memory Program Erase Address Physical, offset: 0x304 */ 94 __IO uint32_t PFCPGM_XPEADR_L; /**< Platform Flash Memory Express Program Erase Address Logical, offset: 0x308 */ 95 __I uint32_t PFCPGM_XPEADR_P; /**< Platform Flash Memory Express Program Erase Address Physical, offset: 0x30C */ 96 uint8_t RESERVED_2[48]; 97 __IO uint32_t PFCBLK_SPELOCK[PFLASH_PFCBLKI_SPELOCK_COUNT]; /**< Block n Sector Program Erase Lock, array offset: 0x340, array step: 0x4 */ 98 uint8_t RESERVED_3[4]; 99 __IO uint32_t PFCBLKU_SPELOCK[PFLASH_U_PFCBLKI_SPELOCK_COUNT]; /**< Block UTEST Sector Program Erase Lock, array offset: 0x358, array step: 0x4 */ 100 __IO uint32_t PFCBLK_SSPELOCK[PFLASH_PFCBLKI_SSPELOCK_COUNT]; /**< Block n Super Sector Program Erase Lock, array offset: 0x35C, array step: 0x4 */ 101 uint8_t RESERVED_4[20]; 102 __IO uint32_t PFCBLK_SETSLOCK[PFLASH_PFCBLKI_SETSLOCK_COUNT]; /**< Block n Set Sector Lock, array offset: 0x380, array step: 0x4 */ 103 uint8_t RESERVED_5[4]; 104 __IO uint32_t PFCBLKU_SETSLOCK[PFLASH_U_PFCBLKI_SETSLOCK_COUNT]; /**< Block UTEST Set Sector Lock, array offset: 0x398, array step: 0x4 */ 105 __IO uint32_t PFCBLK_SSETSLOCK[PFLASH_PFCBLKI_SSETSLOCK_COUNT]; /**< Block n Set Super Sector Lock, array offset: 0x39C, array step: 0x4 */ 106 uint8_t RESERVED_6[20]; 107 __I uint32_t PFCBLK_LOCKMASTER_S[PFLASH_PFCBLKI_LOCKMASTER_S_COUNT][PFLASH_PFCBLKI_LOCKMASTER_S_PFCBLKI_LOCKMASTER_SJ_COUNT]; /**< Block a Lock Master Sector b, array offset: 0x3C0, array step: index*0x20, index2*0x4 */ 108 uint8_t RESERVED_7[32]; 109 __I uint32_t PFCBLKU_LOCKMASTER_S[PFLASH_U_PFCBLKI_LOCKMASTER_S_COUNT]; /**< Block UTEST Lock Master Sector, array offset: 0x480, array step: 0x4 */ 110 struct { /* offset: 0x484, array step: 0x10 */ 111 __I uint32_t PFCBLK_LOCKMASTER_SS[PFLASH_PFCBLKI_LOCKMASTER_SS_PFCBLKI_LOCKMASTER_SSJ_COUNT]; /**< Block m Lock Master Super Sector n, array offset: 0x484, array step: index*0x10, index2*0x4 */ 112 uint8_t RESERVED_0[4]; 113 } PFCBLKI_LOCKMASTER_SS[PFLASH_PFCBLKI_LOCKMASTER_SS_COUNT]; 114 } PFLASH_Type, *PFLASH_MemMapPtr; 115 116 /** Number of instances of the PFLASH module. */ 117 #define PFLASH_INSTANCE_COUNT (1u) 118 119 /* PFLASH - Peripheral instance base addresses */ 120 /** Peripheral PFLASH base address */ 121 #define IP_PFLASH_BASE (0x40268000u) 122 /** Peripheral PFLASH base pointer */ 123 #define IP_PFLASH ((PFLASH_Type *)IP_PFLASH_BASE) 124 /** Array initializer of PFLASH peripheral base addresses */ 125 #define IP_PFLASH_BASE_ADDRS { IP_PFLASH_BASE } 126 /** Array initializer of PFLASH peripheral base pointers */ 127 #define IP_PFLASH_BASE_PTRS { IP_PFLASH } 128 129 /* ---------------------------------------------------------------------------- 130 -- PFLASH Register Masks 131 ---------------------------------------------------------------------------- */ 132 133 /*! 134 * @addtogroup PFLASH_Register_Masks PFLASH Register Masks 135 * @{ 136 */ 137 138 /*! @name PFCR - Platform Flash Memory Configuration 0..Platform Flash Memory Configuration 1 */ 139 /*! @{ */ 140 141 #define PFLASH_PFCR_P0_CBFEN_MASK (0x1U) 142 #define PFLASH_PFCR_P0_CBFEN_SHIFT (0U) 143 #define PFLASH_PFCR_P0_CBFEN_WIDTH (1U) 144 #define PFLASH_PFCR_P0_CBFEN(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCR_P0_CBFEN_SHIFT)) & PFLASH_PFCR_P0_CBFEN_MASK) 145 146 #define PFLASH_PFCR_P0_DBFEN_MASK (0x2U) 147 #define PFLASH_PFCR_P0_DBFEN_SHIFT (1U) 148 #define PFLASH_PFCR_P0_DBFEN_WIDTH (1U) 149 #define PFLASH_PFCR_P0_DBFEN(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCR_P0_DBFEN_SHIFT)) & PFLASH_PFCR_P0_DBFEN_MASK) 150 151 #define PFLASH_PFCR_P0_CPFEN_MASK (0x10U) 152 #define PFLASH_PFCR_P0_CPFEN_SHIFT (4U) 153 #define PFLASH_PFCR_P0_CPFEN_WIDTH (1U) 154 #define PFLASH_PFCR_P0_CPFEN(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCR_P0_CPFEN_SHIFT)) & PFLASH_PFCR_P0_CPFEN_MASK) 155 156 #define PFLASH_PFCR_P0_DPFEN_MASK (0x20U) 157 #define PFLASH_PFCR_P0_DPFEN_SHIFT (5U) 158 #define PFLASH_PFCR_P0_DPFEN_WIDTH (1U) 159 #define PFLASH_PFCR_P0_DPFEN(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCR_P0_DPFEN_SHIFT)) & PFLASH_PFCR_P0_DPFEN_MASK) 160 161 #define PFLASH_PFCR_P1_CBFEN_MASK (0x1U) 162 #define PFLASH_PFCR_P1_CBFEN_SHIFT (0U) 163 #define PFLASH_PFCR_P1_CBFEN_WIDTH (1U) 164 #define PFLASH_PFCR_P1_CBFEN(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCR_P1_CBFEN_SHIFT)) & PFLASH_PFCR_P1_CBFEN_MASK) 165 166 #define PFLASH_PFCR_P1_DBFEN_MASK (0x2U) 167 #define PFLASH_PFCR_P1_DBFEN_SHIFT (1U) 168 #define PFLASH_PFCR_P1_DBFEN_WIDTH (1U) 169 #define PFLASH_PFCR_P1_DBFEN(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCR_P1_DBFEN_SHIFT)) & PFLASH_PFCR_P1_DBFEN_MASK) 170 171 #define PFLASH_PFCR_P1_CPFEN_MASK (0x10U) 172 #define PFLASH_PFCR_P1_CPFEN_SHIFT (4U) 173 #define PFLASH_PFCR_P1_CPFEN_WIDTH (1U) 174 #define PFLASH_PFCR_P1_CPFEN(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCR_P1_CPFEN_SHIFT)) & PFLASH_PFCR_P1_CPFEN_MASK) 175 176 #define PFLASH_PFCR_P1_DPFEN_MASK (0x20U) 177 #define PFLASH_PFCR_P1_DPFEN_SHIFT (5U) 178 #define PFLASH_PFCR_P1_DPFEN_WIDTH (1U) 179 #define PFLASH_PFCR_P1_DPFEN(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCR_P1_DPFEN_SHIFT)) & PFLASH_PFCR_P1_DPFEN_MASK) 180 /*! @} */ 181 182 /*! @name PFCR4 - Platform Flash Memory Configuration 4 */ 183 /*! @{ */ 184 185 #define PFLASH_PFCR4_DERR_SUP_MASK (0x1U) 186 #define PFLASH_PFCR4_DERR_SUP_SHIFT (0U) 187 #define PFLASH_PFCR4_DERR_SUP_WIDTH (1U) 188 #define PFLASH_PFCR4_DERR_SUP(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCR4_DERR_SUP_SHIFT)) & PFLASH_PFCR4_DERR_SUP_MASK) 189 190 #define PFLASH_PFCR4_BLK4_PS_MASK (0xEU) 191 #define PFLASH_PFCR4_BLK4_PS_SHIFT (1U) 192 #define PFLASH_PFCR4_BLK4_PS_WIDTH (3U) 193 #define PFLASH_PFCR4_BLK4_PS(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCR4_BLK4_PS_SHIFT)) & PFLASH_PFCR4_BLK4_PS_MASK) 194 195 #define PFLASH_PFCR4_DMEEE_MASK (0x80U) 196 #define PFLASH_PFCR4_DMEEE_SHIFT (7U) 197 #define PFLASH_PFCR4_DMEEE_WIDTH (1U) 198 #define PFLASH_PFCR4_DMEEE(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCR4_DMEEE_SHIFT)) & PFLASH_PFCR4_DMEEE_MASK) 199 /*! @} */ 200 201 /*! @name PFAPR - Platform Flash Memory Access Protection */ 202 /*! @{ */ 203 204 #define PFLASH_PFAPR_M15AP_MASK (0x3U) 205 #define PFLASH_PFAPR_M15AP_SHIFT (0U) 206 #define PFLASH_PFAPR_M15AP_WIDTH (2U) 207 #define PFLASH_PFAPR_M15AP(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFAPR_M15AP_SHIFT)) & PFLASH_PFAPR_M15AP_MASK) 208 209 #define PFLASH_PFAPR_M14AP_MASK (0xCU) 210 #define PFLASH_PFAPR_M14AP_SHIFT (2U) 211 #define PFLASH_PFAPR_M14AP_WIDTH (2U) 212 #define PFLASH_PFAPR_M14AP(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFAPR_M14AP_SHIFT)) & PFLASH_PFAPR_M14AP_MASK) 213 214 #define PFLASH_PFAPR_M13AP_MASK (0x30U) 215 #define PFLASH_PFAPR_M13AP_SHIFT (4U) 216 #define PFLASH_PFAPR_M13AP_WIDTH (2U) 217 #define PFLASH_PFAPR_M13AP(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFAPR_M13AP_SHIFT)) & PFLASH_PFAPR_M13AP_MASK) 218 219 #define PFLASH_PFAPR_M12AP_MASK (0xC0U) 220 #define PFLASH_PFAPR_M12AP_SHIFT (6U) 221 #define PFLASH_PFAPR_M12AP_WIDTH (2U) 222 #define PFLASH_PFAPR_M12AP(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFAPR_M12AP_SHIFT)) & PFLASH_PFAPR_M12AP_MASK) 223 224 #define PFLASH_PFAPR_M11AP_MASK (0x300U) 225 #define PFLASH_PFAPR_M11AP_SHIFT (8U) 226 #define PFLASH_PFAPR_M11AP_WIDTH (2U) 227 #define PFLASH_PFAPR_M11AP(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFAPR_M11AP_SHIFT)) & PFLASH_PFAPR_M11AP_MASK) 228 229 #define PFLASH_PFAPR_M10AP_MASK (0xC00U) 230 #define PFLASH_PFAPR_M10AP_SHIFT (10U) 231 #define PFLASH_PFAPR_M10AP_WIDTH (2U) 232 #define PFLASH_PFAPR_M10AP(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFAPR_M10AP_SHIFT)) & PFLASH_PFAPR_M10AP_MASK) 233 234 #define PFLASH_PFAPR_M9AP_MASK (0x3000U) 235 #define PFLASH_PFAPR_M9AP_SHIFT (12U) 236 #define PFLASH_PFAPR_M9AP_WIDTH (2U) 237 #define PFLASH_PFAPR_M9AP(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFAPR_M9AP_SHIFT)) & PFLASH_PFAPR_M9AP_MASK) 238 239 #define PFLASH_PFAPR_M8AP_MASK (0xC000U) 240 #define PFLASH_PFAPR_M8AP_SHIFT (14U) 241 #define PFLASH_PFAPR_M8AP_WIDTH (2U) 242 #define PFLASH_PFAPR_M8AP(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFAPR_M8AP_SHIFT)) & PFLASH_PFAPR_M8AP_MASK) 243 244 #define PFLASH_PFAPR_M7AP_MASK (0x30000U) 245 #define PFLASH_PFAPR_M7AP_SHIFT (16U) 246 #define PFLASH_PFAPR_M7AP_WIDTH (2U) 247 #define PFLASH_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFAPR_M7AP_SHIFT)) & PFLASH_PFAPR_M7AP_MASK) 248 249 #define PFLASH_PFAPR_M6AP_MASK (0xC0000U) 250 #define PFLASH_PFAPR_M6AP_SHIFT (18U) 251 #define PFLASH_PFAPR_M6AP_WIDTH (2U) 252 #define PFLASH_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFAPR_M6AP_SHIFT)) & PFLASH_PFAPR_M6AP_MASK) 253 254 #define PFLASH_PFAPR_M5AP_MASK (0x300000U) 255 #define PFLASH_PFAPR_M5AP_SHIFT (20U) 256 #define PFLASH_PFAPR_M5AP_WIDTH (2U) 257 #define PFLASH_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFAPR_M5AP_SHIFT)) & PFLASH_PFAPR_M5AP_MASK) 258 259 #define PFLASH_PFAPR_M4AP_MASK (0xC00000U) 260 #define PFLASH_PFAPR_M4AP_SHIFT (22U) 261 #define PFLASH_PFAPR_M4AP_WIDTH (2U) 262 #define PFLASH_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFAPR_M4AP_SHIFT)) & PFLASH_PFAPR_M4AP_MASK) 263 264 #define PFLASH_PFAPR_M2AP_MASK (0xC000000U) 265 #define PFLASH_PFAPR_M2AP_SHIFT (26U) 266 #define PFLASH_PFAPR_M2AP_WIDTH (2U) 267 #define PFLASH_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFAPR_M2AP_SHIFT)) & PFLASH_PFAPR_M2AP_MASK) 268 269 #define PFLASH_PFAPR_M1AP_MASK (0x30000000U) 270 #define PFLASH_PFAPR_M1AP_SHIFT (28U) 271 #define PFLASH_PFAPR_M1AP_WIDTH (2U) 272 #define PFLASH_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFAPR_M1AP_SHIFT)) & PFLASH_PFAPR_M1AP_MASK) 273 274 #define PFLASH_PFAPR_M0AP_MASK (0xC0000000U) 275 #define PFLASH_PFAPR_M0AP_SHIFT (30U) 276 #define PFLASH_PFAPR_M0AP_WIDTH (2U) 277 #define PFLASH_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFAPR_M0AP_SHIFT)) & PFLASH_PFAPR_M0AP_MASK) 278 /*! @} */ 279 280 /*! @name PFCPGM_PEADR_L - Platform Flash Memory Program Erase Address Logical */ 281 /*! @{ */ 282 283 #define PFLASH_PFCPGM_PEADR_L_PEADR_L_MASK (0xFFFFFFFFU) 284 #define PFLASH_PFCPGM_PEADR_L_PEADR_L_SHIFT (0U) 285 #define PFLASH_PFCPGM_PEADR_L_PEADR_L_WIDTH (32U) 286 #define PFLASH_PFCPGM_PEADR_L_PEADR_L(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCPGM_PEADR_L_PEADR_L_SHIFT)) & PFLASH_PFCPGM_PEADR_L_PEADR_L_MASK) 287 /*! @} */ 288 289 /*! @name PFCPGM_PEADR_P - Platform Flash Memory Program Erase Address Physical */ 290 /*! @{ */ 291 292 #define PFLASH_PFCPGM_PEADR_P_PEADR_P_MASK (0xFFFFFFFFU) 293 #define PFLASH_PFCPGM_PEADR_P_PEADR_P_SHIFT (0U) 294 #define PFLASH_PFCPGM_PEADR_P_PEADR_P_WIDTH (32U) 295 #define PFLASH_PFCPGM_PEADR_P_PEADR_P(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCPGM_PEADR_P_PEADR_P_SHIFT)) & PFLASH_PFCPGM_PEADR_P_PEADR_P_MASK) 296 /*! @} */ 297 298 /*! @name PFCPGM_XPEADR_L - Platform Flash Memory Express Program Erase Address Logical */ 299 /*! @{ */ 300 301 #define PFLASH_PFCPGM_XPEADR_L_XPEADR_L_MASK (0xFFFFFFFFU) 302 #define PFLASH_PFCPGM_XPEADR_L_XPEADR_L_SHIFT (0U) 303 #define PFLASH_PFCPGM_XPEADR_L_XPEADR_L_WIDTH (32U) 304 #define PFLASH_PFCPGM_XPEADR_L_XPEADR_L(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCPGM_XPEADR_L_XPEADR_L_SHIFT)) & PFLASH_PFCPGM_XPEADR_L_XPEADR_L_MASK) 305 /*! @} */ 306 307 /*! @name PFCPGM_XPEADR_P - Platform Flash Memory Express Program Erase Address Physical */ 308 /*! @{ */ 309 310 #define PFLASH_PFCPGM_XPEADR_P_XPEADR_P_MASK (0xFFFFFFFFU) 311 #define PFLASH_PFCPGM_XPEADR_P_XPEADR_P_SHIFT (0U) 312 #define PFLASH_PFCPGM_XPEADR_P_XPEADR_P_WIDTH (32U) 313 #define PFLASH_PFCPGM_XPEADR_P_XPEADR_P(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCPGM_XPEADR_P_XPEADR_P_SHIFT)) & PFLASH_PFCPGM_XPEADR_P_XPEADR_P_MASK) 314 /*! @} */ 315 316 /*! @name PFCBLK_SPELOCK - Block n Sector Program Erase Lock */ 317 /*! @{ */ 318 319 #define PFLASH_PFCBLK_SPELOCK_SLCK_MASK (0xFFFFFFFFU) 320 #define PFLASH_PFCBLK_SPELOCK_SLCK_SHIFT (0U) 321 #define PFLASH_PFCBLK_SPELOCK_SLCK_WIDTH (32U) 322 #define PFLASH_PFCBLK_SPELOCK_SLCK(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCBLK_SPELOCK_SLCK_SHIFT)) & PFLASH_PFCBLK_SPELOCK_SLCK_MASK) 323 /*! @} */ 324 325 /*! @name PFCBLKU_SPELOCK - Block UTEST Sector Program Erase Lock */ 326 /*! @{ */ 327 328 #define PFLASH_PFCBLKU_SPELOCK_SLCK_MASK (0x1U) 329 #define PFLASH_PFCBLKU_SPELOCK_SLCK_SHIFT (0U) 330 #define PFLASH_PFCBLKU_SPELOCK_SLCK_WIDTH (1U) 331 #define PFLASH_PFCBLKU_SPELOCK_SLCK(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCBLKU_SPELOCK_SLCK_SHIFT)) & PFLASH_PFCBLKU_SPELOCK_SLCK_MASK) 332 /*! @} */ 333 334 /*! @name PFCBLK_SSPELOCK - Block n Super Sector Program Erase Lock */ 335 /*! @{ */ 336 337 #define PFLASH_PFCBLK_SSPELOCK_SSLCK_MASK (0xFFFU) 338 #define PFLASH_PFCBLK_SSPELOCK_SSLCK_SHIFT (0U) 339 #define PFLASH_PFCBLK_SSPELOCK_SSLCK_WIDTH (12U) 340 #define PFLASH_PFCBLK_SSPELOCK_SSLCK(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCBLK_SSPELOCK_SSLCK_SHIFT)) & PFLASH_PFCBLK_SSPELOCK_SSLCK_MASK) 341 /*! @} */ 342 343 /*! @name PFCBLK_SETSLOCK - Block n Set Sector Lock */ 344 /*! @{ */ 345 346 #define PFLASH_PFCBLK_SETSLOCK_SETSLCK_MASK (0xFFFFFFFFU) 347 #define PFLASH_PFCBLK_SETSLOCK_SETSLCK_SHIFT (0U) 348 #define PFLASH_PFCBLK_SETSLOCK_SETSLCK_WIDTH (32U) 349 #define PFLASH_PFCBLK_SETSLOCK_SETSLCK(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCBLK_SETSLOCK_SETSLCK_SHIFT)) & PFLASH_PFCBLK_SETSLOCK_SETSLCK_MASK) 350 /*! @} */ 351 352 /*! @name PFCBLKU_SETSLOCK - Block UTEST Set Sector Lock */ 353 /*! @{ */ 354 355 #define PFLASH_PFCBLKU_SETSLOCK_SETSLCK_MASK (0x1U) 356 #define PFLASH_PFCBLKU_SETSLOCK_SETSLCK_SHIFT (0U) 357 #define PFLASH_PFCBLKU_SETSLOCK_SETSLCK_WIDTH (1U) 358 #define PFLASH_PFCBLKU_SETSLOCK_SETSLCK(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCBLKU_SETSLOCK_SETSLCK_SHIFT)) & PFLASH_PFCBLKU_SETSLOCK_SETSLCK_MASK) 359 /*! @} */ 360 361 /*! @name PFCBLK_SSETSLOCK - Block n Set Super Sector Lock */ 362 /*! @{ */ 363 364 #define PFLASH_PFCBLK_SSETSLOCK_SSETSLCK_MASK (0xFFFU) 365 #define PFLASH_PFCBLK_SSETSLOCK_SSETSLCK_SHIFT (0U) 366 #define PFLASH_PFCBLK_SSETSLOCK_SSETSLCK_WIDTH (12U) 367 #define PFLASH_PFCBLK_SSETSLOCK_SSETSLCK(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCBLK_SSETSLOCK_SSETSLCK_SHIFT)) & PFLASH_PFCBLK_SSETSLOCK_SSETSLCK_MASK) 368 /*! @} */ 369 370 /*! @name PFCBLK_LOCKMASTER_S - Block a Lock Master Sector b */ 371 /*! @{ */ 372 373 #define PFLASH_PFCBLK_LOCKMASTER_S_LOCKMASTER_S_MASK (0xFFFFFFFFU) 374 #define PFLASH_PFCBLK_LOCKMASTER_S_LOCKMASTER_S_SHIFT (0U) 375 #define PFLASH_PFCBLK_LOCKMASTER_S_LOCKMASTER_S_WIDTH (32U) 376 #define PFLASH_PFCBLK_LOCKMASTER_S_LOCKMASTER_S(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCBLK_LOCKMASTER_S_LOCKMASTER_S_SHIFT)) & PFLASH_PFCBLK_LOCKMASTER_S_LOCKMASTER_S_MASK) 377 /*! @} */ 378 379 /*! @name PFCBLKU_LOCKMASTER_S - Block UTEST Lock Master Sector */ 380 /*! @{ */ 381 382 #define PFLASH_PFCBLKU_LOCKMASTER_S_LOCKMASTER_S_MASK (0xFFU) 383 #define PFLASH_PFCBLKU_LOCKMASTER_S_LOCKMASTER_S_SHIFT (0U) 384 #define PFLASH_PFCBLKU_LOCKMASTER_S_LOCKMASTER_S_WIDTH (8U) 385 #define PFLASH_PFCBLKU_LOCKMASTER_S_LOCKMASTER_S(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCBLKU_LOCKMASTER_S_LOCKMASTER_S_SHIFT)) & PFLASH_PFCBLKU_LOCKMASTER_S_LOCKMASTER_S_MASK) 386 /*! @} */ 387 388 /*! @name PFCBLK_LOCKMASTER_SS - Block m Lock Master Super Sector n */ 389 /*! @{ */ 390 391 #define PFLASH_PFCBLK_LOCKMASTER_SS_LOCKMASTER_SS_MASK (0xFFFFFFFFU) 392 #define PFLASH_PFCBLK_LOCKMASTER_SS_LOCKMASTER_SS_SHIFT (0U) 393 #define PFLASH_PFCBLK_LOCKMASTER_SS_LOCKMASTER_SS_WIDTH (32U) 394 #define PFLASH_PFCBLK_LOCKMASTER_SS_LOCKMASTER_SS(x) (((uint32_t)(((uint32_t)(x)) << PFLASH_PFCBLK_LOCKMASTER_SS_LOCKMASTER_SS_SHIFT)) & PFLASH_PFCBLK_LOCKMASTER_SS_LOCKMASTER_SS_MASK) 395 /*! @} */ 396 397 /*! 398 * @} 399 */ /* end of group PFLASH_Register_Masks */ 400 401 /*! 402 * @} 403 */ /* end of group PFLASH_Peripheral_Access_Layer */ 404 405 #endif /* #if !defined(S32K344_PFLASH_H_) */ 406
