1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_MU.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_MU 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_MU_H_) /* Check if memory map has not been already included */ 58 #define S32K344_MU_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- MU Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer 68 * @{ 69 */ 70 71 /** MU - Size of Registers Arrays */ 72 #define MU_TR_COUNT 4u 73 #define MU_RR_COUNT 4u 74 75 /** MU - Register Layout Typedef */ 76 typedef struct { 77 __I uint32_t VER; /**< Version ID Register, offset: 0x0 */ 78 __I uint32_t PAR; /**< Parameter Register, offset: 0x4 */ 79 __IO uint32_t CR; /**< Control Register, offset: 0x8 */ 80 __IO uint32_t SR; /**< Status Register, offset: 0xC */ 81 __IO uint32_t CCR0; /**< Core Control Register 0, offset: 0x10 */ 82 uint8_t RESERVED_0[4]; 83 __IO uint32_t CSSR0; /**< Core Sticky Status Register 0, offset: 0x18 */ 84 uint8_t RESERVED_1[228]; 85 __IO uint32_t FCR; /**< Flag Control Register, offset: 0x100 */ 86 __I uint32_t FSR; /**< Flag Status Register, offset: 0x104 */ 87 uint8_t RESERVED_2[8]; 88 __IO uint32_t GIER; /**< General Interrupt Enable Register, offset: 0x110 */ 89 __IO uint32_t GCR; /**< General Control Register, offset: 0x114 */ 90 __IO uint32_t GSR; /**< General Status Register, offset: 0x118 */ 91 uint8_t RESERVED_3[4]; 92 __IO uint32_t TCR; /**< Transmit Control Register, offset: 0x120 */ 93 __I uint32_t TSR; /**< Transmit Status Register, offset: 0x124 */ 94 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x128 */ 95 __I uint32_t RSR; /**< Receive Status Register, offset: 0x12C */ 96 uint8_t RESERVED_4[208]; 97 __IO uint32_t TR[MU_TR_COUNT]; /**< Transmit Register, array offset: 0x200, array step: 0x4 */ 98 uint8_t RESERVED_5[112]; 99 __I uint32_t RR[MU_RR_COUNT]; /**< Receive Register, array offset: 0x280, array step: 0x4 */ 100 } MU_Type, *MU_MemMapPtr; 101 102 /** Number of instances of the MU module. */ 103 #define MU_INSTANCE_COUNT (2u) 104 105 /* MU - Peripheral instance base addresses */ 106 /** Peripheral MU_0__MUB base address */ 107 #define IP_MU_0__MUB_BASE (0x4038C000u) 108 /** Peripheral MU_0__MUB base pointer */ 109 #define IP_MU_0__MUB ((MU_Type *)IP_MU_0__MUB_BASE) 110 /** Peripheral MU_1__MUB base address */ 111 #define IP_MU_1__MUB_BASE (0x404EC000u) 112 /** Peripheral MU_1__MUB base pointer */ 113 #define IP_MU_1__MUB ((MU_Type *)IP_MU_1__MUB_BASE) 114 /** Array initializer of MU peripheral base addresses */ 115 #define IP_MU_BASE_ADDRS { IP_MU_0__MUB_BASE, IP_MU_1__MUB_BASE } 116 /** Array initializer of MU peripheral base pointers */ 117 #define IP_MU_BASE_PTRS { IP_MU_0__MUB, IP_MU_1__MUB } 118 119 /* ---------------------------------------------------------------------------- 120 -- MU Register Masks 121 ---------------------------------------------------------------------------- */ 122 123 /*! 124 * @addtogroup MU_Register_Masks MU Register Masks 125 * @{ 126 */ 127 128 /*! @name VER - Version ID Register */ 129 /*! @{ */ 130 131 #define MU_VER_FEATURE_MASK (0xFFFFU) 132 #define MU_VER_FEATURE_SHIFT (0U) 133 #define MU_VER_FEATURE_WIDTH (16U) 134 #define MU_VER_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_FEATURE_SHIFT)) & MU_VER_FEATURE_MASK) 135 136 #define MU_VER_MINOR_MASK (0xFF0000U) 137 #define MU_VER_MINOR_SHIFT (16U) 138 #define MU_VER_MINOR_WIDTH (8U) 139 #define MU_VER_MINOR(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_MINOR_SHIFT)) & MU_VER_MINOR_MASK) 140 141 #define MU_VER_MAJOR_MASK (0xFF000000U) 142 #define MU_VER_MAJOR_SHIFT (24U) 143 #define MU_VER_MAJOR_WIDTH (8U) 144 #define MU_VER_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_MAJOR_SHIFT)) & MU_VER_MAJOR_MASK) 145 /*! @} */ 146 147 /*! @name PAR - Parameter Register */ 148 /*! @{ */ 149 150 #define MU_PAR_TR_NUM_MASK (0xFFU) 151 #define MU_PAR_TR_NUM_SHIFT (0U) 152 #define MU_PAR_TR_NUM_WIDTH (8U) 153 #define MU_PAR_TR_NUM(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_TR_NUM_SHIFT)) & MU_PAR_TR_NUM_MASK) 154 155 #define MU_PAR_RR_NUM_MASK (0xFF00U) 156 #define MU_PAR_RR_NUM_SHIFT (8U) 157 #define MU_PAR_RR_NUM_WIDTH (8U) 158 #define MU_PAR_RR_NUM(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_RR_NUM_SHIFT)) & MU_PAR_RR_NUM_MASK) 159 160 #define MU_PAR_GIR_NUM_MASK (0xFF0000U) 161 #define MU_PAR_GIR_NUM_SHIFT (16U) 162 #define MU_PAR_GIR_NUM_WIDTH (8U) 163 #define MU_PAR_GIR_NUM(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_GIR_NUM_SHIFT)) & MU_PAR_GIR_NUM_MASK) 164 165 #define MU_PAR_FLAG_WIDTH_MASK (0xFF000000U) 166 #define MU_PAR_FLAG_WIDTH_SHIFT (24U) 167 #define MU_PAR_FLAG_WIDTH_WIDTH (8U) 168 #define MU_PAR_FLAG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_FLAG_WIDTH_SHIFT)) & MU_PAR_FLAG_WIDTH_MASK) 169 /*! @} */ 170 171 /*! @name CR - Control Register */ 172 /*! @{ */ 173 174 #define MU_CR_MUR_MASK (0x1U) 175 #define MU_CR_MUR_SHIFT (0U) 176 #define MU_CR_MUR_WIDTH (1U) 177 #define MU_CR_MUR(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK) 178 179 #define MU_CR_MURIE_MASK (0x2U) 180 #define MU_CR_MURIE_SHIFT (1U) 181 #define MU_CR_MURIE_WIDTH (1U) 182 #define MU_CR_MURIE(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MURIE_SHIFT)) & MU_CR_MURIE_MASK) 183 /*! @} */ 184 185 /*! @name SR - Status Register */ 186 /*! @{ */ 187 188 #define MU_SR_MURS_MASK (0x1U) 189 #define MU_SR_MURS_SHIFT (0U) 190 #define MU_SR_MURS_WIDTH (1U) 191 #define MU_SR_MURS(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_MURS_SHIFT)) & MU_SR_MURS_MASK) 192 193 #define MU_SR_MURIP_MASK (0x2U) 194 #define MU_SR_MURIP_SHIFT (1U) 195 #define MU_SR_MURIP_WIDTH (1U) 196 #define MU_SR_MURIP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_MURIP_SHIFT)) & MU_SR_MURIP_MASK) 197 198 #define MU_SR_EP_MASK (0x4U) 199 #define MU_SR_EP_SHIFT (2U) 200 #define MU_SR_EP_WIDTH (1U) 201 #define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK) 202 203 #define MU_SR_FUP_MASK (0x8U) 204 #define MU_SR_FUP_SHIFT (3U) 205 #define MU_SR_FUP_WIDTH (1U) 206 #define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK) 207 208 #define MU_SR_GIRP_MASK (0x10U) 209 #define MU_SR_GIRP_SHIFT (4U) 210 #define MU_SR_GIRP_WIDTH (1U) 211 #define MU_SR_GIRP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIRP_SHIFT)) & MU_SR_GIRP_MASK) 212 213 #define MU_SR_TEP_MASK (0x20U) 214 #define MU_SR_TEP_SHIFT (5U) 215 #define MU_SR_TEP_WIDTH (1U) 216 #define MU_SR_TEP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEP_SHIFT)) & MU_SR_TEP_MASK) 217 218 #define MU_SR_RFP_MASK (0x40U) 219 #define MU_SR_RFP_SHIFT (6U) 220 #define MU_SR_RFP_WIDTH (1U) 221 #define MU_SR_RFP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFP_SHIFT)) & MU_SR_RFP_MASK) 222 /*! @} */ 223 224 /*! @name CCR0 - Core Control Register 0 */ 225 /*! @{ */ 226 227 #define MU_CCR0_NMI_MASK (0x1U) 228 #define MU_CCR0_NMI_SHIFT (0U) 229 #define MU_CCR0_NMI_WIDTH (1U) 230 #define MU_CCR0_NMI(x) (((uint32_t)(((uint32_t)(x)) << MU_CCR0_NMI_SHIFT)) & MU_CCR0_NMI_MASK) 231 /*! @} */ 232 233 /*! @name CSSR0 - Core Sticky Status Register 0 */ 234 /*! @{ */ 235 236 #define MU_CSSR0_NMIC_MASK (0x1U) 237 #define MU_CSSR0_NMIC_SHIFT (0U) 238 #define MU_CSSR0_NMIC_WIDTH (1U) 239 #define MU_CSSR0_NMIC(x) (((uint32_t)(((uint32_t)(x)) << MU_CSSR0_NMIC_SHIFT)) & MU_CSSR0_NMIC_MASK) 240 /*! @} */ 241 242 /*! @name FCR - Flag Control Register */ 243 /*! @{ */ 244 245 #define MU_FCR_F0_MASK (0x1U) 246 #define MU_FCR_F0_SHIFT (0U) 247 #define MU_FCR_F0_WIDTH (1U) 248 #define MU_FCR_F0(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F0_SHIFT)) & MU_FCR_F0_MASK) 249 250 #define MU_FCR_F1_MASK (0x2U) 251 #define MU_FCR_F1_SHIFT (1U) 252 #define MU_FCR_F1_WIDTH (1U) 253 #define MU_FCR_F1(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F1_SHIFT)) & MU_FCR_F1_MASK) 254 255 #define MU_FCR_F2_MASK (0x4U) 256 #define MU_FCR_F2_SHIFT (2U) 257 #define MU_FCR_F2_WIDTH (1U) 258 #define MU_FCR_F2(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F2_SHIFT)) & MU_FCR_F2_MASK) 259 260 #define MU_FCR_F3_MASK (0x8U) 261 #define MU_FCR_F3_SHIFT (3U) 262 #define MU_FCR_F3_WIDTH (1U) 263 #define MU_FCR_F3(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F3_SHIFT)) & MU_FCR_F3_MASK) 264 265 #define MU_FCR_F4_MASK (0x10U) 266 #define MU_FCR_F4_SHIFT (4U) 267 #define MU_FCR_F4_WIDTH (1U) 268 #define MU_FCR_F4(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F4_SHIFT)) & MU_FCR_F4_MASK) 269 270 #define MU_FCR_F5_MASK (0x20U) 271 #define MU_FCR_F5_SHIFT (5U) 272 #define MU_FCR_F5_WIDTH (1U) 273 #define MU_FCR_F5(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F5_SHIFT)) & MU_FCR_F5_MASK) 274 275 #define MU_FCR_F6_MASK (0x40U) 276 #define MU_FCR_F6_SHIFT (6U) 277 #define MU_FCR_F6_WIDTH (1U) 278 #define MU_FCR_F6(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F6_SHIFT)) & MU_FCR_F6_MASK) 279 280 #define MU_FCR_F7_MASK (0x80U) 281 #define MU_FCR_F7_SHIFT (7U) 282 #define MU_FCR_F7_WIDTH (1U) 283 #define MU_FCR_F7(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F7_SHIFT)) & MU_FCR_F7_MASK) 284 285 #define MU_FCR_F8_MASK (0x100U) 286 #define MU_FCR_F8_SHIFT (8U) 287 #define MU_FCR_F8_WIDTH (1U) 288 #define MU_FCR_F8(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F8_SHIFT)) & MU_FCR_F8_MASK) 289 290 #define MU_FCR_F9_MASK (0x200U) 291 #define MU_FCR_F9_SHIFT (9U) 292 #define MU_FCR_F9_WIDTH (1U) 293 #define MU_FCR_F9(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F9_SHIFT)) & MU_FCR_F9_MASK) 294 295 #define MU_FCR_F10_MASK (0x400U) 296 #define MU_FCR_F10_SHIFT (10U) 297 #define MU_FCR_F10_WIDTH (1U) 298 #define MU_FCR_F10(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F10_SHIFT)) & MU_FCR_F10_MASK) 299 300 #define MU_FCR_F11_MASK (0x800U) 301 #define MU_FCR_F11_SHIFT (11U) 302 #define MU_FCR_F11_WIDTH (1U) 303 #define MU_FCR_F11(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F11_SHIFT)) & MU_FCR_F11_MASK) 304 305 #define MU_FCR_F12_MASK (0x1000U) 306 #define MU_FCR_F12_SHIFT (12U) 307 #define MU_FCR_F12_WIDTH (1U) 308 #define MU_FCR_F12(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F12_SHIFT)) & MU_FCR_F12_MASK) 309 310 #define MU_FCR_F13_MASK (0x2000U) 311 #define MU_FCR_F13_SHIFT (13U) 312 #define MU_FCR_F13_WIDTH (1U) 313 #define MU_FCR_F13(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F13_SHIFT)) & MU_FCR_F13_MASK) 314 315 #define MU_FCR_F14_MASK (0x4000U) 316 #define MU_FCR_F14_SHIFT (14U) 317 #define MU_FCR_F14_WIDTH (1U) 318 #define MU_FCR_F14(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F14_SHIFT)) & MU_FCR_F14_MASK) 319 320 #define MU_FCR_F15_MASK (0x8000U) 321 #define MU_FCR_F15_SHIFT (15U) 322 #define MU_FCR_F15_WIDTH (1U) 323 #define MU_FCR_F15(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F15_SHIFT)) & MU_FCR_F15_MASK) 324 325 #define MU_FCR_F16_MASK (0x10000U) 326 #define MU_FCR_F16_SHIFT (16U) 327 #define MU_FCR_F16_WIDTH (1U) 328 #define MU_FCR_F16(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F16_SHIFT)) & MU_FCR_F16_MASK) 329 330 #define MU_FCR_F17_MASK (0x20000U) 331 #define MU_FCR_F17_SHIFT (17U) 332 #define MU_FCR_F17_WIDTH (1U) 333 #define MU_FCR_F17(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F17_SHIFT)) & MU_FCR_F17_MASK) 334 335 #define MU_FCR_F18_MASK (0x40000U) 336 #define MU_FCR_F18_SHIFT (18U) 337 #define MU_FCR_F18_WIDTH (1U) 338 #define MU_FCR_F18(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F18_SHIFT)) & MU_FCR_F18_MASK) 339 340 #define MU_FCR_F19_MASK (0x80000U) 341 #define MU_FCR_F19_SHIFT (19U) 342 #define MU_FCR_F19_WIDTH (1U) 343 #define MU_FCR_F19(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F19_SHIFT)) & MU_FCR_F19_MASK) 344 345 #define MU_FCR_F20_MASK (0x100000U) 346 #define MU_FCR_F20_SHIFT (20U) 347 #define MU_FCR_F20_WIDTH (1U) 348 #define MU_FCR_F20(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F20_SHIFT)) & MU_FCR_F20_MASK) 349 350 #define MU_FCR_F21_MASK (0x200000U) 351 #define MU_FCR_F21_SHIFT (21U) 352 #define MU_FCR_F21_WIDTH (1U) 353 #define MU_FCR_F21(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F21_SHIFT)) & MU_FCR_F21_MASK) 354 355 #define MU_FCR_F22_MASK (0x400000U) 356 #define MU_FCR_F22_SHIFT (22U) 357 #define MU_FCR_F22_WIDTH (1U) 358 #define MU_FCR_F22(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F22_SHIFT)) & MU_FCR_F22_MASK) 359 360 #define MU_FCR_F23_MASK (0x800000U) 361 #define MU_FCR_F23_SHIFT (23U) 362 #define MU_FCR_F23_WIDTH (1U) 363 #define MU_FCR_F23(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F23_SHIFT)) & MU_FCR_F23_MASK) 364 365 #define MU_FCR_F24_MASK (0x1000000U) 366 #define MU_FCR_F24_SHIFT (24U) 367 #define MU_FCR_F24_WIDTH (1U) 368 #define MU_FCR_F24(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F24_SHIFT)) & MU_FCR_F24_MASK) 369 370 #define MU_FCR_F25_MASK (0x2000000U) 371 #define MU_FCR_F25_SHIFT (25U) 372 #define MU_FCR_F25_WIDTH (1U) 373 #define MU_FCR_F25(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F25_SHIFT)) & MU_FCR_F25_MASK) 374 375 #define MU_FCR_F26_MASK (0x4000000U) 376 #define MU_FCR_F26_SHIFT (26U) 377 #define MU_FCR_F26_WIDTH (1U) 378 #define MU_FCR_F26(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F26_SHIFT)) & MU_FCR_F26_MASK) 379 380 #define MU_FCR_F27_MASK (0x8000000U) 381 #define MU_FCR_F27_SHIFT (27U) 382 #define MU_FCR_F27_WIDTH (1U) 383 #define MU_FCR_F27(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F27_SHIFT)) & MU_FCR_F27_MASK) 384 385 #define MU_FCR_F28_MASK (0x10000000U) 386 #define MU_FCR_F28_SHIFT (28U) 387 #define MU_FCR_F28_WIDTH (1U) 388 #define MU_FCR_F28(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F28_SHIFT)) & MU_FCR_F28_MASK) 389 390 #define MU_FCR_F29_MASK (0x20000000U) 391 #define MU_FCR_F29_SHIFT (29U) 392 #define MU_FCR_F29_WIDTH (1U) 393 #define MU_FCR_F29(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F29_SHIFT)) & MU_FCR_F29_MASK) 394 395 #define MU_FCR_F30_MASK (0x40000000U) 396 #define MU_FCR_F30_SHIFT (30U) 397 #define MU_FCR_F30_WIDTH (1U) 398 #define MU_FCR_F30(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F30_SHIFT)) & MU_FCR_F30_MASK) 399 400 #define MU_FCR_F31_MASK (0x80000000U) 401 #define MU_FCR_F31_SHIFT (31U) 402 #define MU_FCR_F31_WIDTH (1U) 403 #define MU_FCR_F31(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F31_SHIFT)) & MU_FCR_F31_MASK) 404 /*! @} */ 405 406 /*! @name FSR - Flag Status Register */ 407 /*! @{ */ 408 409 #define MU_FSR_F0_MASK (0x1U) 410 #define MU_FSR_F0_SHIFT (0U) 411 #define MU_FSR_F0_WIDTH (1U) 412 #define MU_FSR_F0(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F0_SHIFT)) & MU_FSR_F0_MASK) 413 414 #define MU_FSR_F1_MASK (0x2U) 415 #define MU_FSR_F1_SHIFT (1U) 416 #define MU_FSR_F1_WIDTH (1U) 417 #define MU_FSR_F1(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F1_SHIFT)) & MU_FSR_F1_MASK) 418 419 #define MU_FSR_F2_MASK (0x4U) 420 #define MU_FSR_F2_SHIFT (2U) 421 #define MU_FSR_F2_WIDTH (1U) 422 #define MU_FSR_F2(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F2_SHIFT)) & MU_FSR_F2_MASK) 423 424 #define MU_FSR_F3_MASK (0x8U) 425 #define MU_FSR_F3_SHIFT (3U) 426 #define MU_FSR_F3_WIDTH (1U) 427 #define MU_FSR_F3(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F3_SHIFT)) & MU_FSR_F3_MASK) 428 429 #define MU_FSR_F4_MASK (0x10U) 430 #define MU_FSR_F4_SHIFT (4U) 431 #define MU_FSR_F4_WIDTH (1U) 432 #define MU_FSR_F4(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F4_SHIFT)) & MU_FSR_F4_MASK) 433 434 #define MU_FSR_F5_MASK (0x20U) 435 #define MU_FSR_F5_SHIFT (5U) 436 #define MU_FSR_F5_WIDTH (1U) 437 #define MU_FSR_F5(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F5_SHIFT)) & MU_FSR_F5_MASK) 438 439 #define MU_FSR_F6_MASK (0x40U) 440 #define MU_FSR_F6_SHIFT (6U) 441 #define MU_FSR_F6_WIDTH (1U) 442 #define MU_FSR_F6(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F6_SHIFT)) & MU_FSR_F6_MASK) 443 444 #define MU_FSR_F7_MASK (0x80U) 445 #define MU_FSR_F7_SHIFT (7U) 446 #define MU_FSR_F7_WIDTH (1U) 447 #define MU_FSR_F7(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F7_SHIFT)) & MU_FSR_F7_MASK) 448 449 #define MU_FSR_F8_MASK (0x100U) 450 #define MU_FSR_F8_SHIFT (8U) 451 #define MU_FSR_F8_WIDTH (1U) 452 #define MU_FSR_F8(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F8_SHIFT)) & MU_FSR_F8_MASK) 453 454 #define MU_FSR_F9_MASK (0x200U) 455 #define MU_FSR_F9_SHIFT (9U) 456 #define MU_FSR_F9_WIDTH (1U) 457 #define MU_FSR_F9(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F9_SHIFT)) & MU_FSR_F9_MASK) 458 459 #define MU_FSR_F10_MASK (0x400U) 460 #define MU_FSR_F10_SHIFT (10U) 461 #define MU_FSR_F10_WIDTH (1U) 462 #define MU_FSR_F10(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F10_SHIFT)) & MU_FSR_F10_MASK) 463 464 #define MU_FSR_F11_MASK (0x800U) 465 #define MU_FSR_F11_SHIFT (11U) 466 #define MU_FSR_F11_WIDTH (1U) 467 #define MU_FSR_F11(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F11_SHIFT)) & MU_FSR_F11_MASK) 468 469 #define MU_FSR_F12_MASK (0x1000U) 470 #define MU_FSR_F12_SHIFT (12U) 471 #define MU_FSR_F12_WIDTH (1U) 472 #define MU_FSR_F12(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F12_SHIFT)) & MU_FSR_F12_MASK) 473 474 #define MU_FSR_F13_MASK (0x2000U) 475 #define MU_FSR_F13_SHIFT (13U) 476 #define MU_FSR_F13_WIDTH (1U) 477 #define MU_FSR_F13(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F13_SHIFT)) & MU_FSR_F13_MASK) 478 479 #define MU_FSR_F14_MASK (0x4000U) 480 #define MU_FSR_F14_SHIFT (14U) 481 #define MU_FSR_F14_WIDTH (1U) 482 #define MU_FSR_F14(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F14_SHIFT)) & MU_FSR_F14_MASK) 483 484 #define MU_FSR_F15_MASK (0x8000U) 485 #define MU_FSR_F15_SHIFT (15U) 486 #define MU_FSR_F15_WIDTH (1U) 487 #define MU_FSR_F15(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F15_SHIFT)) & MU_FSR_F15_MASK) 488 489 #define MU_FSR_F16_MASK (0x10000U) 490 #define MU_FSR_F16_SHIFT (16U) 491 #define MU_FSR_F16_WIDTH (1U) 492 #define MU_FSR_F16(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F16_SHIFT)) & MU_FSR_F16_MASK) 493 494 #define MU_FSR_F17_MASK (0x20000U) 495 #define MU_FSR_F17_SHIFT (17U) 496 #define MU_FSR_F17_WIDTH (1U) 497 #define MU_FSR_F17(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F17_SHIFT)) & MU_FSR_F17_MASK) 498 499 #define MU_FSR_F18_MASK (0x40000U) 500 #define MU_FSR_F18_SHIFT (18U) 501 #define MU_FSR_F18_WIDTH (1U) 502 #define MU_FSR_F18(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F18_SHIFT)) & MU_FSR_F18_MASK) 503 504 #define MU_FSR_F19_MASK (0x80000U) 505 #define MU_FSR_F19_SHIFT (19U) 506 #define MU_FSR_F19_WIDTH (1U) 507 #define MU_FSR_F19(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F19_SHIFT)) & MU_FSR_F19_MASK) 508 509 #define MU_FSR_F20_MASK (0x100000U) 510 #define MU_FSR_F20_SHIFT (20U) 511 #define MU_FSR_F20_WIDTH (1U) 512 #define MU_FSR_F20(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F20_SHIFT)) & MU_FSR_F20_MASK) 513 514 #define MU_FSR_F21_MASK (0x200000U) 515 #define MU_FSR_F21_SHIFT (21U) 516 #define MU_FSR_F21_WIDTH (1U) 517 #define MU_FSR_F21(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F21_SHIFT)) & MU_FSR_F21_MASK) 518 519 #define MU_FSR_F22_MASK (0x400000U) 520 #define MU_FSR_F22_SHIFT (22U) 521 #define MU_FSR_F22_WIDTH (1U) 522 #define MU_FSR_F22(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F22_SHIFT)) & MU_FSR_F22_MASK) 523 524 #define MU_FSR_F23_MASK (0x800000U) 525 #define MU_FSR_F23_SHIFT (23U) 526 #define MU_FSR_F23_WIDTH (1U) 527 #define MU_FSR_F23(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F23_SHIFT)) & MU_FSR_F23_MASK) 528 529 #define MU_FSR_F24_MASK (0x1000000U) 530 #define MU_FSR_F24_SHIFT (24U) 531 #define MU_FSR_F24_WIDTH (1U) 532 #define MU_FSR_F24(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F24_SHIFT)) & MU_FSR_F24_MASK) 533 534 #define MU_FSR_F25_MASK (0x2000000U) 535 #define MU_FSR_F25_SHIFT (25U) 536 #define MU_FSR_F25_WIDTH (1U) 537 #define MU_FSR_F25(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F25_SHIFT)) & MU_FSR_F25_MASK) 538 539 #define MU_FSR_F26_MASK (0x4000000U) 540 #define MU_FSR_F26_SHIFT (26U) 541 #define MU_FSR_F26_WIDTH (1U) 542 #define MU_FSR_F26(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F26_SHIFT)) & MU_FSR_F26_MASK) 543 544 #define MU_FSR_F27_MASK (0x8000000U) 545 #define MU_FSR_F27_SHIFT (27U) 546 #define MU_FSR_F27_WIDTH (1U) 547 #define MU_FSR_F27(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F27_SHIFT)) & MU_FSR_F27_MASK) 548 549 #define MU_FSR_F28_MASK (0x10000000U) 550 #define MU_FSR_F28_SHIFT (28U) 551 #define MU_FSR_F28_WIDTH (1U) 552 #define MU_FSR_F28(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F28_SHIFT)) & MU_FSR_F28_MASK) 553 554 #define MU_FSR_F29_MASK (0x20000000U) 555 #define MU_FSR_F29_SHIFT (29U) 556 #define MU_FSR_F29_WIDTH (1U) 557 #define MU_FSR_F29(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F29_SHIFT)) & MU_FSR_F29_MASK) 558 559 #define MU_FSR_F30_MASK (0x40000000U) 560 #define MU_FSR_F30_SHIFT (30U) 561 #define MU_FSR_F30_WIDTH (1U) 562 #define MU_FSR_F30(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F30_SHIFT)) & MU_FSR_F30_MASK) 563 564 #define MU_FSR_F31_MASK (0x80000000U) 565 #define MU_FSR_F31_SHIFT (31U) 566 #define MU_FSR_F31_WIDTH (1U) 567 #define MU_FSR_F31(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F31_SHIFT)) & MU_FSR_F31_MASK) 568 /*! @} */ 569 570 /*! @name GIER - General Interrupt Enable Register */ 571 /*! @{ */ 572 573 #define MU_GIER_GIE0_MASK (0x1U) 574 #define MU_GIER_GIE0_SHIFT (0U) 575 #define MU_GIER_GIE0_WIDTH (1U) 576 #define MU_GIER_GIE0(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE0_SHIFT)) & MU_GIER_GIE0_MASK) 577 578 #define MU_GIER_GIE1_MASK (0x2U) 579 #define MU_GIER_GIE1_SHIFT (1U) 580 #define MU_GIER_GIE1_WIDTH (1U) 581 #define MU_GIER_GIE1(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE1_SHIFT)) & MU_GIER_GIE1_MASK) 582 583 #define MU_GIER_GIE2_MASK (0x4U) 584 #define MU_GIER_GIE2_SHIFT (2U) 585 #define MU_GIER_GIE2_WIDTH (1U) 586 #define MU_GIER_GIE2(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE2_SHIFT)) & MU_GIER_GIE2_MASK) 587 588 #define MU_GIER_GIE3_MASK (0x8U) 589 #define MU_GIER_GIE3_SHIFT (3U) 590 #define MU_GIER_GIE3_WIDTH (1U) 591 #define MU_GIER_GIE3(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE3_SHIFT)) & MU_GIER_GIE3_MASK) 592 593 #define MU_GIER_GIE4_MASK (0x10U) 594 #define MU_GIER_GIE4_SHIFT (4U) 595 #define MU_GIER_GIE4_WIDTH (1U) 596 #define MU_GIER_GIE4(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE4_SHIFT)) & MU_GIER_GIE4_MASK) 597 598 #define MU_GIER_GIE5_MASK (0x20U) 599 #define MU_GIER_GIE5_SHIFT (5U) 600 #define MU_GIER_GIE5_WIDTH (1U) 601 #define MU_GIER_GIE5(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE5_SHIFT)) & MU_GIER_GIE5_MASK) 602 603 #define MU_GIER_GIE6_MASK (0x40U) 604 #define MU_GIER_GIE6_SHIFT (6U) 605 #define MU_GIER_GIE6_WIDTH (1U) 606 #define MU_GIER_GIE6(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE6_SHIFT)) & MU_GIER_GIE6_MASK) 607 608 #define MU_GIER_GIE7_MASK (0x80U) 609 #define MU_GIER_GIE7_SHIFT (7U) 610 #define MU_GIER_GIE7_WIDTH (1U) 611 #define MU_GIER_GIE7(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE7_SHIFT)) & MU_GIER_GIE7_MASK) 612 613 #define MU_GIER_GIE8_MASK (0x100U) 614 #define MU_GIER_GIE8_SHIFT (8U) 615 #define MU_GIER_GIE8_WIDTH (1U) 616 #define MU_GIER_GIE8(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE8_SHIFT)) & MU_GIER_GIE8_MASK) 617 618 #define MU_GIER_GIE9_MASK (0x200U) 619 #define MU_GIER_GIE9_SHIFT (9U) 620 #define MU_GIER_GIE9_WIDTH (1U) 621 #define MU_GIER_GIE9(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE9_SHIFT)) & MU_GIER_GIE9_MASK) 622 623 #define MU_GIER_GIE10_MASK (0x400U) 624 #define MU_GIER_GIE10_SHIFT (10U) 625 #define MU_GIER_GIE10_WIDTH (1U) 626 #define MU_GIER_GIE10(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE10_SHIFT)) & MU_GIER_GIE10_MASK) 627 628 #define MU_GIER_GIE11_MASK (0x800U) 629 #define MU_GIER_GIE11_SHIFT (11U) 630 #define MU_GIER_GIE11_WIDTH (1U) 631 #define MU_GIER_GIE11(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE11_SHIFT)) & MU_GIER_GIE11_MASK) 632 633 #define MU_GIER_GIE12_MASK (0x1000U) 634 #define MU_GIER_GIE12_SHIFT (12U) 635 #define MU_GIER_GIE12_WIDTH (1U) 636 #define MU_GIER_GIE12(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE12_SHIFT)) & MU_GIER_GIE12_MASK) 637 638 #define MU_GIER_GIE13_MASK (0x2000U) 639 #define MU_GIER_GIE13_SHIFT (13U) 640 #define MU_GIER_GIE13_WIDTH (1U) 641 #define MU_GIER_GIE13(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE13_SHIFT)) & MU_GIER_GIE13_MASK) 642 643 #define MU_GIER_GIE14_MASK (0x4000U) 644 #define MU_GIER_GIE14_SHIFT (14U) 645 #define MU_GIER_GIE14_WIDTH (1U) 646 #define MU_GIER_GIE14(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE14_SHIFT)) & MU_GIER_GIE14_MASK) 647 648 #define MU_GIER_GIE15_MASK (0x8000U) 649 #define MU_GIER_GIE15_SHIFT (15U) 650 #define MU_GIER_GIE15_WIDTH (1U) 651 #define MU_GIER_GIE15(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE15_SHIFT)) & MU_GIER_GIE15_MASK) 652 653 #define MU_GIER_GIE16_MASK (0x10000U) 654 #define MU_GIER_GIE16_SHIFT (16U) 655 #define MU_GIER_GIE16_WIDTH (1U) 656 #define MU_GIER_GIE16(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE16_SHIFT)) & MU_GIER_GIE16_MASK) 657 658 #define MU_GIER_GIE17_MASK (0x20000U) 659 #define MU_GIER_GIE17_SHIFT (17U) 660 #define MU_GIER_GIE17_WIDTH (1U) 661 #define MU_GIER_GIE17(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE17_SHIFT)) & MU_GIER_GIE17_MASK) 662 663 #define MU_GIER_GIE18_MASK (0x40000U) 664 #define MU_GIER_GIE18_SHIFT (18U) 665 #define MU_GIER_GIE18_WIDTH (1U) 666 #define MU_GIER_GIE18(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE18_SHIFT)) & MU_GIER_GIE18_MASK) 667 668 #define MU_GIER_GIE19_MASK (0x80000U) 669 #define MU_GIER_GIE19_SHIFT (19U) 670 #define MU_GIER_GIE19_WIDTH (1U) 671 #define MU_GIER_GIE19(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE19_SHIFT)) & MU_GIER_GIE19_MASK) 672 673 #define MU_GIER_GIE20_MASK (0x100000U) 674 #define MU_GIER_GIE20_SHIFT (20U) 675 #define MU_GIER_GIE20_WIDTH (1U) 676 #define MU_GIER_GIE20(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE20_SHIFT)) & MU_GIER_GIE20_MASK) 677 678 #define MU_GIER_GIE21_MASK (0x200000U) 679 #define MU_GIER_GIE21_SHIFT (21U) 680 #define MU_GIER_GIE21_WIDTH (1U) 681 #define MU_GIER_GIE21(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE21_SHIFT)) & MU_GIER_GIE21_MASK) 682 683 #define MU_GIER_GIE22_MASK (0x400000U) 684 #define MU_GIER_GIE22_SHIFT (22U) 685 #define MU_GIER_GIE22_WIDTH (1U) 686 #define MU_GIER_GIE22(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE22_SHIFT)) & MU_GIER_GIE22_MASK) 687 688 #define MU_GIER_GIE23_MASK (0x800000U) 689 #define MU_GIER_GIE23_SHIFT (23U) 690 #define MU_GIER_GIE23_WIDTH (1U) 691 #define MU_GIER_GIE23(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE23_SHIFT)) & MU_GIER_GIE23_MASK) 692 693 #define MU_GIER_GIE24_MASK (0x1000000U) 694 #define MU_GIER_GIE24_SHIFT (24U) 695 #define MU_GIER_GIE24_WIDTH (1U) 696 #define MU_GIER_GIE24(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE24_SHIFT)) & MU_GIER_GIE24_MASK) 697 698 #define MU_GIER_GIE25_MASK (0x2000000U) 699 #define MU_GIER_GIE25_SHIFT (25U) 700 #define MU_GIER_GIE25_WIDTH (1U) 701 #define MU_GIER_GIE25(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE25_SHIFT)) & MU_GIER_GIE25_MASK) 702 703 #define MU_GIER_GIE26_MASK (0x4000000U) 704 #define MU_GIER_GIE26_SHIFT (26U) 705 #define MU_GIER_GIE26_WIDTH (1U) 706 #define MU_GIER_GIE26(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE26_SHIFT)) & MU_GIER_GIE26_MASK) 707 708 #define MU_GIER_GIE27_MASK (0x8000000U) 709 #define MU_GIER_GIE27_SHIFT (27U) 710 #define MU_GIER_GIE27_WIDTH (1U) 711 #define MU_GIER_GIE27(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE27_SHIFT)) & MU_GIER_GIE27_MASK) 712 713 #define MU_GIER_GIE28_MASK (0x10000000U) 714 #define MU_GIER_GIE28_SHIFT (28U) 715 #define MU_GIER_GIE28_WIDTH (1U) 716 #define MU_GIER_GIE28(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE28_SHIFT)) & MU_GIER_GIE28_MASK) 717 718 #define MU_GIER_GIE29_MASK (0x20000000U) 719 #define MU_GIER_GIE29_SHIFT (29U) 720 #define MU_GIER_GIE29_WIDTH (1U) 721 #define MU_GIER_GIE29(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE29_SHIFT)) & MU_GIER_GIE29_MASK) 722 723 #define MU_GIER_GIE30_MASK (0x40000000U) 724 #define MU_GIER_GIE30_SHIFT (30U) 725 #define MU_GIER_GIE30_WIDTH (1U) 726 #define MU_GIER_GIE30(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE30_SHIFT)) & MU_GIER_GIE30_MASK) 727 728 #define MU_GIER_GIE31_MASK (0x80000000U) 729 #define MU_GIER_GIE31_SHIFT (31U) 730 #define MU_GIER_GIE31_WIDTH (1U) 731 #define MU_GIER_GIE31(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE31_SHIFT)) & MU_GIER_GIE31_MASK) 732 /*! @} */ 733 734 /*! @name GCR - General Control Register */ 735 /*! @{ */ 736 737 #define MU_GCR_GIR0_MASK (0x1U) 738 #define MU_GCR_GIR0_SHIFT (0U) 739 #define MU_GCR_GIR0_WIDTH (1U) 740 #define MU_GCR_GIR0(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR0_SHIFT)) & MU_GCR_GIR0_MASK) 741 742 #define MU_GCR_GIR1_MASK (0x2U) 743 #define MU_GCR_GIR1_SHIFT (1U) 744 #define MU_GCR_GIR1_WIDTH (1U) 745 #define MU_GCR_GIR1(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR1_SHIFT)) & MU_GCR_GIR1_MASK) 746 747 #define MU_GCR_GIR2_MASK (0x4U) 748 #define MU_GCR_GIR2_SHIFT (2U) 749 #define MU_GCR_GIR2_WIDTH (1U) 750 #define MU_GCR_GIR2(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR2_SHIFT)) & MU_GCR_GIR2_MASK) 751 752 #define MU_GCR_GIR3_MASK (0x8U) 753 #define MU_GCR_GIR3_SHIFT (3U) 754 #define MU_GCR_GIR3_WIDTH (1U) 755 #define MU_GCR_GIR3(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR3_SHIFT)) & MU_GCR_GIR3_MASK) 756 757 #define MU_GCR_GIR4_MASK (0x10U) 758 #define MU_GCR_GIR4_SHIFT (4U) 759 #define MU_GCR_GIR4_WIDTH (1U) 760 #define MU_GCR_GIR4(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR4_SHIFT)) & MU_GCR_GIR4_MASK) 761 762 #define MU_GCR_GIR5_MASK (0x20U) 763 #define MU_GCR_GIR5_SHIFT (5U) 764 #define MU_GCR_GIR5_WIDTH (1U) 765 #define MU_GCR_GIR5(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR5_SHIFT)) & MU_GCR_GIR5_MASK) 766 767 #define MU_GCR_GIR6_MASK (0x40U) 768 #define MU_GCR_GIR6_SHIFT (6U) 769 #define MU_GCR_GIR6_WIDTH (1U) 770 #define MU_GCR_GIR6(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR6_SHIFT)) & MU_GCR_GIR6_MASK) 771 772 #define MU_GCR_GIR7_MASK (0x80U) 773 #define MU_GCR_GIR7_SHIFT (7U) 774 #define MU_GCR_GIR7_WIDTH (1U) 775 #define MU_GCR_GIR7(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR7_SHIFT)) & MU_GCR_GIR7_MASK) 776 777 #define MU_GCR_GIR8_MASK (0x100U) 778 #define MU_GCR_GIR8_SHIFT (8U) 779 #define MU_GCR_GIR8_WIDTH (1U) 780 #define MU_GCR_GIR8(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR8_SHIFT)) & MU_GCR_GIR8_MASK) 781 782 #define MU_GCR_GIR9_MASK (0x200U) 783 #define MU_GCR_GIR9_SHIFT (9U) 784 #define MU_GCR_GIR9_WIDTH (1U) 785 #define MU_GCR_GIR9(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR9_SHIFT)) & MU_GCR_GIR9_MASK) 786 787 #define MU_GCR_GIR10_MASK (0x400U) 788 #define MU_GCR_GIR10_SHIFT (10U) 789 #define MU_GCR_GIR10_WIDTH (1U) 790 #define MU_GCR_GIR10(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR10_SHIFT)) & MU_GCR_GIR10_MASK) 791 792 #define MU_GCR_GIR11_MASK (0x800U) 793 #define MU_GCR_GIR11_SHIFT (11U) 794 #define MU_GCR_GIR11_WIDTH (1U) 795 #define MU_GCR_GIR11(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR11_SHIFT)) & MU_GCR_GIR11_MASK) 796 797 #define MU_GCR_GIR12_MASK (0x1000U) 798 #define MU_GCR_GIR12_SHIFT (12U) 799 #define MU_GCR_GIR12_WIDTH (1U) 800 #define MU_GCR_GIR12(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR12_SHIFT)) & MU_GCR_GIR12_MASK) 801 802 #define MU_GCR_GIR13_MASK (0x2000U) 803 #define MU_GCR_GIR13_SHIFT (13U) 804 #define MU_GCR_GIR13_WIDTH (1U) 805 #define MU_GCR_GIR13(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR13_SHIFT)) & MU_GCR_GIR13_MASK) 806 807 #define MU_GCR_GIR14_MASK (0x4000U) 808 #define MU_GCR_GIR14_SHIFT (14U) 809 #define MU_GCR_GIR14_WIDTH (1U) 810 #define MU_GCR_GIR14(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR14_SHIFT)) & MU_GCR_GIR14_MASK) 811 812 #define MU_GCR_GIR15_MASK (0x8000U) 813 #define MU_GCR_GIR15_SHIFT (15U) 814 #define MU_GCR_GIR15_WIDTH (1U) 815 #define MU_GCR_GIR15(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR15_SHIFT)) & MU_GCR_GIR15_MASK) 816 817 #define MU_GCR_GIR16_MASK (0x10000U) 818 #define MU_GCR_GIR16_SHIFT (16U) 819 #define MU_GCR_GIR16_WIDTH (1U) 820 #define MU_GCR_GIR16(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR16_SHIFT)) & MU_GCR_GIR16_MASK) 821 822 #define MU_GCR_GIR17_MASK (0x20000U) 823 #define MU_GCR_GIR17_SHIFT (17U) 824 #define MU_GCR_GIR17_WIDTH (1U) 825 #define MU_GCR_GIR17(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR17_SHIFT)) & MU_GCR_GIR17_MASK) 826 827 #define MU_GCR_GIR18_MASK (0x40000U) 828 #define MU_GCR_GIR18_SHIFT (18U) 829 #define MU_GCR_GIR18_WIDTH (1U) 830 #define MU_GCR_GIR18(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR18_SHIFT)) & MU_GCR_GIR18_MASK) 831 832 #define MU_GCR_GIR19_MASK (0x80000U) 833 #define MU_GCR_GIR19_SHIFT (19U) 834 #define MU_GCR_GIR19_WIDTH (1U) 835 #define MU_GCR_GIR19(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR19_SHIFT)) & MU_GCR_GIR19_MASK) 836 837 #define MU_GCR_GIR20_MASK (0x100000U) 838 #define MU_GCR_GIR20_SHIFT (20U) 839 #define MU_GCR_GIR20_WIDTH (1U) 840 #define MU_GCR_GIR20(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR20_SHIFT)) & MU_GCR_GIR20_MASK) 841 842 #define MU_GCR_GIR21_MASK (0x200000U) 843 #define MU_GCR_GIR21_SHIFT (21U) 844 #define MU_GCR_GIR21_WIDTH (1U) 845 #define MU_GCR_GIR21(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR21_SHIFT)) & MU_GCR_GIR21_MASK) 846 847 #define MU_GCR_GIR22_MASK (0x400000U) 848 #define MU_GCR_GIR22_SHIFT (22U) 849 #define MU_GCR_GIR22_WIDTH (1U) 850 #define MU_GCR_GIR22(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR22_SHIFT)) & MU_GCR_GIR22_MASK) 851 852 #define MU_GCR_GIR23_MASK (0x800000U) 853 #define MU_GCR_GIR23_SHIFT (23U) 854 #define MU_GCR_GIR23_WIDTH (1U) 855 #define MU_GCR_GIR23(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR23_SHIFT)) & MU_GCR_GIR23_MASK) 856 857 #define MU_GCR_GIR24_MASK (0x1000000U) 858 #define MU_GCR_GIR24_SHIFT (24U) 859 #define MU_GCR_GIR24_WIDTH (1U) 860 #define MU_GCR_GIR24(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR24_SHIFT)) & MU_GCR_GIR24_MASK) 861 862 #define MU_GCR_GIR25_MASK (0x2000000U) 863 #define MU_GCR_GIR25_SHIFT (25U) 864 #define MU_GCR_GIR25_WIDTH (1U) 865 #define MU_GCR_GIR25(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR25_SHIFT)) & MU_GCR_GIR25_MASK) 866 867 #define MU_GCR_GIR26_MASK (0x4000000U) 868 #define MU_GCR_GIR26_SHIFT (26U) 869 #define MU_GCR_GIR26_WIDTH (1U) 870 #define MU_GCR_GIR26(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR26_SHIFT)) & MU_GCR_GIR26_MASK) 871 872 #define MU_GCR_GIR27_MASK (0x8000000U) 873 #define MU_GCR_GIR27_SHIFT (27U) 874 #define MU_GCR_GIR27_WIDTH (1U) 875 #define MU_GCR_GIR27(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR27_SHIFT)) & MU_GCR_GIR27_MASK) 876 877 #define MU_GCR_GIR28_MASK (0x10000000U) 878 #define MU_GCR_GIR28_SHIFT (28U) 879 #define MU_GCR_GIR28_WIDTH (1U) 880 #define MU_GCR_GIR28(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR28_SHIFT)) & MU_GCR_GIR28_MASK) 881 882 #define MU_GCR_GIR29_MASK (0x20000000U) 883 #define MU_GCR_GIR29_SHIFT (29U) 884 #define MU_GCR_GIR29_WIDTH (1U) 885 #define MU_GCR_GIR29(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR29_SHIFT)) & MU_GCR_GIR29_MASK) 886 887 #define MU_GCR_GIR30_MASK (0x40000000U) 888 #define MU_GCR_GIR30_SHIFT (30U) 889 #define MU_GCR_GIR30_WIDTH (1U) 890 #define MU_GCR_GIR30(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR30_SHIFT)) & MU_GCR_GIR30_MASK) 891 892 #define MU_GCR_GIR31_MASK (0x80000000U) 893 #define MU_GCR_GIR31_SHIFT (31U) 894 #define MU_GCR_GIR31_WIDTH (1U) 895 #define MU_GCR_GIR31(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR31_SHIFT)) & MU_GCR_GIR31_MASK) 896 /*! @} */ 897 898 /*! @name GSR - General Status Register */ 899 /*! @{ */ 900 901 #define MU_GSR_GIP0_MASK (0x1U) 902 #define MU_GSR_GIP0_SHIFT (0U) 903 #define MU_GSR_GIP0_WIDTH (1U) 904 #define MU_GSR_GIP0(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP0_SHIFT)) & MU_GSR_GIP0_MASK) 905 906 #define MU_GSR_GIP1_MASK (0x2U) 907 #define MU_GSR_GIP1_SHIFT (1U) 908 #define MU_GSR_GIP1_WIDTH (1U) 909 #define MU_GSR_GIP1(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP1_SHIFT)) & MU_GSR_GIP1_MASK) 910 911 #define MU_GSR_GIP2_MASK (0x4U) 912 #define MU_GSR_GIP2_SHIFT (2U) 913 #define MU_GSR_GIP2_WIDTH (1U) 914 #define MU_GSR_GIP2(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP2_SHIFT)) & MU_GSR_GIP2_MASK) 915 916 #define MU_GSR_GIP3_MASK (0x8U) 917 #define MU_GSR_GIP3_SHIFT (3U) 918 #define MU_GSR_GIP3_WIDTH (1U) 919 #define MU_GSR_GIP3(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP3_SHIFT)) & MU_GSR_GIP3_MASK) 920 921 #define MU_GSR_GIP4_MASK (0x10U) 922 #define MU_GSR_GIP4_SHIFT (4U) 923 #define MU_GSR_GIP4_WIDTH (1U) 924 #define MU_GSR_GIP4(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP4_SHIFT)) & MU_GSR_GIP4_MASK) 925 926 #define MU_GSR_GIP5_MASK (0x20U) 927 #define MU_GSR_GIP5_SHIFT (5U) 928 #define MU_GSR_GIP5_WIDTH (1U) 929 #define MU_GSR_GIP5(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP5_SHIFT)) & MU_GSR_GIP5_MASK) 930 931 #define MU_GSR_GIP6_MASK (0x40U) 932 #define MU_GSR_GIP6_SHIFT (6U) 933 #define MU_GSR_GIP6_WIDTH (1U) 934 #define MU_GSR_GIP6(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP6_SHIFT)) & MU_GSR_GIP6_MASK) 935 936 #define MU_GSR_GIP7_MASK (0x80U) 937 #define MU_GSR_GIP7_SHIFT (7U) 938 #define MU_GSR_GIP7_WIDTH (1U) 939 #define MU_GSR_GIP7(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP7_SHIFT)) & MU_GSR_GIP7_MASK) 940 941 #define MU_GSR_GIP8_MASK (0x100U) 942 #define MU_GSR_GIP8_SHIFT (8U) 943 #define MU_GSR_GIP8_WIDTH (1U) 944 #define MU_GSR_GIP8(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP8_SHIFT)) & MU_GSR_GIP8_MASK) 945 946 #define MU_GSR_GIP9_MASK (0x200U) 947 #define MU_GSR_GIP9_SHIFT (9U) 948 #define MU_GSR_GIP9_WIDTH (1U) 949 #define MU_GSR_GIP9(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP9_SHIFT)) & MU_GSR_GIP9_MASK) 950 951 #define MU_GSR_GIP10_MASK (0x400U) 952 #define MU_GSR_GIP10_SHIFT (10U) 953 #define MU_GSR_GIP10_WIDTH (1U) 954 #define MU_GSR_GIP10(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP10_SHIFT)) & MU_GSR_GIP10_MASK) 955 956 #define MU_GSR_GIP11_MASK (0x800U) 957 #define MU_GSR_GIP11_SHIFT (11U) 958 #define MU_GSR_GIP11_WIDTH (1U) 959 #define MU_GSR_GIP11(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP11_SHIFT)) & MU_GSR_GIP11_MASK) 960 961 #define MU_GSR_GIP12_MASK (0x1000U) 962 #define MU_GSR_GIP12_SHIFT (12U) 963 #define MU_GSR_GIP12_WIDTH (1U) 964 #define MU_GSR_GIP12(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP12_SHIFT)) & MU_GSR_GIP12_MASK) 965 966 #define MU_GSR_GIP13_MASK (0x2000U) 967 #define MU_GSR_GIP13_SHIFT (13U) 968 #define MU_GSR_GIP13_WIDTH (1U) 969 #define MU_GSR_GIP13(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP13_SHIFT)) & MU_GSR_GIP13_MASK) 970 971 #define MU_GSR_GIP14_MASK (0x4000U) 972 #define MU_GSR_GIP14_SHIFT (14U) 973 #define MU_GSR_GIP14_WIDTH (1U) 974 #define MU_GSR_GIP14(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP14_SHIFT)) & MU_GSR_GIP14_MASK) 975 976 #define MU_GSR_GIP15_MASK (0x8000U) 977 #define MU_GSR_GIP15_SHIFT (15U) 978 #define MU_GSR_GIP15_WIDTH (1U) 979 #define MU_GSR_GIP15(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP15_SHIFT)) & MU_GSR_GIP15_MASK) 980 981 #define MU_GSR_GIP16_MASK (0x10000U) 982 #define MU_GSR_GIP16_SHIFT (16U) 983 #define MU_GSR_GIP16_WIDTH (1U) 984 #define MU_GSR_GIP16(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP16_SHIFT)) & MU_GSR_GIP16_MASK) 985 986 #define MU_GSR_GIP17_MASK (0x20000U) 987 #define MU_GSR_GIP17_SHIFT (17U) 988 #define MU_GSR_GIP17_WIDTH (1U) 989 #define MU_GSR_GIP17(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP17_SHIFT)) & MU_GSR_GIP17_MASK) 990 991 #define MU_GSR_GIP18_MASK (0x40000U) 992 #define MU_GSR_GIP18_SHIFT (18U) 993 #define MU_GSR_GIP18_WIDTH (1U) 994 #define MU_GSR_GIP18(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP18_SHIFT)) & MU_GSR_GIP18_MASK) 995 996 #define MU_GSR_GIP19_MASK (0x80000U) 997 #define MU_GSR_GIP19_SHIFT (19U) 998 #define MU_GSR_GIP19_WIDTH (1U) 999 #define MU_GSR_GIP19(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP19_SHIFT)) & MU_GSR_GIP19_MASK) 1000 1001 #define MU_GSR_GIP20_MASK (0x100000U) 1002 #define MU_GSR_GIP20_SHIFT (20U) 1003 #define MU_GSR_GIP20_WIDTH (1U) 1004 #define MU_GSR_GIP20(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP20_SHIFT)) & MU_GSR_GIP20_MASK) 1005 1006 #define MU_GSR_GIP21_MASK (0x200000U) 1007 #define MU_GSR_GIP21_SHIFT (21U) 1008 #define MU_GSR_GIP21_WIDTH (1U) 1009 #define MU_GSR_GIP21(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP21_SHIFT)) & MU_GSR_GIP21_MASK) 1010 1011 #define MU_GSR_GIP22_MASK (0x400000U) 1012 #define MU_GSR_GIP22_SHIFT (22U) 1013 #define MU_GSR_GIP22_WIDTH (1U) 1014 #define MU_GSR_GIP22(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP22_SHIFT)) & MU_GSR_GIP22_MASK) 1015 1016 #define MU_GSR_GIP23_MASK (0x800000U) 1017 #define MU_GSR_GIP23_SHIFT (23U) 1018 #define MU_GSR_GIP23_WIDTH (1U) 1019 #define MU_GSR_GIP23(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP23_SHIFT)) & MU_GSR_GIP23_MASK) 1020 1021 #define MU_GSR_GIP24_MASK (0x1000000U) 1022 #define MU_GSR_GIP24_SHIFT (24U) 1023 #define MU_GSR_GIP24_WIDTH (1U) 1024 #define MU_GSR_GIP24(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP24_SHIFT)) & MU_GSR_GIP24_MASK) 1025 1026 #define MU_GSR_GIP25_MASK (0x2000000U) 1027 #define MU_GSR_GIP25_SHIFT (25U) 1028 #define MU_GSR_GIP25_WIDTH (1U) 1029 #define MU_GSR_GIP25(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP25_SHIFT)) & MU_GSR_GIP25_MASK) 1030 1031 #define MU_GSR_GIP26_MASK (0x4000000U) 1032 #define MU_GSR_GIP26_SHIFT (26U) 1033 #define MU_GSR_GIP26_WIDTH (1U) 1034 #define MU_GSR_GIP26(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP26_SHIFT)) & MU_GSR_GIP26_MASK) 1035 1036 #define MU_GSR_GIP27_MASK (0x8000000U) 1037 #define MU_GSR_GIP27_SHIFT (27U) 1038 #define MU_GSR_GIP27_WIDTH (1U) 1039 #define MU_GSR_GIP27(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP27_SHIFT)) & MU_GSR_GIP27_MASK) 1040 1041 #define MU_GSR_GIP28_MASK (0x10000000U) 1042 #define MU_GSR_GIP28_SHIFT (28U) 1043 #define MU_GSR_GIP28_WIDTH (1U) 1044 #define MU_GSR_GIP28(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP28_SHIFT)) & MU_GSR_GIP28_MASK) 1045 1046 #define MU_GSR_GIP29_MASK (0x20000000U) 1047 #define MU_GSR_GIP29_SHIFT (29U) 1048 #define MU_GSR_GIP29_WIDTH (1U) 1049 #define MU_GSR_GIP29(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP29_SHIFT)) & MU_GSR_GIP29_MASK) 1050 1051 #define MU_GSR_GIP30_MASK (0x40000000U) 1052 #define MU_GSR_GIP30_SHIFT (30U) 1053 #define MU_GSR_GIP30_WIDTH (1U) 1054 #define MU_GSR_GIP30(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP30_SHIFT)) & MU_GSR_GIP30_MASK) 1055 1056 #define MU_GSR_GIP31_MASK (0x80000000U) 1057 #define MU_GSR_GIP31_SHIFT (31U) 1058 #define MU_GSR_GIP31_WIDTH (1U) 1059 #define MU_GSR_GIP31(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP31_SHIFT)) & MU_GSR_GIP31_MASK) 1060 /*! @} */ 1061 1062 /*! @name TCR - Transmit Control Register */ 1063 /*! @{ */ 1064 1065 #define MU_TCR_TIE0_MASK (0x1U) 1066 #define MU_TCR_TIE0_SHIFT (0U) 1067 #define MU_TCR_TIE0_WIDTH (1U) 1068 #define MU_TCR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE0_SHIFT)) & MU_TCR_TIE0_MASK) 1069 1070 #define MU_TCR_TIE1_MASK (0x2U) 1071 #define MU_TCR_TIE1_SHIFT (1U) 1072 #define MU_TCR_TIE1_WIDTH (1U) 1073 #define MU_TCR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE1_SHIFT)) & MU_TCR_TIE1_MASK) 1074 1075 #define MU_TCR_TIE2_MASK (0x4U) 1076 #define MU_TCR_TIE2_SHIFT (2U) 1077 #define MU_TCR_TIE2_WIDTH (1U) 1078 #define MU_TCR_TIE2(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE2_SHIFT)) & MU_TCR_TIE2_MASK) 1079 1080 #define MU_TCR_TIE3_MASK (0x8U) 1081 #define MU_TCR_TIE3_SHIFT (3U) 1082 #define MU_TCR_TIE3_WIDTH (1U) 1083 #define MU_TCR_TIE3(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE3_SHIFT)) & MU_TCR_TIE3_MASK) 1084 /*! @} */ 1085 1086 /*! @name TSR - Transmit Status Register */ 1087 /*! @{ */ 1088 1089 #define MU_TSR_TE0_MASK (0x1U) 1090 #define MU_TSR_TE0_SHIFT (0U) 1091 #define MU_TSR_TE0_WIDTH (1U) 1092 #define MU_TSR_TE0(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE0_SHIFT)) & MU_TSR_TE0_MASK) 1093 1094 #define MU_TSR_TE1_MASK (0x2U) 1095 #define MU_TSR_TE1_SHIFT (1U) 1096 #define MU_TSR_TE1_WIDTH (1U) 1097 #define MU_TSR_TE1(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE1_SHIFT)) & MU_TSR_TE1_MASK) 1098 1099 #define MU_TSR_TE2_MASK (0x4U) 1100 #define MU_TSR_TE2_SHIFT (2U) 1101 #define MU_TSR_TE2_WIDTH (1U) 1102 #define MU_TSR_TE2(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE2_SHIFT)) & MU_TSR_TE2_MASK) 1103 1104 #define MU_TSR_TE3_MASK (0x8U) 1105 #define MU_TSR_TE3_SHIFT (3U) 1106 #define MU_TSR_TE3_WIDTH (1U) 1107 #define MU_TSR_TE3(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE3_SHIFT)) & MU_TSR_TE3_MASK) 1108 /*! @} */ 1109 1110 /*! @name RCR - Receive Control Register */ 1111 /*! @{ */ 1112 1113 #define MU_RCR_RIE0_MASK (0x1U) 1114 #define MU_RCR_RIE0_SHIFT (0U) 1115 #define MU_RCR_RIE0_WIDTH (1U) 1116 #define MU_RCR_RIE0(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE0_SHIFT)) & MU_RCR_RIE0_MASK) 1117 1118 #define MU_RCR_RIE1_MASK (0x2U) 1119 #define MU_RCR_RIE1_SHIFT (1U) 1120 #define MU_RCR_RIE1_WIDTH (1U) 1121 #define MU_RCR_RIE1(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE1_SHIFT)) & MU_RCR_RIE1_MASK) 1122 1123 #define MU_RCR_RIE2_MASK (0x4U) 1124 #define MU_RCR_RIE2_SHIFT (2U) 1125 #define MU_RCR_RIE2_WIDTH (1U) 1126 #define MU_RCR_RIE2(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE2_SHIFT)) & MU_RCR_RIE2_MASK) 1127 1128 #define MU_RCR_RIE3_MASK (0x8U) 1129 #define MU_RCR_RIE3_SHIFT (3U) 1130 #define MU_RCR_RIE3_WIDTH (1U) 1131 #define MU_RCR_RIE3(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE3_SHIFT)) & MU_RCR_RIE3_MASK) 1132 /*! @} */ 1133 1134 /*! @name RSR - Receive Status Register */ 1135 /*! @{ */ 1136 1137 #define MU_RSR_RF0_MASK (0x1U) 1138 #define MU_RSR_RF0_SHIFT (0U) 1139 #define MU_RSR_RF0_WIDTH (1U) 1140 #define MU_RSR_RF0(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF0_SHIFT)) & MU_RSR_RF0_MASK) 1141 1142 #define MU_RSR_RF1_MASK (0x2U) 1143 #define MU_RSR_RF1_SHIFT (1U) 1144 #define MU_RSR_RF1_WIDTH (1U) 1145 #define MU_RSR_RF1(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF1_SHIFT)) & MU_RSR_RF1_MASK) 1146 1147 #define MU_RSR_RF2_MASK (0x4U) 1148 #define MU_RSR_RF2_SHIFT (2U) 1149 #define MU_RSR_RF2_WIDTH (1U) 1150 #define MU_RSR_RF2(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF2_SHIFT)) & MU_RSR_RF2_MASK) 1151 1152 #define MU_RSR_RF3_MASK (0x8U) 1153 #define MU_RSR_RF3_SHIFT (3U) 1154 #define MU_RSR_RF3_WIDTH (1U) 1155 #define MU_RSR_RF3(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF3_SHIFT)) & MU_RSR_RF3_MASK) 1156 /*! @} */ 1157 1158 /*! @name TR - Transmit Register */ 1159 /*! @{ */ 1160 1161 #define MU_TR_TR_DATA_MASK (0xFFFFFFFFU) 1162 #define MU_TR_TR_DATA_SHIFT (0U) 1163 #define MU_TR_TR_DATA_WIDTH (32U) 1164 #define MU_TR_TR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_TR_DATA_SHIFT)) & MU_TR_TR_DATA_MASK) 1165 /*! @} */ 1166 1167 /*! @name RR - Receive Register */ 1168 /*! @{ */ 1169 1170 #define MU_RR_RR_DATA_MASK (0xFFFFFFFFU) 1171 #define MU_RR_RR_DATA_SHIFT (0U) 1172 #define MU_RR_RR_DATA_WIDTH (32U) 1173 #define MU_RR_RR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_RR_DATA_SHIFT)) & MU_RR_RR_DATA_MASK) 1174 /*! @} */ 1175 1176 /*! 1177 * @} 1178 */ /* end of group MU_Register_Masks */ 1179 1180 /*! 1181 * @} 1182 */ /* end of group MU_Peripheral_Access_Layer */ 1183 1184 #endif /* #if !defined(S32K344_MU_H_) */ 1185
