1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_MDM_AP.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_MDM_AP 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_MDM_AP_H_) /* Check if memory map has not been already included */ 58 #define S32K344_MDM_AP_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- MDM_AP Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup MDM_AP_Peripheral_Access_Layer MDM_AP Peripheral Access Layer 68 * @{ 69 */ 70 71 /** MDM_AP - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t MDMAPSTTS; /**< Status, offset: 0x0 */ 74 __IO uint32_t MDMAPCTL; /**< Control, offset: 0x4 */ 75 uint8_t RESERVED_0[40]; 76 __IO uint32_t MDMAPWIREN; /**< WIR Enable, offset: 0x30 */ 77 __I uint32_t MDMAPWIRSTTS; /**< WIR Status, offset: 0x34 */ 78 __IO uint32_t MDMAPWIRREL; /**< WIR Release, offset: 0x38 */ 79 uint8_t RESERVED_1[192]; 80 __I uint32_t ID; /**< Identity, offset: 0xFC */ 81 } MDM_AP_Type, *MDM_AP_MemMapPtr; 82 83 /** Number of instances of the MDM_AP module. */ 84 #define MDM_AP_INSTANCE_COUNT (1u) 85 86 /* MDM_AP - Peripheral instance base addresses */ 87 /** Peripheral MDM_AP base address */ 88 #define IP_MDM_AP_BASE (0x40250600u) 89 /** Peripheral MDM_AP base pointer */ 90 #define IP_MDM_AP ((MDM_AP_Type *)IP_MDM_AP_BASE) 91 /** Array initializer of MDM_AP peripheral base addresses */ 92 #define IP_MDM_AP_BASE_ADDRS { IP_MDM_AP_BASE } 93 /** Array initializer of MDM_AP peripheral base pointers */ 94 #define IP_MDM_AP_BASE_PTRS { IP_MDM_AP } 95 96 /* ---------------------------------------------------------------------------- 97 -- MDM_AP Register Masks 98 ---------------------------------------------------------------------------- */ 99 100 /*! 101 * @addtogroup MDM_AP_Register_Masks MDM_AP Register Masks 102 * @{ 103 */ 104 105 /*! @name MDMAPSTTS - Status */ 106 /*! @{ */ 107 108 #define MDM_AP_MDMAPSTTS_DESTRST_MASK (0x2U) 109 #define MDM_AP_MDMAPSTTS_DESTRST_SHIFT (1U) 110 #define MDM_AP_MDMAPSTTS_DESTRST_WIDTH (1U) 111 #define MDM_AP_MDMAPSTTS_DESTRST(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_MDMAPSTTS_DESTRST_SHIFT)) & MDM_AP_MDMAPSTTS_DESTRST_MASK) 112 113 #define MDM_AP_MDMAPSTTS_FUNCRST_MASK (0x4U) 114 #define MDM_AP_MDMAPSTTS_FUNCRST_SHIFT (2U) 115 #define MDM_AP_MDMAPSTTS_FUNCRST_WIDTH (1U) 116 #define MDM_AP_MDMAPSTTS_FUNCRST(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_MDMAPSTTS_FUNCRST_SHIFT)) & MDM_AP_MDMAPSTTS_FUNCRST_MASK) 117 118 #define MDM_AP_MDMAPSTTS_CM70HLT_MASK (0x1000U) 119 #define MDM_AP_MDMAPSTTS_CM70HLT_SHIFT (12U) 120 #define MDM_AP_MDMAPSTTS_CM70HLT_WIDTH (1U) 121 #define MDM_AP_MDMAPSTTS_CM70HLT(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_MDMAPSTTS_CM70HLT_SHIFT)) & MDM_AP_MDMAPSTTS_CM70HLT_MASK) 122 123 #define MDM_AP_MDMAPSTTS_CM70DPSLP_MASK (0x10000U) 124 #define MDM_AP_MDMAPSTTS_CM70DPSLP_SHIFT (16U) 125 #define MDM_AP_MDMAPSTTS_CM70DPSLP_WIDTH (1U) 126 #define MDM_AP_MDMAPSTTS_CM70DPSLP(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_MDMAPSTTS_CM70DPSLP_SHIFT)) & MDM_AP_MDMAPSTTS_CM70DPSLP_MASK) 127 128 #define MDM_AP_MDMAPSTTS_CM70SLPNG_MASK (0x100000U) 129 #define MDM_AP_MDMAPSTTS_CM70SLPNG_SHIFT (20U) 130 #define MDM_AP_MDMAPSTTS_CM70SLPNG_WIDTH (1U) 131 #define MDM_AP_MDMAPSTTS_CM70SLPNG(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_MDMAPSTTS_CM70SLPNG_SHIFT)) & MDM_AP_MDMAPSTTS_CM70SLPNG_MASK) 132 133 #define MDM_AP_MDMAPSTTS_CM70DBGRSTRD_MASK (0x10000000U) 134 #define MDM_AP_MDMAPSTTS_CM70DBGRSTRD_SHIFT (28U) 135 #define MDM_AP_MDMAPSTTS_CM70DBGRSTRD_WIDTH (1U) 136 #define MDM_AP_MDMAPSTTS_CM70DBGRSTRD(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_MDMAPSTTS_CM70DBGRSTRD_SHIFT)) & MDM_AP_MDMAPSTTS_CM70DBGRSTRD_MASK) 137 /*! @} */ 138 139 /*! @name MDMAPCTL - Control */ 140 /*! @{ */ 141 142 #define MDM_AP_MDMAPCTL_SYSRESETREQ_MASK (0x10U) 143 #define MDM_AP_MDMAPCTL_SYSRESETREQ_SHIFT (4U) 144 #define MDM_AP_MDMAPCTL_SYSRESETREQ_WIDTH (1U) 145 #define MDM_AP_MDMAPCTL_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_MDMAPCTL_SYSRESETREQ_SHIFT)) & MDM_AP_MDMAPCTL_SYSRESETREQ_MASK) 146 147 #define MDM_AP_MDMAPCTL_SYSFUNCRST_MASK (0x20U) 148 #define MDM_AP_MDMAPCTL_SYSFUNCRST_SHIFT (5U) 149 #define MDM_AP_MDMAPCTL_SYSFUNCRST_WIDTH (1U) 150 #define MDM_AP_MDMAPCTL_SYSFUNCRST(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_MDMAPCTL_SYSFUNCRST_SHIFT)) & MDM_AP_MDMAPCTL_SYSFUNCRST_MASK) 151 152 #define MDM_AP_MDMAPCTL_CM70DBGREQ_MASK (0x100U) 153 #define MDM_AP_MDMAPCTL_CM70DBGREQ_SHIFT (8U) 154 #define MDM_AP_MDMAPCTL_CM70DBGREQ_WIDTH (1U) 155 #define MDM_AP_MDMAPCTL_CM70DBGREQ(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_MDMAPCTL_CM70DBGREQ_SHIFT)) & MDM_AP_MDMAPCTL_CM70DBGREQ_MASK) 156 157 #define MDM_AP_MDMAPCTL_DBGRSTSLOWPAD_MASK (0x1000U) 158 #define MDM_AP_MDMAPCTL_DBGRSTSLOWPAD_SHIFT (12U) 159 #define MDM_AP_MDMAPCTL_DBGRSTSLOWPAD_WIDTH (1U) 160 #define MDM_AP_MDMAPCTL_DBGRSTSLOWPAD(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_MDMAPCTL_DBGRSTSLOWPAD_SHIFT)) & MDM_AP_MDMAPCTL_DBGRSTSLOWPAD_MASK) 161 162 #define MDM_AP_MDMAPCTL_DBGRSTFASTPAD_MASK (0x2000U) 163 #define MDM_AP_MDMAPCTL_DBGRSTFASTPAD_SHIFT (13U) 164 #define MDM_AP_MDMAPCTL_DBGRSTFASTPAD_WIDTH (1U) 165 #define MDM_AP_MDMAPCTL_DBGRSTFASTPAD(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_MDMAPCTL_DBGRSTFASTPAD_SHIFT)) & MDM_AP_MDMAPCTL_DBGRSTFASTPAD_MASK) 166 167 #define MDM_AP_MDMAPCTL_POR_WDG_DIS_MASK (0x8000U) 168 #define MDM_AP_MDMAPCTL_POR_WDG_DIS_SHIFT (15U) 169 #define MDM_AP_MDMAPCTL_POR_WDG_DIS_WIDTH (1U) 170 #define MDM_AP_MDMAPCTL_POR_WDG_DIS(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_MDMAPCTL_POR_WDG_DIS_SHIFT)) & MDM_AP_MDMAPCTL_POR_WDG_DIS_MASK) 171 172 #define MDM_AP_MDMAPCTL_TRIUOVRD_MASK (0x100000U) 173 #define MDM_AP_MDMAPCTL_TRIUOVRD_SHIFT (20U) 174 #define MDM_AP_MDMAPCTL_TRIUOVRD_WIDTH (1U) 175 #define MDM_AP_MDMAPCTL_TRIUOVRD(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_MDMAPCTL_TRIUOVRD_SHIFT)) & MDM_AP_MDMAPCTL_TRIUOVRD_MASK) 176 177 #define MDM_AP_MDMAPCTL_SWOOVRD_MASK (0x400000U) 178 #define MDM_AP_MDMAPCTL_SWOOVRD_SHIFT (22U) 179 #define MDM_AP_MDMAPCTL_SWOOVRD_WIDTH (1U) 180 #define MDM_AP_MDMAPCTL_SWOOVRD(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_MDMAPCTL_SWOOVRD_SHIFT)) & MDM_AP_MDMAPCTL_SWOOVRD_MASK) 181 182 #define MDM_AP_MDMAPCTL_CM70DBGRSRT_MASK (0x10000000U) 183 #define MDM_AP_MDMAPCTL_CM70DBGRSRT_SHIFT (28U) 184 #define MDM_AP_MDMAPCTL_CM70DBGRSRT_WIDTH (1U) 185 #define MDM_AP_MDMAPCTL_CM70DBGRSRT(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_MDMAPCTL_CM70DBGRSRT_SHIFT)) & MDM_AP_MDMAPCTL_CM70DBGRSRT_MASK) 186 /*! @} */ 187 188 /*! @name MDMAPWIREN - WIR Enable */ 189 /*! @{ */ 190 191 #define MDM_AP_MDMAPWIREN_LWPWREN_MASK (0x1U) 192 #define MDM_AP_MDMAPWIREN_LWPWREN_SHIFT (0U) 193 #define MDM_AP_MDMAPWIREN_LWPWREN_WIDTH (1U) 194 #define MDM_AP_MDMAPWIREN_LWPWREN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_MDMAPWIREN_LWPWREN_SHIFT)) & MDM_AP_MDMAPWIREN_LWPWREN_MASK) 195 196 #define MDM_AP_MDMAPWIREN_LWPRSTPRVT_MASK (0x2U) 197 #define MDM_AP_MDMAPWIREN_LWPRSTPRVT_SHIFT (1U) 198 #define MDM_AP_MDMAPWIREN_LWPRSTPRVT_WIDTH (1U) 199 #define MDM_AP_MDMAPWIREN_LWPRSTPRVT(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_MDMAPWIREN_LWPRSTPRVT_SHIFT)) & MDM_AP_MDMAPWIREN_LWPRSTPRVT_MASK) 200 /*! @} */ 201 202 /*! @name MDMAPWIRSTTS - WIR Status */ 203 /*! @{ */ 204 205 #define MDM_AP_MDMAPWIRSTTS_MDM_DAP_WIR_STATUS_MASK (0xFFFFFFFFU) 206 #define MDM_AP_MDMAPWIRSTTS_MDM_DAP_WIR_STATUS_SHIFT (0U) 207 #define MDM_AP_MDMAPWIRSTTS_MDM_DAP_WIR_STATUS_WIDTH (32U) 208 #define MDM_AP_MDMAPWIRSTTS_MDM_DAP_WIR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_MDMAPWIRSTTS_MDM_DAP_WIR_STATUS_SHIFT)) & MDM_AP_MDMAPWIRSTTS_MDM_DAP_WIR_STATUS_MASK) 209 /*! @} */ 210 211 /*! @name MDMAPWIRREL - WIR Release */ 212 /*! @{ */ 213 214 #define MDM_AP_MDMAPWIRREL_WTRSTRGM_MASK (0x1U) 215 #define MDM_AP_MDMAPWIRREL_WTRSTRGM_SHIFT (0U) 216 #define MDM_AP_MDMAPWIRREL_WTRSTRGM_WIDTH (1U) 217 #define MDM_AP_MDMAPWIRREL_WTRSTRGM(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_MDMAPWIRREL_WTRSTRGM_SHIFT)) & MDM_AP_MDMAPWIRREL_WTRSTRGM_MASK) 218 219 #define MDM_AP_MDMAPWIRREL_PRVNTRSTRGM_MASK (0x2U) 220 #define MDM_AP_MDMAPWIRREL_PRVNTRSTRGM_SHIFT (1U) 221 #define MDM_AP_MDMAPWIRREL_PRVNTRSTRGM_WIDTH (1U) 222 #define MDM_AP_MDMAPWIRREL_PRVNTRSTRGM(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_MDMAPWIRREL_PRVNTRSTRGM_SHIFT)) & MDM_AP_MDMAPWIRREL_PRVNTRSTRGM_MASK) 223 /*! @} */ 224 225 /*! @name ID - Identity */ 226 /*! @{ */ 227 228 #define MDM_AP_ID_ID_MASK (0xFFFFFFFFU) 229 #define MDM_AP_ID_ID_SHIFT (0U) 230 #define MDM_AP_ID_ID_WIDTH (32U) 231 #define MDM_AP_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_ID_ID_SHIFT)) & MDM_AP_ID_ID_MASK) 232 /*! @} */ 233 234 /*! 235 * @} 236 */ /* end of group MDM_AP_Register_Masks */ 237 238 /*! 239 * @} 240 */ /* end of group MDM_AP_Peripheral_Access_Layer */ 241 242 #endif /* #if !defined(S32K344_MDM_AP_H_) */ 243
