1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_LCU.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_LCU 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_LCU_H_) /* Check if memory map has not been already included */ 58 #define S32K344_LCU_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- LCU Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup LCU_Peripheral_Access_Layer LCU Peripheral Access Layer 68 * @{ 69 */ 70 71 /** LCU - Size of Registers Arrays */ 72 #define LCU_LC_LUTCTRL_COUNT 4u 73 #define LCU_LC_FILT_COUNT 4u 74 #define LCU_LC_COUNT 3u 75 #define LCU_SEL_COUNT 12u 76 77 /** LCU - Register Layout Typedef */ 78 typedef struct { 79 struct { /* offset: 0x0, array step: 0x40 */ 80 __IO uint32_t LUTCTRL[LCU_LC_LUTCTRL_COUNT]; /**< LC 0 Output 0 LUT Control..LC 2 Output 3 LUT Control, array offset: 0x0, array step: index*0x40, index2*0x4 */ 81 __IO uint32_t FILT[LCU_LC_FILT_COUNT]; /**< LC 0 Output 0 Filter..LC 2 Output 3 Filter, array offset: 0x10, array step: index*0x40, index2*0x4 */ 82 __IO uint32_t INTDMAEN; /**< LC 0 Interrupt and DMA Enable..LC 2 Interrupt and DMA Enable, array offset: 0x20, array step: 0x40 */ 83 __IO uint32_t STS; /**< LC 0 Status..LC 2 Status, array offset: 0x24, array step: 0x40 */ 84 __IO uint32_t OUTPOL; /**< LC 0 Output Polarity Control..LC 2 Output Polarity Control, array offset: 0x28, array step: 0x40 */ 85 __IO uint32_t FFILT; /**< LC 0 Force Filter..LC 2 Force Filter, array offset: 0x2C, array step: 0x40 */ 86 __IO uint32_t FCTRL; /**< LC 0 Force Control..LC 2 Force Control, array offset: 0x30, array step: 0x40 */ 87 __IO uint32_t SCTRL; /**< LC 0 Sync Control..LC 2 Sync Control, array offset: 0x34, array step: 0x40 */ 88 uint8_t RESERVED_0[8]; 89 } LC[LCU_LC_COUNT]; 90 uint8_t RESERVED_0[320]; 91 __IO uint32_t MUXSEL[LCU_SEL_COUNT]; /**< Mux Select, array offset: 0x200, array step: 0x4 */ 92 uint8_t RESERVED_1[80]; 93 __IO uint32_t CFG; /**< Configuration, offset: 0x280 */ 94 __IO uint32_t SWEN; /**< Software Override Enable, offset: 0x284 */ 95 __IO uint32_t SWVALUE; /**< Software Override Value, offset: 0x288 */ 96 __IO uint32_t OUTEN; /**< Output Enable, offset: 0x28C */ 97 __I uint32_t LCIN; /**< Logic Inputs, offset: 0x290 */ 98 __I uint32_t SWOUT; /**< Overridden Inputs, offset: 0x294 */ 99 __I uint32_t LCOUT; /**< Logic Outputs, offset: 0x298 */ 100 __I uint32_t FORCEOUT; /**< Forced Outputs, offset: 0x29C */ 101 __IO uint32_t FORCESTS; /**< Force Status, offset: 0x2A0 */ 102 uint8_t RESERVED_2[4]; 103 __IO uint32_t DBGEN; /**< Debug Mode Enable, offset: 0x2A8 */ 104 } LCU_Type, *LCU_MemMapPtr; 105 106 /** Number of instances of the LCU module. */ 107 #define LCU_INSTANCE_COUNT (2) 108 109 /* LCU - Peripheral instance base addresses */ 110 /** Peripheral LCU_0 base address */ 111 #define IP_LCU_0_BASE (0x40098000u) 112 /** Peripheral LCU_0 base pointer */ 113 #define IP_LCU_0 ((LCU_Type *)IP_LCU_0_BASE) 114 /** Peripheral LCU_1 base address */ 115 #define IP_LCU_1_BASE (0x4009C000u) 116 /** Peripheral LCU_1 base pointer */ 117 #define IP_LCU_1 ((LCU_Type *)IP_LCU_1_BASE) 118 /** Array initializer of LCU peripheral base addresses */ 119 #define IP_LCU_BASE_ADDRS { IP_LCU_0_BASE, IP_LCU_1_BASE } 120 /** Array initializer of LCU peripheral base pointers */ 121 #define IP_LCU_BASE_PTRS { IP_LCU_0, IP_LCU_1 } 122 123 /* ---------------------------------------------------------------------------- 124 -- LCU Register Masks 125 ---------------------------------------------------------------------------- */ 126 127 /*! 128 * @addtogroup LCU_Register_Masks LCU Register Masks 129 * @{ 130 */ 131 132 /*! @name LUTCTRL - LC 0 Output 0 LUT Control..LC 2 Output 3 LUT Control */ 133 /*! @{ */ 134 135 #define LCU_LUTCTRL_LUTCTRL_MASK (0xFFFFU) 136 #define LCU_LUTCTRL_LUTCTRL_SHIFT (0U) 137 #define LCU_LUTCTRL_LUTCTRL_WIDTH (16U) 138 #define LCU_LUTCTRL_LUTCTRL(x) (((uint32_t)(((uint32_t)(x)) << LCU_LUTCTRL_LUTCTRL_SHIFT)) & LCU_LUTCTRL_LUTCTRL_MASK) 139 /*! @} */ 140 141 /*! @name FILT - LC 0 Output 0 Filter..LC 2 Output 3 Filter */ 142 /*! @{ */ 143 144 #define LCU_FILT_LUT_FALL_FILT_MASK (0xFFFFU) 145 #define LCU_FILT_LUT_FALL_FILT_SHIFT (0U) 146 #define LCU_FILT_LUT_FALL_FILT_WIDTH (16U) 147 #define LCU_FILT_LUT_FALL_FILT(x) (((uint32_t)(((uint32_t)(x)) << LCU_FILT_LUT_FALL_FILT_SHIFT)) & LCU_FILT_LUT_FALL_FILT_MASK) 148 149 #define LCU_FILT_LUT_RISE_FILT_MASK (0xFFFF0000U) 150 #define LCU_FILT_LUT_RISE_FILT_SHIFT (16U) 151 #define LCU_FILT_LUT_RISE_FILT_WIDTH (16U) 152 #define LCU_FILT_LUT_RISE_FILT(x) (((uint32_t)(((uint32_t)(x)) << LCU_FILT_LUT_RISE_FILT_SHIFT)) & LCU_FILT_LUT_RISE_FILT_MASK) 153 /*! @} */ 154 155 /*! @name INTDMAEN - LC 0 Interrupt and DMA Enable..LC 2 Interrupt and DMA Enable */ 156 /*! @{ */ 157 158 #define LCU_INTDMAEN_LUT_INT_EN_MASK (0xFU) 159 #define LCU_INTDMAEN_LUT_INT_EN_SHIFT (0U) 160 #define LCU_INTDMAEN_LUT_INT_EN_WIDTH (4U) 161 #define LCU_INTDMAEN_LUT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << LCU_INTDMAEN_LUT_INT_EN_SHIFT)) & LCU_INTDMAEN_LUT_INT_EN_MASK) 162 163 #define LCU_INTDMAEN_LUT_DMA_EN_MASK (0xF00U) 164 #define LCU_INTDMAEN_LUT_DMA_EN_SHIFT (8U) 165 #define LCU_INTDMAEN_LUT_DMA_EN_WIDTH (4U) 166 #define LCU_INTDMAEN_LUT_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCU_INTDMAEN_LUT_DMA_EN_SHIFT)) & LCU_INTDMAEN_LUT_DMA_EN_MASK) 167 168 #define LCU_INTDMAEN_FORCE_INT_EN_MASK (0xF0000U) 169 #define LCU_INTDMAEN_FORCE_INT_EN_SHIFT (16U) 170 #define LCU_INTDMAEN_FORCE_INT_EN_WIDTH (4U) 171 #define LCU_INTDMAEN_FORCE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << LCU_INTDMAEN_FORCE_INT_EN_SHIFT)) & LCU_INTDMAEN_FORCE_INT_EN_MASK) 172 173 #define LCU_INTDMAEN_FORCE_DMA_EN_MASK (0xF000000U) 174 #define LCU_INTDMAEN_FORCE_DMA_EN_SHIFT (24U) 175 #define LCU_INTDMAEN_FORCE_DMA_EN_WIDTH (4U) 176 #define LCU_INTDMAEN_FORCE_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCU_INTDMAEN_FORCE_DMA_EN_SHIFT)) & LCU_INTDMAEN_FORCE_DMA_EN_MASK) 177 /*! @} */ 178 179 /*! @name STS - LC 0 Status..LC 2 Status */ 180 /*! @{ */ 181 182 #define LCU_STS_LUT_STS_MASK (0xFU) 183 #define LCU_STS_LUT_STS_SHIFT (0U) 184 #define LCU_STS_LUT_STS_WIDTH (4U) 185 #define LCU_STS_LUT_STS(x) (((uint32_t)(((uint32_t)(x)) << LCU_STS_LUT_STS_SHIFT)) & LCU_STS_LUT_STS_MASK) 186 187 #define LCU_STS_FORCESTS_MASK (0xF00U) 188 #define LCU_STS_FORCESTS_SHIFT (8U) 189 #define LCU_STS_FORCESTS_WIDTH (4U) 190 #define LCU_STS_FORCESTS(x) (((uint32_t)(((uint32_t)(x)) << LCU_STS_FORCESTS_SHIFT)) & LCU_STS_FORCESTS_MASK) 191 /*! @} */ 192 193 /*! @name OUTPOL - LC 0 Output Polarity Control..LC 2 Output Polarity Control */ 194 /*! @{ */ 195 196 #define LCU_OUTPOL_OUTPOL_MASK (0xFU) 197 #define LCU_OUTPOL_OUTPOL_SHIFT (0U) 198 #define LCU_OUTPOL_OUTPOL_WIDTH (4U) 199 #define LCU_OUTPOL_OUTPOL(x) (((uint32_t)(((uint32_t)(x)) << LCU_OUTPOL_OUTPOL_SHIFT)) & LCU_OUTPOL_OUTPOL_MASK) 200 /*! @} */ 201 202 /*! @name FFILT - LC 0 Force Filter..LC 2 Force Filter */ 203 /*! @{ */ 204 205 #define LCU_FFILT_FORCE_FILT_MASK (0xFFU) 206 #define LCU_FFILT_FORCE_FILT_SHIFT (0U) 207 #define LCU_FFILT_FORCE_FILT_WIDTH (8U) 208 #define LCU_FFILT_FORCE_FILT(x) (((uint32_t)(((uint32_t)(x)) << LCU_FFILT_FORCE_FILT_SHIFT)) & LCU_FFILT_FORCE_FILT_MASK) 209 210 #define LCU_FFILT_FORCE_POL_MASK (0x70000U) 211 #define LCU_FFILT_FORCE_POL_SHIFT (16U) 212 #define LCU_FFILT_FORCE_POL_WIDTH (3U) 213 #define LCU_FFILT_FORCE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCU_FFILT_FORCE_POL_SHIFT)) & LCU_FFILT_FORCE_POL_MASK) 214 215 #define LCU_FFILT_COMB_EN_MASK (0x7000000U) 216 #define LCU_FFILT_COMB_EN_SHIFT (24U) 217 #define LCU_FFILT_COMB_EN_WIDTH (3U) 218 #define LCU_FFILT_COMB_EN(x) (((uint32_t)(((uint32_t)(x)) << LCU_FFILT_COMB_EN_SHIFT)) & LCU_FFILT_COMB_EN_MASK) 219 220 #define LCU_FFILT_COMB_FORCE_MASK (0xF0000000U) 221 #define LCU_FFILT_COMB_FORCE_SHIFT (28U) 222 #define LCU_FFILT_COMB_FORCE_WIDTH (4U) 223 #define LCU_FFILT_COMB_FORCE(x) (((uint32_t)(((uint32_t)(x)) << LCU_FFILT_COMB_FORCE_SHIFT)) & LCU_FFILT_COMB_FORCE_MASK) 224 /*! @} */ 225 226 /*! @name FCTRL - LC 0 Force Control..LC 2 Force Control */ 227 /*! @{ */ 228 229 #define LCU_FCTRL_FORCE_SENSE0_MASK (0xFU) 230 #define LCU_FCTRL_FORCE_SENSE0_SHIFT (0U) 231 #define LCU_FCTRL_FORCE_SENSE0_WIDTH (4U) 232 #define LCU_FCTRL_FORCE_SENSE0(x) (((uint32_t)(((uint32_t)(x)) << LCU_FCTRL_FORCE_SENSE0_SHIFT)) & LCU_FCTRL_FORCE_SENSE0_MASK) 233 234 #define LCU_FCTRL_FORCE_MODE0_MASK (0x30U) 235 #define LCU_FCTRL_FORCE_MODE0_SHIFT (4U) 236 #define LCU_FCTRL_FORCE_MODE0_WIDTH (2U) 237 #define LCU_FCTRL_FORCE_MODE0(x) (((uint32_t)(((uint32_t)(x)) << LCU_FCTRL_FORCE_MODE0_SHIFT)) & LCU_FCTRL_FORCE_MODE0_MASK) 238 239 #define LCU_FCTRL_SYNC_SEL0_MASK (0xC0U) 240 #define LCU_FCTRL_SYNC_SEL0_SHIFT (6U) 241 #define LCU_FCTRL_SYNC_SEL0_WIDTH (2U) 242 #define LCU_FCTRL_SYNC_SEL0(x) (((uint32_t)(((uint32_t)(x)) << LCU_FCTRL_SYNC_SEL0_SHIFT)) & LCU_FCTRL_SYNC_SEL0_MASK) 243 244 #define LCU_FCTRL_FORCE_SENSE1_MASK (0xF00U) 245 #define LCU_FCTRL_FORCE_SENSE1_SHIFT (8U) 246 #define LCU_FCTRL_FORCE_SENSE1_WIDTH (4U) 247 #define LCU_FCTRL_FORCE_SENSE1(x) (((uint32_t)(((uint32_t)(x)) << LCU_FCTRL_FORCE_SENSE1_SHIFT)) & LCU_FCTRL_FORCE_SENSE1_MASK) 248 249 #define LCU_FCTRL_FORCE_MODE1_MASK (0x3000U) 250 #define LCU_FCTRL_FORCE_MODE1_SHIFT (12U) 251 #define LCU_FCTRL_FORCE_MODE1_WIDTH (2U) 252 #define LCU_FCTRL_FORCE_MODE1(x) (((uint32_t)(((uint32_t)(x)) << LCU_FCTRL_FORCE_MODE1_SHIFT)) & LCU_FCTRL_FORCE_MODE1_MASK) 253 254 #define LCU_FCTRL_SYNC_SEL1_MASK (0xC000U) 255 #define LCU_FCTRL_SYNC_SEL1_SHIFT (14U) 256 #define LCU_FCTRL_SYNC_SEL1_WIDTH (2U) 257 #define LCU_FCTRL_SYNC_SEL1(x) (((uint32_t)(((uint32_t)(x)) << LCU_FCTRL_SYNC_SEL1_SHIFT)) & LCU_FCTRL_SYNC_SEL1_MASK) 258 259 #define LCU_FCTRL_FORCE_SENSE2_MASK (0xF0000U) 260 #define LCU_FCTRL_FORCE_SENSE2_SHIFT (16U) 261 #define LCU_FCTRL_FORCE_SENSE2_WIDTH (4U) 262 #define LCU_FCTRL_FORCE_SENSE2(x) (((uint32_t)(((uint32_t)(x)) << LCU_FCTRL_FORCE_SENSE2_SHIFT)) & LCU_FCTRL_FORCE_SENSE2_MASK) 263 264 #define LCU_FCTRL_FORCE_MODE2_MASK (0x300000U) 265 #define LCU_FCTRL_FORCE_MODE2_SHIFT (20U) 266 #define LCU_FCTRL_FORCE_MODE2_WIDTH (2U) 267 #define LCU_FCTRL_FORCE_MODE2(x) (((uint32_t)(((uint32_t)(x)) << LCU_FCTRL_FORCE_MODE2_SHIFT)) & LCU_FCTRL_FORCE_MODE2_MASK) 268 269 #define LCU_FCTRL_SYNC_SEL2_MASK (0xC00000U) 270 #define LCU_FCTRL_SYNC_SEL2_SHIFT (22U) 271 #define LCU_FCTRL_SYNC_SEL2_WIDTH (2U) 272 #define LCU_FCTRL_SYNC_SEL2(x) (((uint32_t)(((uint32_t)(x)) << LCU_FCTRL_SYNC_SEL2_SHIFT)) & LCU_FCTRL_SYNC_SEL2_MASK) 273 274 #define LCU_FCTRL_FORCE_SENSE3_MASK (0xF000000U) 275 #define LCU_FCTRL_FORCE_SENSE3_SHIFT (24U) 276 #define LCU_FCTRL_FORCE_SENSE3_WIDTH (4U) 277 #define LCU_FCTRL_FORCE_SENSE3(x) (((uint32_t)(((uint32_t)(x)) << LCU_FCTRL_FORCE_SENSE3_SHIFT)) & LCU_FCTRL_FORCE_SENSE3_MASK) 278 279 #define LCU_FCTRL_FORCE_MODE3_MASK (0x30000000U) 280 #define LCU_FCTRL_FORCE_MODE3_SHIFT (28U) 281 #define LCU_FCTRL_FORCE_MODE3_WIDTH (2U) 282 #define LCU_FCTRL_FORCE_MODE3(x) (((uint32_t)(((uint32_t)(x)) << LCU_FCTRL_FORCE_MODE3_SHIFT)) & LCU_FCTRL_FORCE_MODE3_MASK) 283 284 #define LCU_FCTRL_SYNC_SEL3_MASK (0xC0000000U) 285 #define LCU_FCTRL_SYNC_SEL3_SHIFT (30U) 286 #define LCU_FCTRL_SYNC_SEL3_WIDTH (2U) 287 #define LCU_FCTRL_SYNC_SEL3(x) (((uint32_t)(((uint32_t)(x)) << LCU_FCTRL_SYNC_SEL3_SHIFT)) & LCU_FCTRL_SYNC_SEL3_MASK) 288 /*! @} */ 289 290 /*! @name SCTRL - LC 0 Sync Control..LC 2 Sync Control */ 291 /*! @{ */ 292 293 #define LCU_SCTRL_SW_MODE_MASK (0xFU) 294 #define LCU_SCTRL_SW_MODE_SHIFT (0U) 295 #define LCU_SCTRL_SW_MODE_WIDTH (4U) 296 #define LCU_SCTRL_SW_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCU_SCTRL_SW_MODE_SHIFT)) & LCU_SCTRL_SW_MODE_MASK) 297 298 #define LCU_SCTRL_SW_SYNC_SEL_MASK (0x300U) 299 #define LCU_SCTRL_SW_SYNC_SEL_SHIFT (8U) 300 #define LCU_SCTRL_SW_SYNC_SEL_WIDTH (2U) 301 #define LCU_SCTRL_SW_SYNC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCU_SCTRL_SW_SYNC_SEL_SHIFT)) & LCU_SCTRL_SW_SYNC_SEL_MASK) 302 /*! @} */ 303 304 /*! @name MUXSEL - Mux Select */ 305 /*! @{ */ 306 307 #define LCU_MUXSEL_MUXSEL_MASK (0xFFU) 308 #define LCU_MUXSEL_MUXSEL_SHIFT (0U) 309 #define LCU_MUXSEL_MUXSEL_WIDTH (8U) 310 #define LCU_MUXSEL_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << LCU_MUXSEL_MUXSEL_SHIFT)) & LCU_MUXSEL_MUXSEL_MASK) 311 /*! @} */ 312 313 /*! @name CFG - Configuration */ 314 /*! @{ */ 315 316 #define LCU_CFG_WP_MASK (0x1U) 317 #define LCU_CFG_WP_SHIFT (0U) 318 #define LCU_CFG_WP_WIDTH (1U) 319 #define LCU_CFG_WP(x) (((uint32_t)(((uint32_t)(x)) << LCU_CFG_WP_SHIFT)) & LCU_CFG_WP_MASK) 320 321 #define LCU_CFG_INCL_MUXES_MASK (0x80U) 322 #define LCU_CFG_INCL_MUXES_SHIFT (7U) 323 #define LCU_CFG_INCL_MUXES_WIDTH (1U) 324 #define LCU_CFG_INCL_MUXES(x) (((uint32_t)(((uint32_t)(x)) << LCU_CFG_INCL_MUXES_SHIFT)) & LCU_CFG_INCL_MUXES_MASK) 325 326 #define LCU_CFG_NUM_SYNCS_MASK (0xFF00U) 327 #define LCU_CFG_NUM_SYNCS_SHIFT (8U) 328 #define LCU_CFG_NUM_SYNCS_WIDTH (8U) 329 #define LCU_CFG_NUM_SYNCS(x) (((uint32_t)(((uint32_t)(x)) << LCU_CFG_NUM_SYNCS_SHIFT)) & LCU_CFG_NUM_SYNCS_MASK) 330 331 #define LCU_CFG_NUM_FORCES_MASK (0xFF0000U) 332 #define LCU_CFG_NUM_FORCES_SHIFT (16U) 333 #define LCU_CFG_NUM_FORCES_WIDTH (8U) 334 #define LCU_CFG_NUM_FORCES(x) (((uint32_t)(((uint32_t)(x)) << LCU_CFG_NUM_FORCES_SHIFT)) & LCU_CFG_NUM_FORCES_MASK) 335 336 #define LCU_CFG_NUM_LOGIC_CELLS_MASK (0xFF000000U) 337 #define LCU_CFG_NUM_LOGIC_CELLS_SHIFT (24U) 338 #define LCU_CFG_NUM_LOGIC_CELLS_WIDTH (8U) 339 #define LCU_CFG_NUM_LOGIC_CELLS(x) (((uint32_t)(((uint32_t)(x)) << LCU_CFG_NUM_LOGIC_CELLS_SHIFT)) & LCU_CFG_NUM_LOGIC_CELLS_MASK) 340 /*! @} */ 341 342 /*! @name SWEN - Software Override Enable */ 343 /*! @{ */ 344 345 #define LCU_SWEN_SWEN_MASK (0xFFFU) 346 #define LCU_SWEN_SWEN_SHIFT (0U) 347 #define LCU_SWEN_SWEN_WIDTH (12U) 348 #define LCU_SWEN_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LCU_SWEN_SWEN_SHIFT)) & LCU_SWEN_SWEN_MASK) 349 /*! @} */ 350 351 /*! @name SWVALUE - Software Override Value */ 352 /*! @{ */ 353 354 #define LCU_SWVALUE_SWVALUE_MASK (0xFFFU) 355 #define LCU_SWVALUE_SWVALUE_SHIFT (0U) 356 #define LCU_SWVALUE_SWVALUE_WIDTH (12U) 357 #define LCU_SWVALUE_SWVALUE(x) (((uint32_t)(((uint32_t)(x)) << LCU_SWVALUE_SWVALUE_SHIFT)) & LCU_SWVALUE_SWVALUE_MASK) 358 /*! @} */ 359 360 /*! @name OUTEN - Output Enable */ 361 /*! @{ */ 362 363 #define LCU_OUTEN_OUTEN_MASK (0xFFFU) 364 #define LCU_OUTEN_OUTEN_SHIFT (0U) 365 #define LCU_OUTEN_OUTEN_WIDTH (12U) 366 #define LCU_OUTEN_OUTEN(x) (((uint32_t)(((uint32_t)(x)) << LCU_OUTEN_OUTEN_SHIFT)) & LCU_OUTEN_OUTEN_MASK) 367 /*! @} */ 368 369 /*! @name LCIN - Logic Inputs */ 370 /*! @{ */ 371 372 #define LCU_LCIN_LC_INPUTS_MASK (0xFFFU) 373 #define LCU_LCIN_LC_INPUTS_SHIFT (0U) 374 #define LCU_LCIN_LC_INPUTS_WIDTH (12U) 375 #define LCU_LCIN_LC_INPUTS(x) (((uint32_t)(((uint32_t)(x)) << LCU_LCIN_LC_INPUTS_SHIFT)) & LCU_LCIN_LC_INPUTS_MASK) 376 /*! @} */ 377 378 /*! @name SWOUT - Overridden Inputs */ 379 /*! @{ */ 380 381 #define LCU_SWOUT_SWOUT_MASK (0xFFFU) 382 #define LCU_SWOUT_SWOUT_SHIFT (0U) 383 #define LCU_SWOUT_SWOUT_WIDTH (12U) 384 #define LCU_SWOUT_SWOUT(x) (((uint32_t)(((uint32_t)(x)) << LCU_SWOUT_SWOUT_SHIFT)) & LCU_SWOUT_SWOUT_MASK) 385 /*! @} */ 386 387 /*! @name LCOUT - Logic Outputs */ 388 /*! @{ */ 389 390 #define LCU_LCOUT_LCOUT_MASK (0xFFFU) 391 #define LCU_LCOUT_LCOUT_SHIFT (0U) 392 #define LCU_LCOUT_LCOUT_WIDTH (12U) 393 #define LCU_LCOUT_LCOUT(x) (((uint32_t)(((uint32_t)(x)) << LCU_LCOUT_LCOUT_SHIFT)) & LCU_LCOUT_LCOUT_MASK) 394 /*! @} */ 395 396 /*! @name FORCEOUT - Forced Outputs */ 397 /*! @{ */ 398 399 #define LCU_FORCEOUT_FORCEOUT_MASK (0xFFFU) 400 #define LCU_FORCEOUT_FORCEOUT_SHIFT (0U) 401 #define LCU_FORCEOUT_FORCEOUT_WIDTH (12U) 402 #define LCU_FORCEOUT_FORCEOUT(x) (((uint32_t)(((uint32_t)(x)) << LCU_FORCEOUT_FORCEOUT_SHIFT)) & LCU_FORCEOUT_FORCEOUT_MASK) 403 /*! @} */ 404 405 /*! @name FORCESTS - Force Status */ 406 /*! @{ */ 407 408 #define LCU_FORCESTS_FORCESTS_MASK (0xFFFU) 409 #define LCU_FORCESTS_FORCESTS_SHIFT (0U) 410 #define LCU_FORCESTS_FORCESTS_WIDTH (12U) 411 #define LCU_FORCESTS_FORCESTS(x) (((uint32_t)(((uint32_t)(x)) << LCU_FORCESTS_FORCESTS_SHIFT)) & LCU_FORCESTS_FORCESTS_MASK) 412 /*! @} */ 413 414 /*! @name DBGEN - Debug Mode Enable */ 415 /*! @{ */ 416 417 #define LCU_DBGEN_DBGEN_MASK (0xFFFU) 418 #define LCU_DBGEN_DBGEN_SHIFT (0U) 419 #define LCU_DBGEN_DBGEN_WIDTH (12U) 420 #define LCU_DBGEN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LCU_DBGEN_DBGEN_SHIFT)) & LCU_DBGEN_DBGEN_MASK) 421 /*! @} */ 422 423 /*! 424 * @} 425 */ /* end of group LCU_Register_Masks */ 426 427 /*! 428 * @} 429 */ /* end of group LCU_Peripheral_Access_Layer */ 430 431 #endif /* #if !defined(S32K344_LCU_H_) */ 432
