1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_JDC.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_JDC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_JDC_H_) /* Check if memory map has not been already included */ 58 #define S32K344_JDC_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- JDC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup JDC_Peripheral_Access_Layer JDC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** JDC - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ 74 __IO uint32_t MSR; /**< Module Status Register, offset: 0x4 */ 75 __IO uint32_t JOUT_IPS; /**< JTAG Output Data Register, offset: 0x8 */ 76 __I uint32_t JIN_IPS; /**< JTAG Input Data Register, offset: 0xC */ 77 } JDC_Type, *JDC_MemMapPtr; 78 79 /** Number of instances of the JDC module. */ 80 #define JDC_INSTANCE_COUNT (1u) 81 82 /* JDC - Peripheral instance base addresses */ 83 /** Peripheral JDC base address */ 84 #define IP_JDC_BASE (0x40394000u) 85 /** Peripheral JDC base pointer */ 86 #define IP_JDC ((JDC_Type *)IP_JDC_BASE) 87 /** Array initializer of JDC peripheral base addresses */ 88 #define IP_JDC_BASE_ADDRS { IP_JDC_BASE } 89 /** Array initializer of JDC peripheral base pointers */ 90 #define IP_JDC_BASE_PTRS { IP_JDC } 91 92 /* ---------------------------------------------------------------------------- 93 -- JDC Register Masks 94 ---------------------------------------------------------------------------- */ 95 96 /*! 97 * @addtogroup JDC_Register_Masks JDC Register Masks 98 * @{ 99 */ 100 101 /*! @name MCR - Module Configuration Register */ 102 /*! @{ */ 103 104 #define JDC_MCR_JOUT_IEN_MASK (0x1U) 105 #define JDC_MCR_JOUT_IEN_SHIFT (0U) 106 #define JDC_MCR_JOUT_IEN_WIDTH (1U) 107 #define JDC_MCR_JOUT_IEN(x) (((uint32_t)(((uint32_t)(x)) << JDC_MCR_JOUT_IEN_SHIFT)) & JDC_MCR_JOUT_IEN_MASK) 108 109 #define JDC_MCR_JIN_IEN_MASK (0x10000U) 110 #define JDC_MCR_JIN_IEN_SHIFT (16U) 111 #define JDC_MCR_JIN_IEN_WIDTH (1U) 112 #define JDC_MCR_JIN_IEN(x) (((uint32_t)(((uint32_t)(x)) << JDC_MCR_JIN_IEN_SHIFT)) & JDC_MCR_JIN_IEN_MASK) 113 /*! @} */ 114 115 /*! @name MSR - Module Status Register */ 116 /*! @{ */ 117 118 #define JDC_MSR_JOUT_INT_MASK (0x1U) 119 #define JDC_MSR_JOUT_INT_SHIFT (0U) 120 #define JDC_MSR_JOUT_INT_WIDTH (1U) 121 #define JDC_MSR_JOUT_INT(x) (((uint32_t)(((uint32_t)(x)) << JDC_MSR_JOUT_INT_SHIFT)) & JDC_MSR_JOUT_INT_MASK) 122 123 #define JDC_MSR_JOUT_RDY_MASK (0x4U) 124 #define JDC_MSR_JOUT_RDY_SHIFT (2U) 125 #define JDC_MSR_JOUT_RDY_WIDTH (1U) 126 #define JDC_MSR_JOUT_RDY(x) (((uint32_t)(((uint32_t)(x)) << JDC_MSR_JOUT_RDY_SHIFT)) & JDC_MSR_JOUT_RDY_MASK) 127 128 #define JDC_MSR_JIN_INT_MASK (0x10000U) 129 #define JDC_MSR_JIN_INT_SHIFT (16U) 130 #define JDC_MSR_JIN_INT_WIDTH (1U) 131 #define JDC_MSR_JIN_INT(x) (((uint32_t)(((uint32_t)(x)) << JDC_MSR_JIN_INT_SHIFT)) & JDC_MSR_JIN_INT_MASK) 132 133 #define JDC_MSR_JIN_RDY_MASK (0x40000U) 134 #define JDC_MSR_JIN_RDY_SHIFT (18U) 135 #define JDC_MSR_JIN_RDY_WIDTH (1U) 136 #define JDC_MSR_JIN_RDY(x) (((uint32_t)(((uint32_t)(x)) << JDC_MSR_JIN_RDY_SHIFT)) & JDC_MSR_JIN_RDY_MASK) 137 /*! @} */ 138 139 /*! @name JOUT_IPS - JTAG Output Data Register */ 140 /*! @{ */ 141 142 #define JDC_JOUT_IPS_Data_MASK (0xFFFFFFFFU) 143 #define JDC_JOUT_IPS_Data_SHIFT (0U) 144 #define JDC_JOUT_IPS_Data_WIDTH (32U) 145 #define JDC_JOUT_IPS_Data(x) (((uint32_t)(((uint32_t)(x)) << JDC_JOUT_IPS_Data_SHIFT)) & JDC_JOUT_IPS_Data_MASK) 146 /*! @} */ 147 148 /*! @name JIN_IPS - JTAG Input Data Register */ 149 /*! @{ */ 150 151 #define JDC_JIN_IPS_Data_MASK (0xFFFFFFFFU) 152 #define JDC_JIN_IPS_Data_SHIFT (0U) 153 #define JDC_JIN_IPS_Data_WIDTH (32U) 154 #define JDC_JIN_IPS_Data(x) (((uint32_t)(((uint32_t)(x)) << JDC_JIN_IPS_Data_SHIFT)) & JDC_JIN_IPS_Data_MASK) 155 /*! @} */ 156 157 /*! 158 * @} 159 */ /* end of group JDC_Register_Masks */ 160 161 /*! 162 * @} 163 */ /* end of group JDC_Peripheral_Access_Layer */ 164 165 #endif /* #if !defined(S32K344_JDC_H_) */ 166
