1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_FLEXIO.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_FLEXIO 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_FLEXIO_H_) /* Check if memory map has not been already included */ 58 #define S32K344_FLEXIO_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- FLEXIO Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer 68 * @{ 69 */ 70 71 /** FLEXIO - Size of Registers Arrays */ 72 #define FLEXIO_SHIFTCTL_COUNT 8u 73 #define FLEXIO_SHIFTCFG_COUNT 8u 74 #define FLEXIO_SHIFTBUF_COUNT 8u 75 #define FLEXIO_SHIFTBUFBIS_COUNT 8u 76 #define FLEXIO_SHIFTBUFBYS_COUNT 8u 77 #define FLEXIO_SHIFTBUFBBS_COUNT 8u 78 #define FLEXIO_TIMCTL_COUNT 8u 79 #define FLEXIO_TIMCFG_COUNT 8u 80 #define FLEXIO_TIMCMP_COUNT 8u 81 #define FLEXIO_SHIFTBUFNBS_COUNT 8u 82 #define FLEXIO_SHIFTBUFHWS_COUNT 8u 83 #define FLEXIO_SHIFTBUFNIS_COUNT 8u 84 #define FLEXIO_SHIFTBUFOES_COUNT 8u 85 #define FLEXIO_SHIFTBUFEOS_COUNT 8u 86 #define FLEXIO_SHIFTBUFHBS_COUNT 8u 87 88 /** FLEXIO - Register Layout Typedef */ 89 typedef struct { 90 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ 91 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ 92 __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */ 93 __I uint32_t PIN; /**< Pin State Register, offset: 0xC */ 94 __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */ 95 __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */ 96 __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */ 97 uint8_t RESERVED_0[4]; 98 __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ 99 __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ 100 __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */ 101 uint8_t RESERVED_1[4]; 102 __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ 103 uint8_t RESERVED_2[4]; 104 __IO uint32_t TIMERSDEN; /**< Timer Status DMA Enable, offset: 0x38 */ 105 uint8_t RESERVED_3[4]; 106 __IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */ 107 uint8_t RESERVED_4[4]; 108 __IO uint32_t TRGSTAT; /**< Trigger Status Register, offset: 0x48 */ 109 __IO uint32_t TRIGIEN; /**< External Trigger Interrupt Enable Register, offset: 0x4C */ 110 __IO uint32_t PINSTAT; /**< Pin Status Register, offset: 0x50 */ 111 __IO uint32_t PINIEN; /**< Pin Interrupt Enable Register, offset: 0x54 */ 112 __IO uint32_t PINREN; /**< Pin Rising Edge Enable Register, offset: 0x58 */ 113 __IO uint32_t PINFEN; /**< Pin Falling Edge Enable Register, offset: 0x5C */ 114 __IO uint32_t PINOUTD; /**< Pin Output Data Register, offset: 0x60 */ 115 __IO uint32_t PINOUTE; /**< Pin Output Enable Register, offset: 0x64 */ 116 __O uint32_t PINOUTDIS; /**< Pin Output Disable Register, offset: 0x68 */ 117 __O uint32_t PINOUTCLR; /**< Pin Output Clear Register, offset: 0x6C */ 118 __O uint32_t PINOUTSET; /**< Pin Output Set Register, offset: 0x70 */ 119 __O uint32_t PINOUTTOG; /**< Pin Output Toggle Register, offset: 0x74 */ 120 uint8_t RESERVED_5[8]; 121 __IO uint32_t SHIFTCTL[FLEXIO_SHIFTCTL_COUNT]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */ 122 uint8_t RESERVED_6[96]; 123 __IO uint32_t SHIFTCFG[FLEXIO_SHIFTCFG_COUNT]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */ 124 uint8_t RESERVED_7[224]; 125 __IO uint32_t SHIFTBUF[FLEXIO_SHIFTBUF_COUNT]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */ 126 uint8_t RESERVED_8[96]; 127 __IO uint32_t SHIFTBUFBIS[FLEXIO_SHIFTBUFBIS_COUNT]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */ 128 uint8_t RESERVED_9[96]; 129 __IO uint32_t SHIFTBUFBYS[FLEXIO_SHIFTBUFBYS_COUNT]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */ 130 uint8_t RESERVED_10[96]; 131 __IO uint32_t SHIFTBUFBBS[FLEXIO_SHIFTBUFBBS_COUNT]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */ 132 uint8_t RESERVED_11[96]; 133 __IO uint32_t TIMCTL[FLEXIO_TIMCTL_COUNT]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */ 134 uint8_t RESERVED_12[96]; 135 __IO uint32_t TIMCFG[FLEXIO_TIMCFG_COUNT]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */ 136 uint8_t RESERVED_13[96]; 137 __IO uint32_t TIMCMP[FLEXIO_TIMCMP_COUNT]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */ 138 uint8_t RESERVED_14[352]; 139 __IO uint32_t SHIFTBUFNBS[FLEXIO_SHIFTBUFNBS_COUNT]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */ 140 uint8_t RESERVED_15[96]; 141 __IO uint32_t SHIFTBUFHWS[FLEXIO_SHIFTBUFHWS_COUNT]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */ 142 uint8_t RESERVED_16[96]; 143 __IO uint32_t SHIFTBUFNIS[FLEXIO_SHIFTBUFNIS_COUNT]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */ 144 uint8_t RESERVED_17[96]; 145 __IO uint32_t SHIFTBUFOES[FLEXIO_SHIFTBUFOES_COUNT]; /**< Shifter Buffer N Odd Even Swapped Register, array offset: 0x800, array step: 0x4 */ 146 uint8_t RESERVED_18[96]; 147 __IO uint32_t SHIFTBUFEOS[FLEXIO_SHIFTBUFEOS_COUNT]; /**< Shifter Buffer N Even Odd Swapped Register, array offset: 0x880, array step: 0x4 */ 148 uint8_t RESERVED_19[96]; 149 __IO uint32_t SHIFTBUFHBS[FLEXIO_SHIFTBUFHBS_COUNT]; /**< Shifter Buffer N Halfword Byte Swapped Register, array offset: 0x900, array step: 0x4 */ 150 } FLEXIO_Type, *FLEXIO_MemMapPtr; 151 152 /** Number of instances of the FLEXIO module. */ 153 #define FLEXIO_INSTANCE_COUNT (1u) 154 155 /* FLEXIO - Peripheral instance base addresses */ 156 /** Peripheral FLEXIO base address */ 157 #define IP_FLEXIO_BASE (0x40324000u) 158 /** Peripheral FLEXIO base pointer */ 159 #define IP_FLEXIO ((FLEXIO_Type *)IP_FLEXIO_BASE) 160 /** Array initializer of FLEXIO peripheral base addresses */ 161 #define IP_FLEXIO_BASE_ADDRS { IP_FLEXIO_BASE } 162 /** Array initializer of FLEXIO peripheral base pointers */ 163 #define IP_FLEXIO_BASE_PTRS { IP_FLEXIO } 164 165 /* ---------------------------------------------------------------------------- 166 -- FLEXIO Register Masks 167 ---------------------------------------------------------------------------- */ 168 169 /*! 170 * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks 171 * @{ 172 */ 173 174 /*! @name VERID - Version ID Register */ 175 /*! @{ */ 176 177 #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) 178 #define FLEXIO_VERID_FEATURE_SHIFT (0U) 179 #define FLEXIO_VERID_FEATURE_WIDTH (16U) 180 #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) 181 182 #define FLEXIO_VERID_MINOR_MASK (0xFF0000U) 183 #define FLEXIO_VERID_MINOR_SHIFT (16U) 184 #define FLEXIO_VERID_MINOR_WIDTH (8U) 185 #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) 186 187 #define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) 188 #define FLEXIO_VERID_MAJOR_SHIFT (24U) 189 #define FLEXIO_VERID_MAJOR_WIDTH (8U) 190 #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) 191 /*! @} */ 192 193 /*! @name PARAM - Parameter Register */ 194 /*! @{ */ 195 196 #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) 197 #define FLEXIO_PARAM_SHIFTER_SHIFT (0U) 198 #define FLEXIO_PARAM_SHIFTER_WIDTH (8U) 199 #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) 200 201 #define FLEXIO_PARAM_TIMER_MASK (0xFF00U) 202 #define FLEXIO_PARAM_TIMER_SHIFT (8U) 203 #define FLEXIO_PARAM_TIMER_WIDTH (8U) 204 #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) 205 206 #define FLEXIO_PARAM_PIN_MASK (0xFF0000U) 207 #define FLEXIO_PARAM_PIN_SHIFT (16U) 208 #define FLEXIO_PARAM_PIN_WIDTH (8U) 209 #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) 210 211 #define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) 212 #define FLEXIO_PARAM_TRIGGER_SHIFT (24U) 213 #define FLEXIO_PARAM_TRIGGER_WIDTH (8U) 214 #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) 215 /*! @} */ 216 217 /*! @name CTRL - FlexIO Control Register */ 218 /*! @{ */ 219 220 #define FLEXIO_CTRL_FLEXEN_MASK (0x1U) 221 #define FLEXIO_CTRL_FLEXEN_SHIFT (0U) 222 #define FLEXIO_CTRL_FLEXEN_WIDTH (1U) 223 #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) 224 225 #define FLEXIO_CTRL_SWRST_MASK (0x2U) 226 #define FLEXIO_CTRL_SWRST_SHIFT (1U) 227 #define FLEXIO_CTRL_SWRST_WIDTH (1U) 228 #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) 229 230 #define FLEXIO_CTRL_FASTACC_MASK (0x4U) 231 #define FLEXIO_CTRL_FASTACC_SHIFT (2U) 232 #define FLEXIO_CTRL_FASTACC_WIDTH (1U) 233 #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) 234 235 #define FLEXIO_CTRL_DBGE_MASK (0x40000000U) 236 #define FLEXIO_CTRL_DBGE_SHIFT (30U) 237 #define FLEXIO_CTRL_DBGE_WIDTH (1U) 238 #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) 239 /*! @} */ 240 241 /*! @name PIN - Pin State Register */ 242 /*! @{ */ 243 244 #define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) 245 #define FLEXIO_PIN_PDI_SHIFT (0U) 246 #define FLEXIO_PIN_PDI_WIDTH (32U) 247 #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) 248 /*! @} */ 249 250 /*! @name SHIFTSTAT - Shifter Status Register */ 251 /*! @{ */ 252 253 #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU) 254 #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) 255 #define FLEXIO_SHIFTSTAT_SSF_WIDTH (8U) 256 #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) 257 /*! @} */ 258 259 /*! @name SHIFTERR - Shifter Error Register */ 260 /*! @{ */ 261 262 #define FLEXIO_SHIFTERR_SEF_MASK (0xFFU) 263 #define FLEXIO_SHIFTERR_SEF_SHIFT (0U) 264 #define FLEXIO_SHIFTERR_SEF_WIDTH (8U) 265 #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) 266 /*! @} */ 267 268 /*! @name TIMSTAT - Timer Status Register */ 269 /*! @{ */ 270 271 #define FLEXIO_TIMSTAT_TSF_MASK (0xFFU) 272 #define FLEXIO_TIMSTAT_TSF_SHIFT (0U) 273 #define FLEXIO_TIMSTAT_TSF_WIDTH (8U) 274 #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) 275 /*! @} */ 276 277 /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ 278 /*! @{ */ 279 280 #define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU) 281 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) 282 #define FLEXIO_SHIFTSIEN_SSIE_WIDTH (8U) 283 #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) 284 /*! @} */ 285 286 /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ 287 /*! @{ */ 288 289 #define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU) 290 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) 291 #define FLEXIO_SHIFTEIEN_SEIE_WIDTH (8U) 292 #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) 293 /*! @} */ 294 295 /*! @name TIMIEN - Timer Interrupt Enable Register */ 296 /*! @{ */ 297 298 #define FLEXIO_TIMIEN_TEIE_MASK (0xFFU) 299 #define FLEXIO_TIMIEN_TEIE_SHIFT (0U) 300 #define FLEXIO_TIMIEN_TEIE_WIDTH (8U) 301 #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) 302 /*! @} */ 303 304 /*! @name SHIFTSDEN - Shifter Status DMA Enable */ 305 /*! @{ */ 306 307 #define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU) 308 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) 309 #define FLEXIO_SHIFTSDEN_SSDE_WIDTH (8U) 310 #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) 311 /*! @} */ 312 313 /*! @name TIMERSDEN - Timer Status DMA Enable */ 314 /*! @{ */ 315 316 #define FLEXIO_TIMERSDEN_TSDE_MASK (0xFFU) 317 #define FLEXIO_TIMERSDEN_TSDE_SHIFT (0U) 318 #define FLEXIO_TIMERSDEN_TSDE_WIDTH (8U) 319 #define FLEXIO_TIMERSDEN_TSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK) 320 /*! @} */ 321 322 /*! @name SHIFTSTATE - Shifter State Register */ 323 /*! @{ */ 324 325 #define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) 326 #define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) 327 #define FLEXIO_SHIFTSTATE_STATE_WIDTH (3U) 328 #define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) 329 /*! @} */ 330 331 /*! @name TRGSTAT - Trigger Status Register */ 332 /*! @{ */ 333 334 #define FLEXIO_TRGSTAT_ETSF_MASK (0xFU) 335 #define FLEXIO_TRGSTAT_ETSF_SHIFT (0U) 336 #define FLEXIO_TRGSTAT_ETSF_WIDTH (4U) 337 #define FLEXIO_TRGSTAT_ETSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRGSTAT_ETSF_SHIFT)) & FLEXIO_TRGSTAT_ETSF_MASK) 338 /*! @} */ 339 340 /*! @name TRIGIEN - External Trigger Interrupt Enable Register */ 341 /*! @{ */ 342 343 #define FLEXIO_TRIGIEN_TRIE_MASK (0xFU) 344 #define FLEXIO_TRIGIEN_TRIE_SHIFT (0U) 345 #define FLEXIO_TRIGIEN_TRIE_WIDTH (4U) 346 #define FLEXIO_TRIGIEN_TRIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRIGIEN_TRIE_SHIFT)) & FLEXIO_TRIGIEN_TRIE_MASK) 347 /*! @} */ 348 349 /*! @name PINSTAT - Pin Status Register */ 350 /*! @{ */ 351 352 #define FLEXIO_PINSTAT_PSF_MASK (0xFFFFFFFFU) 353 #define FLEXIO_PINSTAT_PSF_SHIFT (0U) 354 #define FLEXIO_PINSTAT_PSF_WIDTH (32U) 355 #define FLEXIO_PINSTAT_PSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINSTAT_PSF_SHIFT)) & FLEXIO_PINSTAT_PSF_MASK) 356 /*! @} */ 357 358 /*! @name PINIEN - Pin Interrupt Enable Register */ 359 /*! @{ */ 360 361 #define FLEXIO_PINIEN_PSIE_MASK (0xFFFFFFFFU) 362 #define FLEXIO_PINIEN_PSIE_SHIFT (0U) 363 #define FLEXIO_PINIEN_PSIE_WIDTH (32U) 364 #define FLEXIO_PINIEN_PSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINIEN_PSIE_SHIFT)) & FLEXIO_PINIEN_PSIE_MASK) 365 /*! @} */ 366 367 /*! @name PINREN - Pin Rising Edge Enable Register */ 368 /*! @{ */ 369 370 #define FLEXIO_PINREN_PRE_MASK (0xFFFFFFFFU) 371 #define FLEXIO_PINREN_PRE_SHIFT (0U) 372 #define FLEXIO_PINREN_PRE_WIDTH (32U) 373 #define FLEXIO_PINREN_PRE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINREN_PRE_SHIFT)) & FLEXIO_PINREN_PRE_MASK) 374 /*! @} */ 375 376 /*! @name PINFEN - Pin Falling Edge Enable Register */ 377 /*! @{ */ 378 379 #define FLEXIO_PINFEN_PFE_MASK (0xFFFFFFFFU) 380 #define FLEXIO_PINFEN_PFE_SHIFT (0U) 381 #define FLEXIO_PINFEN_PFE_WIDTH (32U) 382 #define FLEXIO_PINFEN_PFE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINFEN_PFE_SHIFT)) & FLEXIO_PINFEN_PFE_MASK) 383 /*! @} */ 384 385 /*! @name PINOUTD - Pin Output Data Register */ 386 /*! @{ */ 387 388 #define FLEXIO_PINOUTD_OUTD_MASK (0xFFFFFFFFU) 389 #define FLEXIO_PINOUTD_OUTD_SHIFT (0U) 390 #define FLEXIO_PINOUTD_OUTD_WIDTH (32U) 391 #define FLEXIO_PINOUTD_OUTD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTD_OUTD_SHIFT)) & FLEXIO_PINOUTD_OUTD_MASK) 392 /*! @} */ 393 394 /*! @name PINOUTE - Pin Output Enable Register */ 395 /*! @{ */ 396 397 #define FLEXIO_PINOUTE_OUTE_MASK (0xFFFFFFFFU) 398 #define FLEXIO_PINOUTE_OUTE_SHIFT (0U) 399 #define FLEXIO_PINOUTE_OUTE_WIDTH (32U) 400 #define FLEXIO_PINOUTE_OUTE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTE_OUTE_SHIFT)) & FLEXIO_PINOUTE_OUTE_MASK) 401 /*! @} */ 402 403 /*! @name PINOUTDIS - Pin Output Disable Register */ 404 /*! @{ */ 405 406 #define FLEXIO_PINOUTDIS_OUTDIS_MASK (0xFFFFFFFFU) 407 #define FLEXIO_PINOUTDIS_OUTDIS_SHIFT (0U) 408 #define FLEXIO_PINOUTDIS_OUTDIS_WIDTH (32U) 409 #define FLEXIO_PINOUTDIS_OUTDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTDIS_OUTDIS_SHIFT)) & FLEXIO_PINOUTDIS_OUTDIS_MASK) 410 /*! @} */ 411 412 /*! @name PINOUTCLR - Pin Output Clear Register */ 413 /*! @{ */ 414 415 #define FLEXIO_PINOUTCLR_OUTCLR_MASK (0xFFFFFFFFU) 416 #define FLEXIO_PINOUTCLR_OUTCLR_SHIFT (0U) 417 #define FLEXIO_PINOUTCLR_OUTCLR_WIDTH (32U) 418 #define FLEXIO_PINOUTCLR_OUTCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTCLR_OUTCLR_SHIFT)) & FLEXIO_PINOUTCLR_OUTCLR_MASK) 419 /*! @} */ 420 421 /*! @name PINOUTSET - Pin Output Set Register */ 422 /*! @{ */ 423 424 #define FLEXIO_PINOUTSET_OUTSET_MASK (0xFFFFFFFFU) 425 #define FLEXIO_PINOUTSET_OUTSET_SHIFT (0U) 426 #define FLEXIO_PINOUTSET_OUTSET_WIDTH (32U) 427 #define FLEXIO_PINOUTSET_OUTSET(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTSET_OUTSET_SHIFT)) & FLEXIO_PINOUTSET_OUTSET_MASK) 428 /*! @} */ 429 430 /*! @name PINOUTTOG - Pin Output Toggle Register */ 431 /*! @{ */ 432 433 #define FLEXIO_PINOUTTOG_OUTTOG_MASK (0xFFFFFFFFU) 434 #define FLEXIO_PINOUTTOG_OUTTOG_SHIFT (0U) 435 #define FLEXIO_PINOUTTOG_OUTTOG_WIDTH (32U) 436 #define FLEXIO_PINOUTTOG_OUTTOG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTTOG_OUTTOG_SHIFT)) & FLEXIO_PINOUTTOG_OUTTOG_MASK) 437 /*! @} */ 438 439 /*! @name SHIFTCTL - Shifter Control N Register */ 440 /*! @{ */ 441 442 #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) 443 #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) 444 #define FLEXIO_SHIFTCTL_SMOD_WIDTH (3U) 445 #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) 446 447 #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) 448 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) 449 #define FLEXIO_SHIFTCTL_PINPOL_WIDTH (1U) 450 #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) 451 452 #define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) 453 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) 454 #define FLEXIO_SHIFTCTL_PINSEL_WIDTH (5U) 455 #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) 456 457 #define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) 458 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) 459 #define FLEXIO_SHIFTCTL_PINCFG_WIDTH (2U) 460 #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) 461 462 #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) 463 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) 464 #define FLEXIO_SHIFTCTL_TIMPOL_WIDTH (1U) 465 #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) 466 467 #define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U) 468 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) 469 #define FLEXIO_SHIFTCTL_TIMSEL_WIDTH (3U) 470 #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) 471 /*! @} */ 472 473 /*! @name SHIFTCFG - Shifter Configuration N Register */ 474 /*! @{ */ 475 476 #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) 477 #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) 478 #define FLEXIO_SHIFTCFG_SSTART_WIDTH (2U) 479 #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) 480 481 #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) 482 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) 483 #define FLEXIO_SHIFTCFG_SSTOP_WIDTH (2U) 484 #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) 485 486 #define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) 487 #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) 488 #define FLEXIO_SHIFTCFG_INSRC_WIDTH (1U) 489 #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) 490 491 #define FLEXIO_SHIFTCFG_LATST_MASK (0x200U) 492 #define FLEXIO_SHIFTCFG_LATST_SHIFT (9U) 493 #define FLEXIO_SHIFTCFG_LATST_WIDTH (1U) 494 #define FLEXIO_SHIFTCFG_LATST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK) 495 496 #define FLEXIO_SHIFTCFG_SSIZE_MASK (0x1000U) 497 #define FLEXIO_SHIFTCFG_SSIZE_SHIFT (12U) 498 #define FLEXIO_SHIFTCFG_SSIZE_WIDTH (1U) 499 #define FLEXIO_SHIFTCFG_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSIZE_SHIFT)) & FLEXIO_SHIFTCFG_SSIZE_MASK) 500 501 #define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) 502 #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) 503 #define FLEXIO_SHIFTCFG_PWIDTH_WIDTH (5U) 504 #define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) 505 /*! @} */ 506 507 /*! @name SHIFTBUF - Shifter Buffer N Register */ 508 /*! @{ */ 509 510 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) 511 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) 512 #define FLEXIO_SHIFTBUF_SHIFTBUF_WIDTH (32U) 513 #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) 514 /*! @} */ 515 516 /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ 517 /*! @{ */ 518 519 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) 520 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) 521 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_WIDTH (32U) 522 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) 523 /*! @} */ 524 525 /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ 526 /*! @{ */ 527 528 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) 529 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) 530 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_WIDTH (32U) 531 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) 532 /*! @} */ 533 534 /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ 535 /*! @{ */ 536 537 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) 538 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) 539 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_WIDTH (32U) 540 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) 541 /*! @} */ 542 543 /*! @name TIMCTL - Timer Control N Register */ 544 /*! @{ */ 545 546 #define FLEXIO_TIMCTL_TIMOD_MASK (0x7U) 547 #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) 548 #define FLEXIO_TIMCTL_TIMOD_WIDTH (3U) 549 #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) 550 551 #define FLEXIO_TIMCTL_ONETIM_MASK (0x20U) 552 #define FLEXIO_TIMCTL_ONETIM_SHIFT (5U) 553 #define FLEXIO_TIMCTL_ONETIM_WIDTH (1U) 554 #define FLEXIO_TIMCTL_ONETIM(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK) 555 556 #define FLEXIO_TIMCTL_PININS_MASK (0x40U) 557 #define FLEXIO_TIMCTL_PININS_SHIFT (6U) 558 #define FLEXIO_TIMCTL_PININS_WIDTH (1U) 559 #define FLEXIO_TIMCTL_PININS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK) 560 561 #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) 562 #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) 563 #define FLEXIO_TIMCTL_PINPOL_WIDTH (1U) 564 #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) 565 566 #define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) 567 #define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) 568 #define FLEXIO_TIMCTL_PINSEL_WIDTH (5U) 569 #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) 570 571 #define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) 572 #define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) 573 #define FLEXIO_TIMCTL_PINCFG_WIDTH (2U) 574 #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) 575 576 #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) 577 #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) 578 #define FLEXIO_TIMCTL_TRGSRC_WIDTH (1U) 579 #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) 580 581 #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) 582 #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) 583 #define FLEXIO_TIMCTL_TRGPOL_WIDTH (1U) 584 #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) 585 586 #define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) 587 #define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) 588 #define FLEXIO_TIMCTL_TRGSEL_WIDTH (6U) 589 #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) 590 /*! @} */ 591 592 /*! @name TIMCFG - Timer Configuration N Register */ 593 /*! @{ */ 594 595 #define FLEXIO_TIMCFG_TSTART_MASK (0x2U) 596 #define FLEXIO_TIMCFG_TSTART_SHIFT (1U) 597 #define FLEXIO_TIMCFG_TSTART_WIDTH (1U) 598 #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) 599 600 #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) 601 #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) 602 #define FLEXIO_TIMCFG_TSTOP_WIDTH (2U) 603 #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) 604 605 #define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) 606 #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) 607 #define FLEXIO_TIMCFG_TIMENA_WIDTH (3U) 608 #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) 609 610 #define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) 611 #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) 612 #define FLEXIO_TIMCFG_TIMDIS_WIDTH (3U) 613 #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) 614 615 #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) 616 #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) 617 #define FLEXIO_TIMCFG_TIMRST_WIDTH (3U) 618 #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) 619 620 #define FLEXIO_TIMCFG_TIMDEC_MASK (0x700000U) 621 #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) 622 #define FLEXIO_TIMCFG_TIMDEC_WIDTH (3U) 623 #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) 624 625 #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) 626 #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) 627 #define FLEXIO_TIMCFG_TIMOUT_WIDTH (2U) 628 #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) 629 /*! @} */ 630 631 /*! @name TIMCMP - Timer Compare N Register */ 632 /*! @{ */ 633 634 #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) 635 #define FLEXIO_TIMCMP_CMP_SHIFT (0U) 636 #define FLEXIO_TIMCMP_CMP_WIDTH (16U) 637 #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) 638 /*! @} */ 639 640 /*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */ 641 /*! @{ */ 642 643 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) 644 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) 645 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_WIDTH (32U) 646 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) 647 /*! @} */ 648 649 /*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */ 650 /*! @{ */ 651 652 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) 653 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) 654 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_WIDTH (32U) 655 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) 656 /*! @} */ 657 658 /*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */ 659 /*! @{ */ 660 661 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) 662 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) 663 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_WIDTH (32U) 664 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) 665 /*! @} */ 666 667 /*! @name SHIFTBUFOES - Shifter Buffer N Odd Even Swapped Register */ 668 /*! @{ */ 669 670 #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK (0xFFFFFFFFU) 671 #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT (0U) 672 #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_WIDTH (32U) 673 #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK) 674 /*! @} */ 675 676 /*! @name SHIFTBUFEOS - Shifter Buffer N Even Odd Swapped Register */ 677 /*! @{ */ 678 679 #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK (0xFFFFFFFFU) 680 #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT (0U) 681 #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_WIDTH (32U) 682 #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK) 683 /*! @} */ 684 685 /*! @name SHIFTBUFHBS - Shifter Buffer N Halfword Byte Swapped Register */ 686 /*! @{ */ 687 688 #define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK (0xFFFFFFFFU) 689 #define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT (0U) 690 #define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_WIDTH (32U) 691 #define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT)) & FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK) 692 /*! @} */ 693 694 /*! 695 * @} 696 */ /* end of group FLEXIO_Register_Masks */ 697 698 /*! 699 * @} 700 */ /* end of group FLEXIO_Peripheral_Access_Layer */ 701 702 #endif /* #if !defined(S32K344_FLEXIO_H_) */ 703
