1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_FCCU.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_FCCU 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_FCCU_H_) /* Check if memory map has not been already included */ 58 #define S32K344_FCCU_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- FCCU Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup FCCU_Peripheral_Access_Layer FCCU Peripheral Access Layer 68 * @{ 69 */ 70 71 /** FCCU - Size of Registers Arrays */ 72 #define FCCU_NCF_CFG_COUNT 1u 73 #define FCCU_NCFS_CFG_COUNT 1u 74 #define FCCU_NCF_S_COUNT 1u 75 #define FCCU_NCF_E_COUNT 1u 76 #define FCCU_NCF_TOE_COUNT 1u 77 #define FCCU_IRQ_ALARM_EN_COUNT 1u 78 #define FCCU_NMI_EN_COUNT 1u 79 #define FCCU_EOUT_SIG_EN_COUNT 1u 80 81 /** FCCU - Register Layout Typedef */ 82 typedef struct { 83 __IO uint32_t CTRL; /**< Control, offset: 0x0 */ 84 __O uint32_t CTRLK; /**< Control Key, offset: 0x4 */ 85 __IO uint32_t CFG; /**< Configuration, offset: 0x8 */ 86 uint8_t RESERVED_0[16]; 87 __IO uint32_t NCF_CFG[FCCU_NCF_CFG_COUNT]; /**< Non-critical Fault Configuration, array offset: 0x1C, array step: 0x4 */ 88 uint8_t RESERVED_1[44]; 89 __IO uint32_t NCFS_CFG[FCCU_NCFS_CFG_COUNT]; /**< Non-critical Fault-State Configuration, array offset: 0x4C, array step: 0x4 */ 90 uint8_t RESERVED_2[48]; 91 __IO uint32_t NCF_S[FCCU_NCF_S_COUNT]; /**< Non-critical Fault Status, array offset: 0x80, array step: 0x4 */ 92 uint8_t RESERVED_3[12]; 93 __O uint32_t NCFK; /**< Non-critical Fault Key, offset: 0x90 */ 94 __IO uint32_t NCF_E[FCCU_NCF_E_COUNT]; /**< Non-critical Fault Enable, array offset: 0x94, array step: 0x4 */ 95 uint8_t RESERVED_4[12]; 96 __IO uint32_t NCF_TOE[FCCU_NCF_TOE_COUNT]; /**< Non-critical-Fault Alarm-State Timeout Enable, array offset: 0xA4, array step: 0x4 */ 97 uint8_t RESERVED_5[12]; 98 __IO uint32_t NCF_TO; /**< Non-critical-Fault Alarm-State Timeout Interval, offset: 0xB4 */ 99 __IO uint32_t CFG_TO; /**< Configuration-State Timeout Interval, offset: 0xB8 */ 100 __IO uint32_t EINOUT; /**< IO Control, offset: 0xBC */ 101 __I uint32_t STAT; /**< Status, offset: 0xC0 */ 102 __I uint32_t N2AF_STATUS; /**< Normal-to-Alarm Freeze Status, offset: 0xC4 */ 103 __I uint32_t A2FF_STATUS; /**< Alarm-to-Fault Freeze Status, offset: 0xC8 */ 104 __I uint32_t N2FF_STATUS; /**< Normal-to-Fault Freeze Status, offset: 0xCC */ 105 __I uint32_t F2AF_STATUS; /**< Fault-to-Alarm Freeze Status, offset: 0xD0 */ 106 uint8_t RESERVED_6[8]; 107 __O uint32_t NCFF; /**< Non-critical Fault Fake, offset: 0xDC */ 108 __IO uint32_t IRQ_STAT; /**< IRQ Status, offset: 0xE0 */ 109 __IO uint32_t IRQ_EN; /**< IRQ Enable, offset: 0xE4 */ 110 uint8_t RESERVED_7[8]; 111 __O uint32_t TRANS_LOCK; /**< Transient Configuration Lock, offset: 0xF0 */ 112 __O uint32_t PERMNT_LOCK; /**< Permanent Configuration Lock, offset: 0xF4 */ 113 __IO uint32_t DELTA_T; /**< Delta T, offset: 0xF8 */ 114 __IO uint32_t IRQ_ALARM_EN[FCCU_IRQ_ALARM_EN_COUNT]; /**< Non-critical Alarm-State Interrupt-Request Enable, array offset: 0xFC, array step: 0x4 */ 115 uint8_t RESERVED_8[12]; 116 __IO uint32_t NMI_EN[FCCU_NMI_EN_COUNT]; /**< Non-critical Fault-State Non-maskable-Interrupt-Request Enable, array offset: 0x10C, array step: 0x4 */ 117 uint8_t RESERVED_9[12]; 118 __IO uint32_t EOUT_SIG_EN[FCCU_EOUT_SIG_EN_COUNT]; /**< Non-critical Fault-State EOUT Signaling Enable, array offset: 0x11C, array step: 0x4 */ 119 uint8_t RESERVED_10[12]; 120 __I uint32_t TMR_ALARM; /**< Alarm-State Timer, offset: 0x12C */ 121 uint8_t RESERVED_11[4]; 122 __I uint32_t TMR_CFG; /**< Configuration-State Timer, offset: 0x134 */ 123 __I uint32_t TMR_ETMR; /**< Fault-Output Timer, offset: 0x138 */ 124 } FCCU_Type, *FCCU_MemMapPtr; 125 126 /** Number of instances of the FCCU module. */ 127 #define FCCU_INSTANCE_COUNT (1u) 128 129 /* FCCU - Peripheral instance base addresses */ 130 /** Peripheral FCCU base address */ 131 #define IP_FCCU_BASE (0x40384000u) 132 /** Peripheral FCCU base pointer */ 133 #define IP_FCCU ((FCCU_Type *)IP_FCCU_BASE) 134 /** Array initializer of FCCU peripheral base addresses */ 135 #define IP_FCCU_BASE_ADDRS { IP_FCCU_BASE } 136 /** Array initializer of FCCU peripheral base pointers */ 137 #define IP_FCCU_BASE_PTRS { IP_FCCU } 138 139 /* ---------------------------------------------------------------------------- 140 -- FCCU Register Masks 141 ---------------------------------------------------------------------------- */ 142 143 /*! 144 * @addtogroup FCCU_Register_Masks FCCU Register Masks 145 * @{ 146 */ 147 148 /*! @name CTRL - Control */ 149 /*! @{ */ 150 151 #define FCCU_CTRL_OPR_MASK (0x1FU) 152 #define FCCU_CTRL_OPR_SHIFT (0U) 153 #define FCCU_CTRL_OPR_WIDTH (5U) 154 #define FCCU_CTRL_OPR(x) (((uint32_t)(((uint32_t)(x)) << FCCU_CTRL_OPR_SHIFT)) & FCCU_CTRL_OPR_MASK) 155 156 #define FCCU_CTRL_OPS_MASK (0xC0U) 157 #define FCCU_CTRL_OPS_SHIFT (6U) 158 #define FCCU_CTRL_OPS_WIDTH (2U) 159 #define FCCU_CTRL_OPS(x) (((uint32_t)(((uint32_t)(x)) << FCCU_CTRL_OPS_SHIFT)) & FCCU_CTRL_OPS_MASK) 160 161 #define FCCU_CTRL_DEBUG_MASK (0x200U) 162 #define FCCU_CTRL_DEBUG_SHIFT (9U) 163 #define FCCU_CTRL_DEBUG_WIDTH (1U) 164 #define FCCU_CTRL_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << FCCU_CTRL_DEBUG_SHIFT)) & FCCU_CTRL_DEBUG_MASK) 165 /*! @} */ 166 167 /*! @name CTRLK - Control Key */ 168 /*! @{ */ 169 170 #define FCCU_CTRLK_CTRLK_MASK (0xFFFFFFFFU) 171 #define FCCU_CTRLK_CTRLK_SHIFT (0U) 172 #define FCCU_CTRLK_CTRLK_WIDTH (32U) 173 #define FCCU_CTRLK_CTRLK(x) (((uint32_t)(((uint32_t)(x)) << FCCU_CTRLK_CTRLK_SHIFT)) & FCCU_CTRLK_CTRLK_MASK) 174 /*! @} */ 175 176 /*! @name CFG - Configuration */ 177 /*! @{ */ 178 179 #define FCCU_CFG_FOM_MASK (0x1C0U) 180 #define FCCU_CFG_FOM_SHIFT (6U) 181 #define FCCU_CFG_FOM_WIDTH (3U) 182 #define FCCU_CFG_FOM(x) (((uint32_t)(((uint32_t)(x)) << FCCU_CFG_FOM_SHIFT)) & FCCU_CFG_FOM_MASK) 183 184 #define FCCU_CFG_PS_MASK (0x200U) 185 #define FCCU_CFG_PS_SHIFT (9U) 186 #define FCCU_CFG_PS_WIDTH (1U) 187 #define FCCU_CFG_PS(x) (((uint32_t)(((uint32_t)(x)) << FCCU_CFG_PS_SHIFT)) & FCCU_CFG_PS_MASK) 188 189 #define FCCU_CFG_CM_MASK (0x800U) 190 #define FCCU_CFG_CM_SHIFT (11U) 191 #define FCCU_CFG_CM_WIDTH (1U) 192 #define FCCU_CFG_CM(x) (((uint32_t)(((uint32_t)(x)) << FCCU_CFG_CM_SHIFT)) & FCCU_CFG_CM_MASK) 193 194 #define FCCU_CFG_FCCU_SET_CLEAR_MASK (0xC00000U) 195 #define FCCU_CFG_FCCU_SET_CLEAR_SHIFT (22U) 196 #define FCCU_CFG_FCCU_SET_CLEAR_WIDTH (2U) 197 #define FCCU_CFG_FCCU_SET_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << FCCU_CFG_FCCU_SET_CLEAR_SHIFT)) & FCCU_CFG_FCCU_SET_CLEAR_MASK) 198 199 #define FCCU_CFG_FCCU_SET_AFTER_RESET_MASK (0x1000000U) 200 #define FCCU_CFG_FCCU_SET_AFTER_RESET_SHIFT (24U) 201 #define FCCU_CFG_FCCU_SET_AFTER_RESET_WIDTH (1U) 202 #define FCCU_CFG_FCCU_SET_AFTER_RESET(x) (((uint32_t)(((uint32_t)(x)) << FCCU_CFG_FCCU_SET_AFTER_RESET_SHIFT)) & FCCU_CFG_FCCU_SET_AFTER_RESET_MASK) 203 /*! @} */ 204 205 /*! @name NCF_CFG - Non-critical Fault Configuration */ 206 /*! @{ */ 207 208 #define FCCU_NCF_CFG_NCFC0_MASK (0x1U) 209 #define FCCU_NCF_CFG_NCFC0_SHIFT (0U) 210 #define FCCU_NCF_CFG_NCFC0_WIDTH (1U) 211 #define FCCU_NCF_CFG_NCFC0(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_CFG_NCFC0_SHIFT)) & FCCU_NCF_CFG_NCFC0_MASK) 212 213 #define FCCU_NCF_CFG_NCFC1_MASK (0x2U) 214 #define FCCU_NCF_CFG_NCFC1_SHIFT (1U) 215 #define FCCU_NCF_CFG_NCFC1_WIDTH (1U) 216 #define FCCU_NCF_CFG_NCFC1(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_CFG_NCFC1_SHIFT)) & FCCU_NCF_CFG_NCFC1_MASK) 217 218 #define FCCU_NCF_CFG_NCFC2_MASK (0x4U) 219 #define FCCU_NCF_CFG_NCFC2_SHIFT (2U) 220 #define FCCU_NCF_CFG_NCFC2_WIDTH (1U) 221 #define FCCU_NCF_CFG_NCFC2(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_CFG_NCFC2_SHIFT)) & FCCU_NCF_CFG_NCFC2_MASK) 222 223 #define FCCU_NCF_CFG_NCFC3_MASK (0x8U) 224 #define FCCU_NCF_CFG_NCFC3_SHIFT (3U) 225 #define FCCU_NCF_CFG_NCFC3_WIDTH (1U) 226 #define FCCU_NCF_CFG_NCFC3(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_CFG_NCFC3_SHIFT)) & FCCU_NCF_CFG_NCFC3_MASK) 227 228 #define FCCU_NCF_CFG_NCFC4_MASK (0x10U) 229 #define FCCU_NCF_CFG_NCFC4_SHIFT (4U) 230 #define FCCU_NCF_CFG_NCFC4_WIDTH (1U) 231 #define FCCU_NCF_CFG_NCFC4(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_CFG_NCFC4_SHIFT)) & FCCU_NCF_CFG_NCFC4_MASK) 232 233 #define FCCU_NCF_CFG_NCFC5_MASK (0x20U) 234 #define FCCU_NCF_CFG_NCFC5_SHIFT (5U) 235 #define FCCU_NCF_CFG_NCFC5_WIDTH (1U) 236 #define FCCU_NCF_CFG_NCFC5(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_CFG_NCFC5_SHIFT)) & FCCU_NCF_CFG_NCFC5_MASK) 237 238 #define FCCU_NCF_CFG_NCFC6_MASK (0x40U) 239 #define FCCU_NCF_CFG_NCFC6_SHIFT (6U) 240 #define FCCU_NCF_CFG_NCFC6_WIDTH (1U) 241 #define FCCU_NCF_CFG_NCFC6(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_CFG_NCFC6_SHIFT)) & FCCU_NCF_CFG_NCFC6_MASK) 242 243 #define FCCU_NCF_CFG_NCFC7_MASK (0x80U) 244 #define FCCU_NCF_CFG_NCFC7_SHIFT (7U) 245 #define FCCU_NCF_CFG_NCFC7_WIDTH (1U) 246 #define FCCU_NCF_CFG_NCFC7(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_CFG_NCFC7_SHIFT)) & FCCU_NCF_CFG_NCFC7_MASK) 247 /*! @} */ 248 249 /*! @name NCFS_CFG - Non-critical Fault-State Configuration */ 250 /*! @{ */ 251 252 #define FCCU_NCFS_CFG_NCFSC0_MASK (0x3U) 253 #define FCCU_NCFS_CFG_NCFSC0_SHIFT (0U) 254 #define FCCU_NCFS_CFG_NCFSC0_WIDTH (2U) 255 #define FCCU_NCFS_CFG_NCFSC0(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCFS_CFG_NCFSC0_SHIFT)) & FCCU_NCFS_CFG_NCFSC0_MASK) 256 257 #define FCCU_NCFS_CFG_NCFSC1_MASK (0xCU) 258 #define FCCU_NCFS_CFG_NCFSC1_SHIFT (2U) 259 #define FCCU_NCFS_CFG_NCFSC1_WIDTH (2U) 260 #define FCCU_NCFS_CFG_NCFSC1(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCFS_CFG_NCFSC1_SHIFT)) & FCCU_NCFS_CFG_NCFSC1_MASK) 261 262 #define FCCU_NCFS_CFG_NCFSC2_MASK (0x30U) 263 #define FCCU_NCFS_CFG_NCFSC2_SHIFT (4U) 264 #define FCCU_NCFS_CFG_NCFSC2_WIDTH (2U) 265 #define FCCU_NCFS_CFG_NCFSC2(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCFS_CFG_NCFSC2_SHIFT)) & FCCU_NCFS_CFG_NCFSC2_MASK) 266 267 #define FCCU_NCFS_CFG_NCFSC3_MASK (0xC0U) 268 #define FCCU_NCFS_CFG_NCFSC3_SHIFT (6U) 269 #define FCCU_NCFS_CFG_NCFSC3_WIDTH (2U) 270 #define FCCU_NCFS_CFG_NCFSC3(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCFS_CFG_NCFSC3_SHIFT)) & FCCU_NCFS_CFG_NCFSC3_MASK) 271 272 #define FCCU_NCFS_CFG_NCFSC4_MASK (0x300U) 273 #define FCCU_NCFS_CFG_NCFSC4_SHIFT (8U) 274 #define FCCU_NCFS_CFG_NCFSC4_WIDTH (2U) 275 #define FCCU_NCFS_CFG_NCFSC4(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCFS_CFG_NCFSC4_SHIFT)) & FCCU_NCFS_CFG_NCFSC4_MASK) 276 277 #define FCCU_NCFS_CFG_NCFSC5_MASK (0xC00U) 278 #define FCCU_NCFS_CFG_NCFSC5_SHIFT (10U) 279 #define FCCU_NCFS_CFG_NCFSC5_WIDTH (2U) 280 #define FCCU_NCFS_CFG_NCFSC5(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCFS_CFG_NCFSC5_SHIFT)) & FCCU_NCFS_CFG_NCFSC5_MASK) 281 282 #define FCCU_NCFS_CFG_NCFSC6_MASK (0x3000U) 283 #define FCCU_NCFS_CFG_NCFSC6_SHIFT (12U) 284 #define FCCU_NCFS_CFG_NCFSC6_WIDTH (2U) 285 #define FCCU_NCFS_CFG_NCFSC6(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCFS_CFG_NCFSC6_SHIFT)) & FCCU_NCFS_CFG_NCFSC6_MASK) 286 287 #define FCCU_NCFS_CFG_NCFSC7_MASK (0xC000U) 288 #define FCCU_NCFS_CFG_NCFSC7_SHIFT (14U) 289 #define FCCU_NCFS_CFG_NCFSC7_WIDTH (2U) 290 #define FCCU_NCFS_CFG_NCFSC7(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCFS_CFG_NCFSC7_SHIFT)) & FCCU_NCFS_CFG_NCFSC7_MASK) 291 /*! @} */ 292 293 /*! @name NCF_S - Non-critical Fault Status */ 294 /*! @{ */ 295 296 #define FCCU_NCF_S_NCFS0_MASK (0x1U) 297 #define FCCU_NCF_S_NCFS0_SHIFT (0U) 298 #define FCCU_NCF_S_NCFS0_WIDTH (1U) 299 #define FCCU_NCF_S_NCFS0(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_S_NCFS0_SHIFT)) & FCCU_NCF_S_NCFS0_MASK) 300 301 #define FCCU_NCF_S_NCFS1_MASK (0x2U) 302 #define FCCU_NCF_S_NCFS1_SHIFT (1U) 303 #define FCCU_NCF_S_NCFS1_WIDTH (1U) 304 #define FCCU_NCF_S_NCFS1(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_S_NCFS1_SHIFT)) & FCCU_NCF_S_NCFS1_MASK) 305 306 #define FCCU_NCF_S_NCFS2_MASK (0x4U) 307 #define FCCU_NCF_S_NCFS2_SHIFT (2U) 308 #define FCCU_NCF_S_NCFS2_WIDTH (1U) 309 #define FCCU_NCF_S_NCFS2(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_S_NCFS2_SHIFT)) & FCCU_NCF_S_NCFS2_MASK) 310 311 #define FCCU_NCF_S_NCFS3_MASK (0x8U) 312 #define FCCU_NCF_S_NCFS3_SHIFT (3U) 313 #define FCCU_NCF_S_NCFS3_WIDTH (1U) 314 #define FCCU_NCF_S_NCFS3(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_S_NCFS3_SHIFT)) & FCCU_NCF_S_NCFS3_MASK) 315 316 #define FCCU_NCF_S_NCFS4_MASK (0x10U) 317 #define FCCU_NCF_S_NCFS4_SHIFT (4U) 318 #define FCCU_NCF_S_NCFS4_WIDTH (1U) 319 #define FCCU_NCF_S_NCFS4(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_S_NCFS4_SHIFT)) & FCCU_NCF_S_NCFS4_MASK) 320 321 #define FCCU_NCF_S_NCFS5_MASK (0x20U) 322 #define FCCU_NCF_S_NCFS5_SHIFT (5U) 323 #define FCCU_NCF_S_NCFS5_WIDTH (1U) 324 #define FCCU_NCF_S_NCFS5(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_S_NCFS5_SHIFT)) & FCCU_NCF_S_NCFS5_MASK) 325 326 #define FCCU_NCF_S_NCFS6_MASK (0x40U) 327 #define FCCU_NCF_S_NCFS6_SHIFT (6U) 328 #define FCCU_NCF_S_NCFS6_WIDTH (1U) 329 #define FCCU_NCF_S_NCFS6(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_S_NCFS6_SHIFT)) & FCCU_NCF_S_NCFS6_MASK) 330 331 #define FCCU_NCF_S_NCFS7_MASK (0x80U) 332 #define FCCU_NCF_S_NCFS7_SHIFT (7U) 333 #define FCCU_NCF_S_NCFS7_WIDTH (1U) 334 #define FCCU_NCF_S_NCFS7(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_S_NCFS7_SHIFT)) & FCCU_NCF_S_NCFS7_MASK) 335 /*! @} */ 336 337 /*! @name NCFK - Non-critical Fault Key */ 338 /*! @{ */ 339 340 #define FCCU_NCFK_NCFK_MASK (0xFFFFFFFFU) 341 #define FCCU_NCFK_NCFK_SHIFT (0U) 342 #define FCCU_NCFK_NCFK_WIDTH (32U) 343 #define FCCU_NCFK_NCFK(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCFK_NCFK_SHIFT)) & FCCU_NCFK_NCFK_MASK) 344 /*! @} */ 345 346 /*! @name NCF_E - Non-critical Fault Enable */ 347 /*! @{ */ 348 349 #define FCCU_NCF_E_NCFE0_MASK (0x1U) 350 #define FCCU_NCF_E_NCFE0_SHIFT (0U) 351 #define FCCU_NCF_E_NCFE0_WIDTH (1U) 352 #define FCCU_NCF_E_NCFE0(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_E_NCFE0_SHIFT)) & FCCU_NCF_E_NCFE0_MASK) 353 354 #define FCCU_NCF_E_NCFE1_MASK (0x2U) 355 #define FCCU_NCF_E_NCFE1_SHIFT (1U) 356 #define FCCU_NCF_E_NCFE1_WIDTH (1U) 357 #define FCCU_NCF_E_NCFE1(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_E_NCFE1_SHIFT)) & FCCU_NCF_E_NCFE1_MASK) 358 359 #define FCCU_NCF_E_NCFE2_MASK (0x4U) 360 #define FCCU_NCF_E_NCFE2_SHIFT (2U) 361 #define FCCU_NCF_E_NCFE2_WIDTH (1U) 362 #define FCCU_NCF_E_NCFE2(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_E_NCFE2_SHIFT)) & FCCU_NCF_E_NCFE2_MASK) 363 364 #define FCCU_NCF_E_NCFE3_MASK (0x8U) 365 #define FCCU_NCF_E_NCFE3_SHIFT (3U) 366 #define FCCU_NCF_E_NCFE3_WIDTH (1U) 367 #define FCCU_NCF_E_NCFE3(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_E_NCFE3_SHIFT)) & FCCU_NCF_E_NCFE3_MASK) 368 369 #define FCCU_NCF_E_NCFE4_MASK (0x10U) 370 #define FCCU_NCF_E_NCFE4_SHIFT (4U) 371 #define FCCU_NCF_E_NCFE4_WIDTH (1U) 372 #define FCCU_NCF_E_NCFE4(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_E_NCFE4_SHIFT)) & FCCU_NCF_E_NCFE4_MASK) 373 374 #define FCCU_NCF_E_NCFE5_MASK (0x20U) 375 #define FCCU_NCF_E_NCFE5_SHIFT (5U) 376 #define FCCU_NCF_E_NCFE5_WIDTH (1U) 377 #define FCCU_NCF_E_NCFE5(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_E_NCFE5_SHIFT)) & FCCU_NCF_E_NCFE5_MASK) 378 379 #define FCCU_NCF_E_NCFE6_MASK (0x40U) 380 #define FCCU_NCF_E_NCFE6_SHIFT (6U) 381 #define FCCU_NCF_E_NCFE6_WIDTH (1U) 382 #define FCCU_NCF_E_NCFE6(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_E_NCFE6_SHIFT)) & FCCU_NCF_E_NCFE6_MASK) 383 384 #define FCCU_NCF_E_NCFE7_MASK (0x80U) 385 #define FCCU_NCF_E_NCFE7_SHIFT (7U) 386 #define FCCU_NCF_E_NCFE7_WIDTH (1U) 387 #define FCCU_NCF_E_NCFE7(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_E_NCFE7_SHIFT)) & FCCU_NCF_E_NCFE7_MASK) 388 /*! @} */ 389 390 /*! @name NCF_TOE - Non-critical-Fault Alarm-State Timeout Enable */ 391 /*! @{ */ 392 393 #define FCCU_NCF_TOE_NCFTOE0_MASK (0x1U) 394 #define FCCU_NCF_TOE_NCFTOE0_SHIFT (0U) 395 #define FCCU_NCF_TOE_NCFTOE0_WIDTH (1U) 396 #define FCCU_NCF_TOE_NCFTOE0(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_TOE_NCFTOE0_SHIFT)) & FCCU_NCF_TOE_NCFTOE0_MASK) 397 398 #define FCCU_NCF_TOE_NCFTOE1_MASK (0x2U) 399 #define FCCU_NCF_TOE_NCFTOE1_SHIFT (1U) 400 #define FCCU_NCF_TOE_NCFTOE1_WIDTH (1U) 401 #define FCCU_NCF_TOE_NCFTOE1(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_TOE_NCFTOE1_SHIFT)) & FCCU_NCF_TOE_NCFTOE1_MASK) 402 403 #define FCCU_NCF_TOE_NCFTOE2_MASK (0x4U) 404 #define FCCU_NCF_TOE_NCFTOE2_SHIFT (2U) 405 #define FCCU_NCF_TOE_NCFTOE2_WIDTH (1U) 406 #define FCCU_NCF_TOE_NCFTOE2(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_TOE_NCFTOE2_SHIFT)) & FCCU_NCF_TOE_NCFTOE2_MASK) 407 408 #define FCCU_NCF_TOE_NCFTOE3_MASK (0x8U) 409 #define FCCU_NCF_TOE_NCFTOE3_SHIFT (3U) 410 #define FCCU_NCF_TOE_NCFTOE3_WIDTH (1U) 411 #define FCCU_NCF_TOE_NCFTOE3(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_TOE_NCFTOE3_SHIFT)) & FCCU_NCF_TOE_NCFTOE3_MASK) 412 413 #define FCCU_NCF_TOE_NCFTOE4_MASK (0x10U) 414 #define FCCU_NCF_TOE_NCFTOE4_SHIFT (4U) 415 #define FCCU_NCF_TOE_NCFTOE4_WIDTH (1U) 416 #define FCCU_NCF_TOE_NCFTOE4(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_TOE_NCFTOE4_SHIFT)) & FCCU_NCF_TOE_NCFTOE4_MASK) 417 418 #define FCCU_NCF_TOE_NCFTOE5_MASK (0x20U) 419 #define FCCU_NCF_TOE_NCFTOE5_SHIFT (5U) 420 #define FCCU_NCF_TOE_NCFTOE5_WIDTH (1U) 421 #define FCCU_NCF_TOE_NCFTOE5(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_TOE_NCFTOE5_SHIFT)) & FCCU_NCF_TOE_NCFTOE5_MASK) 422 423 #define FCCU_NCF_TOE_NCFTOE6_MASK (0x40U) 424 #define FCCU_NCF_TOE_NCFTOE6_SHIFT (6U) 425 #define FCCU_NCF_TOE_NCFTOE6_WIDTH (1U) 426 #define FCCU_NCF_TOE_NCFTOE6(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_TOE_NCFTOE6_SHIFT)) & FCCU_NCF_TOE_NCFTOE6_MASK) 427 428 #define FCCU_NCF_TOE_NCFTOE7_MASK (0x80U) 429 #define FCCU_NCF_TOE_NCFTOE7_SHIFT (7U) 430 #define FCCU_NCF_TOE_NCFTOE7_WIDTH (1U) 431 #define FCCU_NCF_TOE_NCFTOE7(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_TOE_NCFTOE7_SHIFT)) & FCCU_NCF_TOE_NCFTOE7_MASK) 432 /*! @} */ 433 434 /*! @name NCF_TO - Non-critical-Fault Alarm-State Timeout Interval */ 435 /*! @{ */ 436 437 #define FCCU_NCF_TO_TO_MASK (0xFFFFFFFFU) 438 #define FCCU_NCF_TO_TO_SHIFT (0U) 439 #define FCCU_NCF_TO_TO_WIDTH (32U) 440 #define FCCU_NCF_TO_TO(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCF_TO_TO_SHIFT)) & FCCU_NCF_TO_TO_MASK) 441 /*! @} */ 442 443 /*! @name CFG_TO - Configuration-State Timeout Interval */ 444 /*! @{ */ 445 446 #define FCCU_CFG_TO_TO_MASK (0x7U) 447 #define FCCU_CFG_TO_TO_SHIFT (0U) 448 #define FCCU_CFG_TO_TO_WIDTH (3U) 449 #define FCCU_CFG_TO_TO(x) (((uint32_t)(((uint32_t)(x)) << FCCU_CFG_TO_TO_SHIFT)) & FCCU_CFG_TO_TO_MASK) 450 /*! @} */ 451 452 /*! @name EINOUT - IO Control */ 453 /*! @{ */ 454 455 #define FCCU_EINOUT_EOUT0_MASK (0x1U) 456 #define FCCU_EINOUT_EOUT0_SHIFT (0U) 457 #define FCCU_EINOUT_EOUT0_WIDTH (1U) 458 #define FCCU_EINOUT_EOUT0(x) (((uint32_t)(((uint32_t)(x)) << FCCU_EINOUT_EOUT0_SHIFT)) & FCCU_EINOUT_EOUT0_MASK) 459 460 #define FCCU_EINOUT_EOUT1_MASK (0x2U) 461 #define FCCU_EINOUT_EOUT1_SHIFT (1U) 462 #define FCCU_EINOUT_EOUT1_WIDTH (1U) 463 #define FCCU_EINOUT_EOUT1(x) (((uint32_t)(((uint32_t)(x)) << FCCU_EINOUT_EOUT1_SHIFT)) & FCCU_EINOUT_EOUT1_MASK) 464 465 #define FCCU_EINOUT_EIN0_MASK (0x10U) 466 #define FCCU_EINOUT_EIN0_SHIFT (4U) 467 #define FCCU_EINOUT_EIN0_WIDTH (1U) 468 #define FCCU_EINOUT_EIN0(x) (((uint32_t)(((uint32_t)(x)) << FCCU_EINOUT_EIN0_SHIFT)) & FCCU_EINOUT_EIN0_MASK) 469 470 #define FCCU_EINOUT_EIN1_MASK (0x20U) 471 #define FCCU_EINOUT_EIN1_SHIFT (5U) 472 #define FCCU_EINOUT_EIN1_WIDTH (1U) 473 #define FCCU_EINOUT_EIN1(x) (((uint32_t)(((uint32_t)(x)) << FCCU_EINOUT_EIN1_SHIFT)) & FCCU_EINOUT_EIN1_MASK) 474 /*! @} */ 475 476 /*! @name STAT - Status */ 477 /*! @{ */ 478 479 #define FCCU_STAT_STATUS_MASK (0x7U) 480 #define FCCU_STAT_STATUS_SHIFT (0U) 481 #define FCCU_STAT_STATUS_WIDTH (3U) 482 #define FCCU_STAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FCCU_STAT_STATUS_SHIFT)) & FCCU_STAT_STATUS_MASK) 483 484 #define FCCU_STAT_ESTAT_MASK (0x8U) 485 #define FCCU_STAT_ESTAT_SHIFT (3U) 486 #define FCCU_STAT_ESTAT_WIDTH (1U) 487 #define FCCU_STAT_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << FCCU_STAT_ESTAT_SHIFT)) & FCCU_STAT_ESTAT_MASK) 488 489 #define FCCU_STAT_PhysicErrorPin_MASK (0x30U) 490 #define FCCU_STAT_PhysicErrorPin_SHIFT (4U) 491 #define FCCU_STAT_PhysicErrorPin_WIDTH (2U) 492 #define FCCU_STAT_PhysicErrorPin(x) (((uint32_t)(((uint32_t)(x)) << FCCU_STAT_PhysicErrorPin_SHIFT)) & FCCU_STAT_PhysicErrorPin_MASK) 493 /*! @} */ 494 495 /*! @name N2AF_STATUS - Normal-to-Alarm Freeze Status */ 496 /*! @{ */ 497 498 #define FCCU_N2AF_STATUS_NAFS_MASK (0xFFU) 499 #define FCCU_N2AF_STATUS_NAFS_SHIFT (0U) 500 #define FCCU_N2AF_STATUS_NAFS_WIDTH (8U) 501 #define FCCU_N2AF_STATUS_NAFS(x) (((uint32_t)(((uint32_t)(x)) << FCCU_N2AF_STATUS_NAFS_SHIFT)) & FCCU_N2AF_STATUS_NAFS_MASK) 502 /*! @} */ 503 504 /*! @name A2FF_STATUS - Alarm-to-Fault Freeze Status */ 505 /*! @{ */ 506 507 #define FCCU_A2FF_STATUS_AFFS_MASK (0xFFU) 508 #define FCCU_A2FF_STATUS_AFFS_SHIFT (0U) 509 #define FCCU_A2FF_STATUS_AFFS_WIDTH (8U) 510 #define FCCU_A2FF_STATUS_AFFS(x) (((uint32_t)(((uint32_t)(x)) << FCCU_A2FF_STATUS_AFFS_SHIFT)) & FCCU_A2FF_STATUS_AFFS_MASK) 511 512 #define FCCU_A2FF_STATUS_AF_SRC_MASK (0x300U) 513 #define FCCU_A2FF_STATUS_AF_SRC_SHIFT (8U) 514 #define FCCU_A2FF_STATUS_AF_SRC_WIDTH (2U) 515 #define FCCU_A2FF_STATUS_AF_SRC(x) (((uint32_t)(((uint32_t)(x)) << FCCU_A2FF_STATUS_AF_SRC_SHIFT)) & FCCU_A2FF_STATUS_AF_SRC_MASK) 516 /*! @} */ 517 518 /*! @name N2FF_STATUS - Normal-to-Fault Freeze Status */ 519 /*! @{ */ 520 521 #define FCCU_N2FF_STATUS_NFFS_MASK (0xFFU) 522 #define FCCU_N2FF_STATUS_NFFS_SHIFT (0U) 523 #define FCCU_N2FF_STATUS_NFFS_WIDTH (8U) 524 #define FCCU_N2FF_STATUS_NFFS(x) (((uint32_t)(((uint32_t)(x)) << FCCU_N2FF_STATUS_NFFS_SHIFT)) & FCCU_N2FF_STATUS_NFFS_MASK) 525 526 #define FCCU_N2FF_STATUS_NF_SRC_MASK (0x300U) 527 #define FCCU_N2FF_STATUS_NF_SRC_SHIFT (8U) 528 #define FCCU_N2FF_STATUS_NF_SRC_WIDTH (2U) 529 #define FCCU_N2FF_STATUS_NF_SRC(x) (((uint32_t)(((uint32_t)(x)) << FCCU_N2FF_STATUS_NF_SRC_SHIFT)) & FCCU_N2FF_STATUS_NF_SRC_MASK) 530 /*! @} */ 531 532 /*! @name F2AF_STATUS - Fault-to-Alarm Freeze Status */ 533 /*! @{ */ 534 535 #define FCCU_F2AF_STATUS_FAFS_MASK (0x1FFU) 536 #define FCCU_F2AF_STATUS_FAFS_SHIFT (0U) 537 #define FCCU_F2AF_STATUS_FAFS_WIDTH (9U) 538 #define FCCU_F2AF_STATUS_FAFS(x) (((uint32_t)(((uint32_t)(x)) << FCCU_F2AF_STATUS_FAFS_SHIFT)) & FCCU_F2AF_STATUS_FAFS_MASK) 539 /*! @} */ 540 541 /*! @name NCFF - Non-critical Fault Fake */ 542 /*! @{ */ 543 544 #define FCCU_NCFF_FNCFC_MASK (0x7FU) 545 #define FCCU_NCFF_FNCFC_SHIFT (0U) 546 #define FCCU_NCFF_FNCFC_WIDTH (7U) 547 #define FCCU_NCFF_FNCFC(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NCFF_FNCFC_SHIFT)) & FCCU_NCFF_FNCFC_MASK) 548 /*! @} */ 549 550 /*! @name IRQ_STAT - IRQ Status */ 551 /*! @{ */ 552 553 #define FCCU_IRQ_STAT_CFG_TO_STAT_MASK (0x1U) 554 #define FCCU_IRQ_STAT_CFG_TO_STAT_SHIFT (0U) 555 #define FCCU_IRQ_STAT_CFG_TO_STAT_WIDTH (1U) 556 #define FCCU_IRQ_STAT_CFG_TO_STAT(x) (((uint32_t)(((uint32_t)(x)) << FCCU_IRQ_STAT_CFG_TO_STAT_SHIFT)) & FCCU_IRQ_STAT_CFG_TO_STAT_MASK) 557 558 #define FCCU_IRQ_STAT_ALRM_STAT_MASK (0x2U) 559 #define FCCU_IRQ_STAT_ALRM_STAT_SHIFT (1U) 560 #define FCCU_IRQ_STAT_ALRM_STAT_WIDTH (1U) 561 #define FCCU_IRQ_STAT_ALRM_STAT(x) (((uint32_t)(((uint32_t)(x)) << FCCU_IRQ_STAT_ALRM_STAT_SHIFT)) & FCCU_IRQ_STAT_ALRM_STAT_MASK) 562 563 #define FCCU_IRQ_STAT_NMI_STAT_MASK (0x4U) 564 #define FCCU_IRQ_STAT_NMI_STAT_SHIFT (2U) 565 #define FCCU_IRQ_STAT_NMI_STAT_WIDTH (1U) 566 #define FCCU_IRQ_STAT_NMI_STAT(x) (((uint32_t)(((uint32_t)(x)) << FCCU_IRQ_STAT_NMI_STAT_SHIFT)) & FCCU_IRQ_STAT_NMI_STAT_MASK) 567 /*! @} */ 568 569 /*! @name IRQ_EN - IRQ Enable */ 570 /*! @{ */ 571 572 #define FCCU_IRQ_EN_CFG_TO_IEN_MASK (0x1U) 573 #define FCCU_IRQ_EN_CFG_TO_IEN_SHIFT (0U) 574 #define FCCU_IRQ_EN_CFG_TO_IEN_WIDTH (1U) 575 #define FCCU_IRQ_EN_CFG_TO_IEN(x) (((uint32_t)(((uint32_t)(x)) << FCCU_IRQ_EN_CFG_TO_IEN_SHIFT)) & FCCU_IRQ_EN_CFG_TO_IEN_MASK) 576 /*! @} */ 577 578 /*! @name TRANS_LOCK - Transient Configuration Lock */ 579 /*! @{ */ 580 581 #define FCCU_TRANS_LOCK_TRANSKEY_MASK (0x1FFU) 582 #define FCCU_TRANS_LOCK_TRANSKEY_SHIFT (0U) 583 #define FCCU_TRANS_LOCK_TRANSKEY_WIDTH (9U) 584 #define FCCU_TRANS_LOCK_TRANSKEY(x) (((uint32_t)(((uint32_t)(x)) << FCCU_TRANS_LOCK_TRANSKEY_SHIFT)) & FCCU_TRANS_LOCK_TRANSKEY_MASK) 585 /*! @} */ 586 587 /*! @name PERMNT_LOCK - Permanent Configuration Lock */ 588 /*! @{ */ 589 590 #define FCCU_PERMNT_LOCK_PERMNTKEY_MASK (0x1FFU) 591 #define FCCU_PERMNT_LOCK_PERMNTKEY_SHIFT (0U) 592 #define FCCU_PERMNT_LOCK_PERMNTKEY_WIDTH (9U) 593 #define FCCU_PERMNT_LOCK_PERMNTKEY(x) (((uint32_t)(((uint32_t)(x)) << FCCU_PERMNT_LOCK_PERMNTKEY_SHIFT)) & FCCU_PERMNT_LOCK_PERMNTKEY_MASK) 594 /*! @} */ 595 596 /*! @name DELTA_T - Delta T */ 597 /*! @{ */ 598 599 #define FCCU_DELTA_T_DELTA_T_MASK (0x3FFFU) 600 #define FCCU_DELTA_T_DELTA_T_SHIFT (0U) 601 #define FCCU_DELTA_T_DELTA_T_WIDTH (14U) 602 #define FCCU_DELTA_T_DELTA_T(x) (((uint32_t)(((uint32_t)(x)) << FCCU_DELTA_T_DELTA_T_SHIFT)) & FCCU_DELTA_T_DELTA_T_MASK) 603 /*! @} */ 604 605 /*! @name IRQ_ALARM_EN - Non-critical Alarm-State Interrupt-Request Enable */ 606 /*! @{ */ 607 608 #define FCCU_IRQ_ALARM_EN_IRQEN0_MASK (0x1U) 609 #define FCCU_IRQ_ALARM_EN_IRQEN0_SHIFT (0U) 610 #define FCCU_IRQ_ALARM_EN_IRQEN0_WIDTH (1U) 611 #define FCCU_IRQ_ALARM_EN_IRQEN0(x) (((uint32_t)(((uint32_t)(x)) << FCCU_IRQ_ALARM_EN_IRQEN0_SHIFT)) & FCCU_IRQ_ALARM_EN_IRQEN0_MASK) 612 613 #define FCCU_IRQ_ALARM_EN_IRQEN1_MASK (0x2U) 614 #define FCCU_IRQ_ALARM_EN_IRQEN1_SHIFT (1U) 615 #define FCCU_IRQ_ALARM_EN_IRQEN1_WIDTH (1U) 616 #define FCCU_IRQ_ALARM_EN_IRQEN1(x) (((uint32_t)(((uint32_t)(x)) << FCCU_IRQ_ALARM_EN_IRQEN1_SHIFT)) & FCCU_IRQ_ALARM_EN_IRQEN1_MASK) 617 618 #define FCCU_IRQ_ALARM_EN_IRQEN2_MASK (0x4U) 619 #define FCCU_IRQ_ALARM_EN_IRQEN2_SHIFT (2U) 620 #define FCCU_IRQ_ALARM_EN_IRQEN2_WIDTH (1U) 621 #define FCCU_IRQ_ALARM_EN_IRQEN2(x) (((uint32_t)(((uint32_t)(x)) << FCCU_IRQ_ALARM_EN_IRQEN2_SHIFT)) & FCCU_IRQ_ALARM_EN_IRQEN2_MASK) 622 623 #define FCCU_IRQ_ALARM_EN_IRQEN3_MASK (0x8U) 624 #define FCCU_IRQ_ALARM_EN_IRQEN3_SHIFT (3U) 625 #define FCCU_IRQ_ALARM_EN_IRQEN3_WIDTH (1U) 626 #define FCCU_IRQ_ALARM_EN_IRQEN3(x) (((uint32_t)(((uint32_t)(x)) << FCCU_IRQ_ALARM_EN_IRQEN3_SHIFT)) & FCCU_IRQ_ALARM_EN_IRQEN3_MASK) 627 628 #define FCCU_IRQ_ALARM_EN_IRQEN4_MASK (0x10U) 629 #define FCCU_IRQ_ALARM_EN_IRQEN4_SHIFT (4U) 630 #define FCCU_IRQ_ALARM_EN_IRQEN4_WIDTH (1U) 631 #define FCCU_IRQ_ALARM_EN_IRQEN4(x) (((uint32_t)(((uint32_t)(x)) << FCCU_IRQ_ALARM_EN_IRQEN4_SHIFT)) & FCCU_IRQ_ALARM_EN_IRQEN4_MASK) 632 633 #define FCCU_IRQ_ALARM_EN_IRQEN5_MASK (0x20U) 634 #define FCCU_IRQ_ALARM_EN_IRQEN5_SHIFT (5U) 635 #define FCCU_IRQ_ALARM_EN_IRQEN5_WIDTH (1U) 636 #define FCCU_IRQ_ALARM_EN_IRQEN5(x) (((uint32_t)(((uint32_t)(x)) << FCCU_IRQ_ALARM_EN_IRQEN5_SHIFT)) & FCCU_IRQ_ALARM_EN_IRQEN5_MASK) 637 638 #define FCCU_IRQ_ALARM_EN_IRQEN6_MASK (0x40U) 639 #define FCCU_IRQ_ALARM_EN_IRQEN6_SHIFT (6U) 640 #define FCCU_IRQ_ALARM_EN_IRQEN6_WIDTH (1U) 641 #define FCCU_IRQ_ALARM_EN_IRQEN6(x) (((uint32_t)(((uint32_t)(x)) << FCCU_IRQ_ALARM_EN_IRQEN6_SHIFT)) & FCCU_IRQ_ALARM_EN_IRQEN6_MASK) 642 643 #define FCCU_IRQ_ALARM_EN_IRQEN7_MASK (0x80U) 644 #define FCCU_IRQ_ALARM_EN_IRQEN7_SHIFT (7U) 645 #define FCCU_IRQ_ALARM_EN_IRQEN7_WIDTH (1U) 646 #define FCCU_IRQ_ALARM_EN_IRQEN7(x) (((uint32_t)(((uint32_t)(x)) << FCCU_IRQ_ALARM_EN_IRQEN7_SHIFT)) & FCCU_IRQ_ALARM_EN_IRQEN7_MASK) 647 /*! @} */ 648 649 /*! @name NMI_EN - Non-critical Fault-State Non-maskable-Interrupt-Request Enable */ 650 /*! @{ */ 651 652 #define FCCU_NMI_EN_NMIEN0_MASK (0x1U) 653 #define FCCU_NMI_EN_NMIEN0_SHIFT (0U) 654 #define FCCU_NMI_EN_NMIEN0_WIDTH (1U) 655 #define FCCU_NMI_EN_NMIEN0(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NMI_EN_NMIEN0_SHIFT)) & FCCU_NMI_EN_NMIEN0_MASK) 656 657 #define FCCU_NMI_EN_NMIEN1_MASK (0x2U) 658 #define FCCU_NMI_EN_NMIEN1_SHIFT (1U) 659 #define FCCU_NMI_EN_NMIEN1_WIDTH (1U) 660 #define FCCU_NMI_EN_NMIEN1(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NMI_EN_NMIEN1_SHIFT)) & FCCU_NMI_EN_NMIEN1_MASK) 661 662 #define FCCU_NMI_EN_NMIEN2_MASK (0x4U) 663 #define FCCU_NMI_EN_NMIEN2_SHIFT (2U) 664 #define FCCU_NMI_EN_NMIEN2_WIDTH (1U) 665 #define FCCU_NMI_EN_NMIEN2(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NMI_EN_NMIEN2_SHIFT)) & FCCU_NMI_EN_NMIEN2_MASK) 666 667 #define FCCU_NMI_EN_NMIEN3_MASK (0x8U) 668 #define FCCU_NMI_EN_NMIEN3_SHIFT (3U) 669 #define FCCU_NMI_EN_NMIEN3_WIDTH (1U) 670 #define FCCU_NMI_EN_NMIEN3(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NMI_EN_NMIEN3_SHIFT)) & FCCU_NMI_EN_NMIEN3_MASK) 671 672 #define FCCU_NMI_EN_NMIEN4_MASK (0x10U) 673 #define FCCU_NMI_EN_NMIEN4_SHIFT (4U) 674 #define FCCU_NMI_EN_NMIEN4_WIDTH (1U) 675 #define FCCU_NMI_EN_NMIEN4(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NMI_EN_NMIEN4_SHIFT)) & FCCU_NMI_EN_NMIEN4_MASK) 676 677 #define FCCU_NMI_EN_NMIEN5_MASK (0x20U) 678 #define FCCU_NMI_EN_NMIEN5_SHIFT (5U) 679 #define FCCU_NMI_EN_NMIEN5_WIDTH (1U) 680 #define FCCU_NMI_EN_NMIEN5(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NMI_EN_NMIEN5_SHIFT)) & FCCU_NMI_EN_NMIEN5_MASK) 681 682 #define FCCU_NMI_EN_NMIEN6_MASK (0x40U) 683 #define FCCU_NMI_EN_NMIEN6_SHIFT (6U) 684 #define FCCU_NMI_EN_NMIEN6_WIDTH (1U) 685 #define FCCU_NMI_EN_NMIEN6(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NMI_EN_NMIEN6_SHIFT)) & FCCU_NMI_EN_NMIEN6_MASK) 686 687 #define FCCU_NMI_EN_NMIEN7_MASK (0x80U) 688 #define FCCU_NMI_EN_NMIEN7_SHIFT (7U) 689 #define FCCU_NMI_EN_NMIEN7_WIDTH (1U) 690 #define FCCU_NMI_EN_NMIEN7(x) (((uint32_t)(((uint32_t)(x)) << FCCU_NMI_EN_NMIEN7_SHIFT)) & FCCU_NMI_EN_NMIEN7_MASK) 691 /*! @} */ 692 693 /*! @name EOUT_SIG_EN - Non-critical Fault-State EOUT Signaling Enable */ 694 /*! @{ */ 695 696 #define FCCU_EOUT_SIG_EN_EOUTEN0_MASK (0x1U) 697 #define FCCU_EOUT_SIG_EN_EOUTEN0_SHIFT (0U) 698 #define FCCU_EOUT_SIG_EN_EOUTEN0_WIDTH (1U) 699 #define FCCU_EOUT_SIG_EN_EOUTEN0(x) (((uint32_t)(((uint32_t)(x)) << FCCU_EOUT_SIG_EN_EOUTEN0_SHIFT)) & FCCU_EOUT_SIG_EN_EOUTEN0_MASK) 700 701 #define FCCU_EOUT_SIG_EN_EOUTEN1_MASK (0x2U) 702 #define FCCU_EOUT_SIG_EN_EOUTEN1_SHIFT (1U) 703 #define FCCU_EOUT_SIG_EN_EOUTEN1_WIDTH (1U) 704 #define FCCU_EOUT_SIG_EN_EOUTEN1(x) (((uint32_t)(((uint32_t)(x)) << FCCU_EOUT_SIG_EN_EOUTEN1_SHIFT)) & FCCU_EOUT_SIG_EN_EOUTEN1_MASK) 705 706 #define FCCU_EOUT_SIG_EN_EOUTEN2_MASK (0x4U) 707 #define FCCU_EOUT_SIG_EN_EOUTEN2_SHIFT (2U) 708 #define FCCU_EOUT_SIG_EN_EOUTEN2_WIDTH (1U) 709 #define FCCU_EOUT_SIG_EN_EOUTEN2(x) (((uint32_t)(((uint32_t)(x)) << FCCU_EOUT_SIG_EN_EOUTEN2_SHIFT)) & FCCU_EOUT_SIG_EN_EOUTEN2_MASK) 710 711 #define FCCU_EOUT_SIG_EN_EOUTEN3_MASK (0x8U) 712 #define FCCU_EOUT_SIG_EN_EOUTEN3_SHIFT (3U) 713 #define FCCU_EOUT_SIG_EN_EOUTEN3_WIDTH (1U) 714 #define FCCU_EOUT_SIG_EN_EOUTEN3(x) (((uint32_t)(((uint32_t)(x)) << FCCU_EOUT_SIG_EN_EOUTEN3_SHIFT)) & FCCU_EOUT_SIG_EN_EOUTEN3_MASK) 715 716 #define FCCU_EOUT_SIG_EN_EOUTEN4_MASK (0x10U) 717 #define FCCU_EOUT_SIG_EN_EOUTEN4_SHIFT (4U) 718 #define FCCU_EOUT_SIG_EN_EOUTEN4_WIDTH (1U) 719 #define FCCU_EOUT_SIG_EN_EOUTEN4(x) (((uint32_t)(((uint32_t)(x)) << FCCU_EOUT_SIG_EN_EOUTEN4_SHIFT)) & FCCU_EOUT_SIG_EN_EOUTEN4_MASK) 720 721 #define FCCU_EOUT_SIG_EN_EOUTEN5_MASK (0x20U) 722 #define FCCU_EOUT_SIG_EN_EOUTEN5_SHIFT (5U) 723 #define FCCU_EOUT_SIG_EN_EOUTEN5_WIDTH (1U) 724 #define FCCU_EOUT_SIG_EN_EOUTEN5(x) (((uint32_t)(((uint32_t)(x)) << FCCU_EOUT_SIG_EN_EOUTEN5_SHIFT)) & FCCU_EOUT_SIG_EN_EOUTEN5_MASK) 725 726 #define FCCU_EOUT_SIG_EN_EOUTEN6_MASK (0x40U) 727 #define FCCU_EOUT_SIG_EN_EOUTEN6_SHIFT (6U) 728 #define FCCU_EOUT_SIG_EN_EOUTEN6_WIDTH (1U) 729 #define FCCU_EOUT_SIG_EN_EOUTEN6(x) (((uint32_t)(((uint32_t)(x)) << FCCU_EOUT_SIG_EN_EOUTEN6_SHIFT)) & FCCU_EOUT_SIG_EN_EOUTEN6_MASK) 730 731 #define FCCU_EOUT_SIG_EN_EOUTEN7_MASK (0x80U) 732 #define FCCU_EOUT_SIG_EN_EOUTEN7_SHIFT (7U) 733 #define FCCU_EOUT_SIG_EN_EOUTEN7_WIDTH (1U) 734 #define FCCU_EOUT_SIG_EN_EOUTEN7(x) (((uint32_t)(((uint32_t)(x)) << FCCU_EOUT_SIG_EN_EOUTEN7_SHIFT)) & FCCU_EOUT_SIG_EN_EOUTEN7_MASK) 735 /*! @} */ 736 737 /*! @name TMR_ALARM - Alarm-State Timer */ 738 /*! @{ */ 739 740 #define FCCU_TMR_ALARM_COUNT_MASK (0xFFFFFFFFU) 741 #define FCCU_TMR_ALARM_COUNT_SHIFT (0U) 742 #define FCCU_TMR_ALARM_COUNT_WIDTH (32U) 743 #define FCCU_TMR_ALARM_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FCCU_TMR_ALARM_COUNT_SHIFT)) & FCCU_TMR_ALARM_COUNT_MASK) 744 /*! @} */ 745 746 /*! @name TMR_CFG - Configuration-State Timer */ 747 /*! @{ */ 748 749 #define FCCU_TMR_CFG_COUNT_MASK (0xFFFFFFFFU) 750 #define FCCU_TMR_CFG_COUNT_SHIFT (0U) 751 #define FCCU_TMR_CFG_COUNT_WIDTH (32U) 752 #define FCCU_TMR_CFG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FCCU_TMR_CFG_COUNT_SHIFT)) & FCCU_TMR_CFG_COUNT_MASK) 753 /*! @} */ 754 755 /*! @name TMR_ETMR - Fault-Output Timer */ 756 /*! @{ */ 757 758 #define FCCU_TMR_ETMR_COUNT_MASK (0xFFFFFFFFU) 759 #define FCCU_TMR_ETMR_COUNT_SHIFT (0U) 760 #define FCCU_TMR_ETMR_COUNT_WIDTH (32U) 761 #define FCCU_TMR_ETMR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FCCU_TMR_ETMR_COUNT_SHIFT)) & FCCU_TMR_ETMR_COUNT_MASK) 762 /*! @} */ 763 764 /*! 765 * @} 766 */ /* end of group FCCU_Register_Masks */ 767 768 /*! 769 * @} 770 */ /* end of group FCCU_Peripheral_Access_Layer */ 771 772 #endif /* #if !defined(S32K344_FCCU_H_) */ 773
