1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_EIM.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_EIM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_EIM_H_) /* Check if memory map has not been already included */ 58 #define S32K344_EIM_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- EIM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** EIM - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t EIMCR; /**< Error Injection Module Configuration Register, offset: 0x0 */ 74 __IO uint32_t EICHEN; /**< Error Injection Channel Enable register, offset: 0x4 */ 75 uint8_t RESERVED_0[248]; 76 __IO uint32_t EICHD0_WORD0; /**< Error Injection Channel Descriptor 0, Word0, offset: 0x100 */ 77 __IO uint32_t EICHD0_WORD1; /**< Error Injection Channel Descriptor 0, Word1, offset: 0x104 */ 78 __IO uint32_t EICHD0_WORD2; /**< Error Injection Channel Descriptor 0, Word2, offset: 0x108 */ 79 uint8_t RESERVED_1[52]; 80 __IO uint32_t EICHD1_WORD0; /**< Error Injection Channel Descriptor 1, Word0, offset: 0x140 */ 81 __IO uint32_t EICHD1_WORD1; /**< Error Injection Channel Descriptor 1, Word1, offset: 0x144 */ 82 __IO uint32_t EICHD1_WORD2; /**< Error Injection Channel Descriptor 1, Word2, offset: 0x148 */ 83 uint8_t RESERVED_2[52]; 84 __IO uint32_t EICHD2_WORD0; /**< Error Injection Channel Descriptor 2, Word0, offset: 0x180 */ 85 __IO uint32_t EICHD2_WORD1; /**< Error Injection Channel Descriptor 2, Word1, offset: 0x184 */ 86 __IO uint32_t EICHD2_WORD2; /**< Error Injection Channel Descriptor 2, Word2, offset: 0x188 */ 87 uint8_t RESERVED_3[52]; 88 __IO uint32_t EICHD3_WORD0; /**< Error Injection Channel Descriptor 3, Word0, offset: 0x1C0 */ 89 __IO uint32_t EICHD3_WORD1; /**< Error Injection Channel Descriptor 3, Word1, offset: 0x1C4 */ 90 __IO uint32_t EICHD3_WORD2; /**< Error Injection Channel Descriptor 3, Word2, offset: 0x1C8 */ 91 uint8_t RESERVED_4[52]; 92 __IO uint32_t EICHD4_WORD0; /**< Error Injection Channel Descriptor 4, Word0, offset: 0x200 */ 93 __IO uint32_t EICHD4_WORD1; /**< Error Injection Channel Descriptor 4, Word1, offset: 0x204 */ 94 __IO uint32_t EICHD4_WORD2; /**< Error Injection Channel Descriptor 4, Word2, offset: 0x208 */ 95 __IO uint32_t EICHD4_WORD3; /**< Error Injection Channel Descriptor 4, Word3, offset: 0x20C */ 96 __IO uint32_t EICHD4_WORD4; /**< Error Injection Channel Descriptor 4, Word4, offset: 0x210 */ 97 uint8_t RESERVED_5[44]; 98 __IO uint32_t EICHD5_WORD0; /**< Error Injection Channel Descriptor 5, Word0, offset: 0x240 */ 99 __IO uint32_t EICHD5_WORD1; /**< Error Injection Channel Descriptor 5, Word1, offset: 0x244 */ 100 __IO uint32_t EICHD5_WORD2; /**< Error Injection Channel Descriptor 5, Word2, offset: 0x248 */ 101 __IO uint32_t EICHD5_WORD3; /**< Error Injection Channel Descriptor 5, Word3, offset: 0x24C */ 102 __IO uint32_t EICHD5_WORD4; /**< Error Injection Channel Descriptor 5, Word4, offset: 0x250 */ 103 uint8_t RESERVED_6[44]; 104 __IO uint32_t EICHD6_WORD0; /**< Error Injection Channel Descriptor 6, Word0, offset: 0x280 */ 105 __IO uint32_t EICHD6_WORD1; /**< Error Injection Channel Descriptor 6, Word1, offset: 0x284 */ 106 __IO uint32_t EICHD6_WORD2; /**< Error Injection Channel Descriptor 6, Word2, offset: 0x288 */ 107 __IO uint32_t EICHD6_WORD3; /**< Error Injection Channel Descriptor 6, Word3, offset: 0x28C */ 108 __IO uint32_t EICHD6_WORD4; /**< Error Injection Channel Descriptor 6, Word4, offset: 0x290 */ 109 uint8_t RESERVED_7[44]; 110 __IO uint32_t EICHD7_WORD0; /**< Error Injection Channel Descriptor 7, Word0, offset: 0x2C0 */ 111 __IO uint32_t EICHD7_WORD1; /**< Error Injection Channel Descriptor 7, Word1, offset: 0x2C4 */ 112 __IO uint32_t EICHD7_WORD2; /**< Error Injection Channel Descriptor 7, Word2, offset: 0x2C8 */ 113 __IO uint32_t EICHD7_WORD3; /**< Error Injection Channel Descriptor 7, Word3, offset: 0x2CC */ 114 __IO uint32_t EICHD7_WORD4; /**< Error Injection Channel Descriptor 7, Word4, offset: 0x2D0 */ 115 uint8_t RESERVED_8[44]; 116 __IO uint32_t EICHD8_WORD0; /**< Error Injection Channel Descriptor 8, Word0, offset: 0x300 */ 117 __IO uint32_t EICHD8_WORD1; /**< Error Injection Channel Descriptor 8, Word1, offset: 0x304 */ 118 __IO uint32_t EICHD8_WORD2; /**< Error Injection Channel Descriptor 8, Word2, offset: 0x308 */ 119 uint8_t RESERVED_9[52]; 120 __IO uint32_t EICHD9_WORD0; /**< Error Injection Channel Descriptor 9, Word0, offset: 0x340 */ 121 __IO uint32_t EICHD9_WORD1; /**< Error Injection Channel Descriptor 9, Word1, offset: 0x344 */ 122 __IO uint32_t EICHD9_WORD2; /**< Error Injection Channel Descriptor 9, Word2, offset: 0x348 */ 123 __IO uint32_t EICHD9_WORD3; /**< Error Injection Channel Descriptor 9, Word3, offset: 0x34C */ 124 __IO uint32_t EICHD9_WORD4; /**< Error Injection Channel Descriptor 9, Word4, offset: 0x350 */ 125 uint8_t RESERVED_10[44]; 126 __IO uint32_t EICHD10_WORD0; /**< Error Injection Channel Descriptor 10, Word0, offset: 0x380 */ 127 __IO uint32_t EICHD10_WORD1; /**< Error Injection Channel Descriptor 10, Word1, offset: 0x384 */ 128 __IO uint32_t EICHD10_WORD2; /**< Error Injection Channel Descriptor 10, Word2, offset: 0x388 */ 129 __IO uint32_t EICHD10_WORD3; /**< Error Injection Channel Descriptor 10, Word3, offset: 0x38C */ 130 __IO uint32_t EICHD10_WORD4; /**< Error Injection Channel Descriptor 10, Word4, offset: 0x390 */ 131 uint8_t RESERVED_11[44]; 132 __IO uint32_t EICHD11_WORD0; /**< Error Injection Channel Descriptor 11, Word0, offset: 0x3C0 */ 133 __IO uint32_t EICHD11_WORD1; /**< Error Injection Channel Descriptor 11, Word1, offset: 0x3C4 */ 134 __IO uint32_t EICHD11_WORD2; /**< Error Injection Channel Descriptor 11, Word2, offset: 0x3C8 */ 135 __IO uint32_t EICHD11_WORD3; /**< Error Injection Channel Descriptor 11, Word3, offset: 0x3CC */ 136 __IO uint32_t EICHD11_WORD4; /**< Error Injection Channel Descriptor 11, Word4, offset: 0x3D0 */ 137 uint8_t RESERVED_12[44]; 138 __IO uint32_t EICHD12_WORD0; /**< Error Injection Channel Descriptor 12, Word0, offset: 0x400 */ 139 __IO uint32_t EICHD12_WORD1; /**< Error Injection Channel Descriptor 12, Word1, offset: 0x404 */ 140 __IO uint32_t EICHD12_WORD2; /**< Error Injection Channel Descriptor 12, Word2, offset: 0x408 */ 141 __IO uint32_t EICHD12_WORD3; /**< Error Injection Channel Descriptor 12, Word3, offset: 0x40C */ 142 __IO uint32_t EICHD12_WORD4; /**< Error Injection Channel Descriptor 12, Word4, offset: 0x410 */ 143 uint8_t RESERVED_13[44]; 144 __IO uint32_t EICHD13_WORD0; /**< Error Injection Channel Descriptor 13, Word0, offset: 0x440 */ 145 __IO uint32_t EICHD13_WORD1; /**< Error Injection Channel Descriptor 13, Word1, offset: 0x444 */ 146 __IO uint32_t EICHD13_WORD2; /**< Error Injection Channel Descriptor 13, Word2, offset: 0x448 */ 147 uint8_t RESERVED_14[52]; 148 __IO uint32_t EICHD14_WORD0; /**< Error Injection Channel Descriptor 14, Word0, offset: 0x480 */ 149 __IO uint32_t EICHD14_WORD1; /**< Error Injection Channel Descriptor 14, Word1, offset: 0x484 */ 150 uint8_t RESERVED_15[56]; 151 __IO uint32_t EICHD15_WORD0; /**< Error Injection Channel Descriptor 15, Word0, offset: 0x4C0 */ 152 __IO uint32_t EICHD15_WORD1; /**< Error Injection Channel Descriptor 15, Word1, offset: 0x4C4 */ 153 uint8_t RESERVED_16[56]; 154 __IO uint32_t EICHD16_WORD0; /**< Error Injection Channel Descriptor 16, Word0, offset: 0x500 */ 155 __IO uint32_t EICHD16_WORD1; /**< Error Injection Channel Descriptor 16, Word1, offset: 0x504 */ 156 __IO uint32_t EICHD16_WORD2; /**< Error Injection Channel Descriptor 16, Word2, offset: 0x508 */ 157 uint8_t RESERVED_17[52]; 158 __IO uint32_t EICHD17_WORD0; /**< Error Injection Channel Descriptor 17, Word0, offset: 0x540 */ 159 __IO uint32_t EICHD17_WORD1; /**< Error Injection Channel Descriptor 17, Word1, offset: 0x544 */ 160 uint8_t RESERVED_18[56]; 161 __IO uint32_t EICHD18_WORD0; /**< Error Injection Channel Descriptor 18, Word0, offset: 0x580 */ 162 __IO uint32_t EICHD18_WORD1; /**< Error Injection Channel Descriptor 18, Word1, offset: 0x584 */ 163 uint8_t RESERVED_19[60]; 164 __IO uint32_t EICHD19_WORD1; /**< Error Injection Channel Descriptor 19, Word1, offset: 0x5C4 */ 165 __IO uint32_t EICHD19_WORD2; /**< Error Injection Channel Descriptor 19, Word2, offset: 0x5C8 */ 166 __IO uint32_t EICHD19_WORD3; /**< Error Injection Channel Descriptor 19, Word3, offset: 0x5CC */ 167 __IO uint32_t EICHD19_WORD4; /**< Error Injection Channel Descriptor 19, Word4, offset: 0x5D0 */ 168 __IO uint32_t EICHD19_WORD5; /**< Error Injection Channel Descriptor 19, Word5, offset: 0x5D4 */ 169 __IO uint32_t EICHD19_WORD6; /**< Error Injection Channel Descriptor 19, Word6, offset: 0x5D8 */ 170 uint8_t RESERVED_20[40]; 171 __IO uint32_t EICHD20_WORD1; /**< Error Injection Channel Descriptor 20, Word1, offset: 0x604 */ 172 __IO uint32_t EICHD20_WORD2; /**< Error Injection Channel Descriptor 20, Word2, offset: 0x608 */ 173 __IO uint32_t EICHD20_WORD3; /**< Error Injection Channel Descriptor 20, Word3, offset: 0x60C */ 174 __IO uint32_t EICHD20_WORD4; /**< Error Injection Channel Descriptor 20, Word4, offset: 0x610 */ 175 __IO uint32_t EICHD20_WORD5; /**< Error Injection Channel Descriptor 20, Word5, offset: 0x614 */ 176 __IO uint32_t EICHD20_WORD6; /**< Error Injection Channel Descriptor 20, Word6, offset: 0x618 */ 177 uint8_t RESERVED_21[40]; 178 __IO uint32_t EICHD21_WORD1; /**< Error Injection Channel Descriptor 21, Word1, offset: 0x644 */ 179 __IO uint32_t EICHD21_WORD2; /**< Error Injection Channel Descriptor 21, Word2, offset: 0x648 */ 180 uint8_t RESERVED_22[56]; 181 __IO uint32_t EICHD22_WORD1; /**< Error Injection Channel Descriptor 22, Word1, offset: 0x684 */ 182 __IO uint32_t EICHD22_WORD2; /**< Error Injection Channel Descriptor 22, Word2, offset: 0x688 */ 183 uint8_t RESERVED_23[56]; 184 __IO uint32_t EICHD23_WORD1; /**< Error Injection Channel Descriptor 23, Word1, offset: 0x6C4 */ 185 __IO uint32_t EICHD23_WORD2; /**< Error Injection Channel Descriptor 23, Word2, offset: 0x6C8 */ 186 uint8_t RESERVED_24[56]; 187 __IO uint32_t EICHD24_WORD1; /**< Error Injection Channel Descriptor 24, Word1, offset: 0x704 */ 188 __IO uint32_t EICHD24_WORD2; /**< Error Injection Channel Descriptor 24, Word2, offset: 0x708 */ 189 uint8_t RESERVED_25[56]; 190 __IO uint32_t EICHD25_WORD1; /**< Error Injection Channel Descriptor 25, Word1, offset: 0x744 */ 191 __IO uint32_t EICHD25_WORD2; /**< Error Injection Channel Descriptor 25, Word2, offset: 0x748 */ 192 uint8_t RESERVED_26[56]; 193 __IO uint32_t EICHD26_WORD1; /**< Error Injection Channel Descriptor 26, Word1, offset: 0x784 */ 194 __IO uint32_t EICHD26_WORD2; /**< Error Injection Channel Descriptor 26, Word2, offset: 0x788 */ 195 uint8_t RESERVED_27[56]; 196 __IO uint32_t EICHD27_WORD1; /**< Error Injection Channel Descriptor 27, Word1, offset: 0x7C4 */ 197 uint8_t RESERVED_28[60]; 198 __IO uint32_t EICHD28_WORD1; /**< Error Injection Channel Descriptor 28, Word1, offset: 0x804 */ 199 uint8_t RESERVED_29[60]; 200 __IO uint32_t EICHD29_WORD1; /**< Error Injection Channel Descriptor 29, Word1, offset: 0x844 */ 201 uint8_t RESERVED_30[60]; 202 __IO uint32_t EICHD30_WORD1; /**< Error Injection Channel Descriptor 30, Word1, offset: 0x884 */ 203 } EIM_Type, *EIM_MemMapPtr; 204 205 /** Number of instances of the EIM module. */ 206 #define EIM_INSTANCE_COUNT (1u) 207 208 /* EIM - Peripheral instance base addresses */ 209 /** Peripheral EIM base address */ 210 #define IP_EIM_BASE (0x40258000u) 211 /** Peripheral EIM base pointer */ 212 #define IP_EIM ((EIM_Type *)IP_EIM_BASE) 213 /** Array initializer of EIM peripheral base addresses */ 214 #define IP_EIM_BASE_ADDRS { IP_EIM_BASE } 215 /** Array initializer of EIM peripheral base pointers */ 216 #define IP_EIM_BASE_PTRS { IP_EIM } 217 218 /* ---------------------------------------------------------------------------- 219 -- EIM Register Masks 220 ---------------------------------------------------------------------------- */ 221 222 /*! 223 * @addtogroup EIM_Register_Masks EIM Register Masks 224 * @{ 225 */ 226 227 /*! @name EIMCR - Error Injection Module Configuration Register */ 228 /*! @{ */ 229 230 #define EIM_EIMCR_GEIEN_MASK (0x1U) 231 #define EIM_EIMCR_GEIEN_SHIFT (0U) 232 #define EIM_EIMCR_GEIEN_WIDTH (1U) 233 #define EIM_EIMCR_GEIEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EIMCR_GEIEN_SHIFT)) & EIM_EIMCR_GEIEN_MASK) 234 /*! @} */ 235 236 /*! @name EICHEN - Error Injection Channel Enable register */ 237 /*! @{ */ 238 239 #define EIM_EICHEN_EICH30EN_MASK (0x2U) 240 #define EIM_EICHEN_EICH30EN_SHIFT (1U) 241 #define EIM_EICHEN_EICH30EN_WIDTH (1U) 242 #define EIM_EICHEN_EICH30EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH30EN_SHIFT)) & EIM_EICHEN_EICH30EN_MASK) 243 244 #define EIM_EICHEN_EICH29EN_MASK (0x4U) 245 #define EIM_EICHEN_EICH29EN_SHIFT (2U) 246 #define EIM_EICHEN_EICH29EN_WIDTH (1U) 247 #define EIM_EICHEN_EICH29EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH29EN_SHIFT)) & EIM_EICHEN_EICH29EN_MASK) 248 249 #define EIM_EICHEN_EICH28EN_MASK (0x8U) 250 #define EIM_EICHEN_EICH28EN_SHIFT (3U) 251 #define EIM_EICHEN_EICH28EN_WIDTH (1U) 252 #define EIM_EICHEN_EICH28EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH28EN_SHIFT)) & EIM_EICHEN_EICH28EN_MASK) 253 254 #define EIM_EICHEN_EICH27EN_MASK (0x10U) 255 #define EIM_EICHEN_EICH27EN_SHIFT (4U) 256 #define EIM_EICHEN_EICH27EN_WIDTH (1U) 257 #define EIM_EICHEN_EICH27EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH27EN_SHIFT)) & EIM_EICHEN_EICH27EN_MASK) 258 259 #define EIM_EICHEN_EICH26EN_MASK (0x20U) 260 #define EIM_EICHEN_EICH26EN_SHIFT (5U) 261 #define EIM_EICHEN_EICH26EN_WIDTH (1U) 262 #define EIM_EICHEN_EICH26EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH26EN_SHIFT)) & EIM_EICHEN_EICH26EN_MASK) 263 264 #define EIM_EICHEN_EICH25EN_MASK (0x40U) 265 #define EIM_EICHEN_EICH25EN_SHIFT (6U) 266 #define EIM_EICHEN_EICH25EN_WIDTH (1U) 267 #define EIM_EICHEN_EICH25EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH25EN_SHIFT)) & EIM_EICHEN_EICH25EN_MASK) 268 269 #define EIM_EICHEN_EICH24EN_MASK (0x80U) 270 #define EIM_EICHEN_EICH24EN_SHIFT (7U) 271 #define EIM_EICHEN_EICH24EN_WIDTH (1U) 272 #define EIM_EICHEN_EICH24EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH24EN_SHIFT)) & EIM_EICHEN_EICH24EN_MASK) 273 274 #define EIM_EICHEN_EICH23EN_MASK (0x100U) 275 #define EIM_EICHEN_EICH23EN_SHIFT (8U) 276 #define EIM_EICHEN_EICH23EN_WIDTH (1U) 277 #define EIM_EICHEN_EICH23EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH23EN_SHIFT)) & EIM_EICHEN_EICH23EN_MASK) 278 279 #define EIM_EICHEN_EICH22EN_MASK (0x200U) 280 #define EIM_EICHEN_EICH22EN_SHIFT (9U) 281 #define EIM_EICHEN_EICH22EN_WIDTH (1U) 282 #define EIM_EICHEN_EICH22EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH22EN_SHIFT)) & EIM_EICHEN_EICH22EN_MASK) 283 284 #define EIM_EICHEN_EICH21EN_MASK (0x400U) 285 #define EIM_EICHEN_EICH21EN_SHIFT (10U) 286 #define EIM_EICHEN_EICH21EN_WIDTH (1U) 287 #define EIM_EICHEN_EICH21EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH21EN_SHIFT)) & EIM_EICHEN_EICH21EN_MASK) 288 289 #define EIM_EICHEN_EICH20EN_MASK (0x800U) 290 #define EIM_EICHEN_EICH20EN_SHIFT (11U) 291 #define EIM_EICHEN_EICH20EN_WIDTH (1U) 292 #define EIM_EICHEN_EICH20EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH20EN_SHIFT)) & EIM_EICHEN_EICH20EN_MASK) 293 294 #define EIM_EICHEN_EICH19EN_MASK (0x1000U) 295 #define EIM_EICHEN_EICH19EN_SHIFT (12U) 296 #define EIM_EICHEN_EICH19EN_WIDTH (1U) 297 #define EIM_EICHEN_EICH19EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH19EN_SHIFT)) & EIM_EICHEN_EICH19EN_MASK) 298 299 #define EIM_EICHEN_EICH18EN_MASK (0x2000U) 300 #define EIM_EICHEN_EICH18EN_SHIFT (13U) 301 #define EIM_EICHEN_EICH18EN_WIDTH (1U) 302 #define EIM_EICHEN_EICH18EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH18EN_SHIFT)) & EIM_EICHEN_EICH18EN_MASK) 303 304 #define EIM_EICHEN_EICH17EN_MASK (0x4000U) 305 #define EIM_EICHEN_EICH17EN_SHIFT (14U) 306 #define EIM_EICHEN_EICH17EN_WIDTH (1U) 307 #define EIM_EICHEN_EICH17EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH17EN_SHIFT)) & EIM_EICHEN_EICH17EN_MASK) 308 309 #define EIM_EICHEN_EICH16EN_MASK (0x8000U) 310 #define EIM_EICHEN_EICH16EN_SHIFT (15U) 311 #define EIM_EICHEN_EICH16EN_WIDTH (1U) 312 #define EIM_EICHEN_EICH16EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH16EN_SHIFT)) & EIM_EICHEN_EICH16EN_MASK) 313 314 #define EIM_EICHEN_EICH15EN_MASK (0x10000U) 315 #define EIM_EICHEN_EICH15EN_SHIFT (16U) 316 #define EIM_EICHEN_EICH15EN_WIDTH (1U) 317 #define EIM_EICHEN_EICH15EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH15EN_SHIFT)) & EIM_EICHEN_EICH15EN_MASK) 318 319 #define EIM_EICHEN_EICH14EN_MASK (0x20000U) 320 #define EIM_EICHEN_EICH14EN_SHIFT (17U) 321 #define EIM_EICHEN_EICH14EN_WIDTH (1U) 322 #define EIM_EICHEN_EICH14EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH14EN_SHIFT)) & EIM_EICHEN_EICH14EN_MASK) 323 324 #define EIM_EICHEN_EICH13EN_MASK (0x40000U) 325 #define EIM_EICHEN_EICH13EN_SHIFT (18U) 326 #define EIM_EICHEN_EICH13EN_WIDTH (1U) 327 #define EIM_EICHEN_EICH13EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH13EN_SHIFT)) & EIM_EICHEN_EICH13EN_MASK) 328 329 #define EIM_EICHEN_EICH12EN_MASK (0x80000U) 330 #define EIM_EICHEN_EICH12EN_SHIFT (19U) 331 #define EIM_EICHEN_EICH12EN_WIDTH (1U) 332 #define EIM_EICHEN_EICH12EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH12EN_SHIFT)) & EIM_EICHEN_EICH12EN_MASK) 333 334 #define EIM_EICHEN_EICH11EN_MASK (0x100000U) 335 #define EIM_EICHEN_EICH11EN_SHIFT (20U) 336 #define EIM_EICHEN_EICH11EN_WIDTH (1U) 337 #define EIM_EICHEN_EICH11EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH11EN_SHIFT)) & EIM_EICHEN_EICH11EN_MASK) 338 339 #define EIM_EICHEN_EICH10EN_MASK (0x200000U) 340 #define EIM_EICHEN_EICH10EN_SHIFT (21U) 341 #define EIM_EICHEN_EICH10EN_WIDTH (1U) 342 #define EIM_EICHEN_EICH10EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH10EN_SHIFT)) & EIM_EICHEN_EICH10EN_MASK) 343 344 #define EIM_EICHEN_EICH9EN_MASK (0x400000U) 345 #define EIM_EICHEN_EICH9EN_SHIFT (22U) 346 #define EIM_EICHEN_EICH9EN_WIDTH (1U) 347 #define EIM_EICHEN_EICH9EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH9EN_SHIFT)) & EIM_EICHEN_EICH9EN_MASK) 348 349 #define EIM_EICHEN_EICH8EN_MASK (0x800000U) 350 #define EIM_EICHEN_EICH8EN_SHIFT (23U) 351 #define EIM_EICHEN_EICH8EN_WIDTH (1U) 352 #define EIM_EICHEN_EICH8EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH8EN_SHIFT)) & EIM_EICHEN_EICH8EN_MASK) 353 354 #define EIM_EICHEN_EICH7EN_MASK (0x1000000U) 355 #define EIM_EICHEN_EICH7EN_SHIFT (24U) 356 #define EIM_EICHEN_EICH7EN_WIDTH (1U) 357 #define EIM_EICHEN_EICH7EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH7EN_SHIFT)) & EIM_EICHEN_EICH7EN_MASK) 358 359 #define EIM_EICHEN_EICH6EN_MASK (0x2000000U) 360 #define EIM_EICHEN_EICH6EN_SHIFT (25U) 361 #define EIM_EICHEN_EICH6EN_WIDTH (1U) 362 #define EIM_EICHEN_EICH6EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH6EN_SHIFT)) & EIM_EICHEN_EICH6EN_MASK) 363 364 #define EIM_EICHEN_EICH5EN_MASK (0x4000000U) 365 #define EIM_EICHEN_EICH5EN_SHIFT (26U) 366 #define EIM_EICHEN_EICH5EN_WIDTH (1U) 367 #define EIM_EICHEN_EICH5EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH5EN_SHIFT)) & EIM_EICHEN_EICH5EN_MASK) 368 369 #define EIM_EICHEN_EICH4EN_MASK (0x8000000U) 370 #define EIM_EICHEN_EICH4EN_SHIFT (27U) 371 #define EIM_EICHEN_EICH4EN_WIDTH (1U) 372 #define EIM_EICHEN_EICH4EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH4EN_SHIFT)) & EIM_EICHEN_EICH4EN_MASK) 373 374 #define EIM_EICHEN_EICH3EN_MASK (0x10000000U) 375 #define EIM_EICHEN_EICH3EN_SHIFT (28U) 376 #define EIM_EICHEN_EICH3EN_WIDTH (1U) 377 #define EIM_EICHEN_EICH3EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH3EN_SHIFT)) & EIM_EICHEN_EICH3EN_MASK) 378 379 #define EIM_EICHEN_EICH2EN_MASK (0x20000000U) 380 #define EIM_EICHEN_EICH2EN_SHIFT (29U) 381 #define EIM_EICHEN_EICH2EN_WIDTH (1U) 382 #define EIM_EICHEN_EICH2EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH2EN_SHIFT)) & EIM_EICHEN_EICH2EN_MASK) 383 384 #define EIM_EICHEN_EICH1EN_MASK (0x40000000U) 385 #define EIM_EICHEN_EICH1EN_SHIFT (30U) 386 #define EIM_EICHEN_EICH1EN_WIDTH (1U) 387 #define EIM_EICHEN_EICH1EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH1EN_SHIFT)) & EIM_EICHEN_EICH1EN_MASK) 388 389 #define EIM_EICHEN_EICH0EN_MASK (0x80000000U) 390 #define EIM_EICHEN_EICH0EN_SHIFT (31U) 391 #define EIM_EICHEN_EICH0EN_WIDTH (1U) 392 #define EIM_EICHEN_EICH0EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH0EN_SHIFT)) & EIM_EICHEN_EICH0EN_MASK) 393 /*! @} */ 394 395 /*! @name EICHD0_WORD0 - Error Injection Channel Descriptor 0, Word0 */ 396 /*! @{ */ 397 398 #define EIM_EICHD0_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 399 #define EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT (24U) 400 #define EIM_EICHD0_WORD0_CHKBIT_MASK_WIDTH (8U) 401 #define EIM_EICHD0_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) 402 /*! @} */ 403 404 /*! @name EICHD0_WORD1 - Error Injection Channel Descriptor 0, Word1 */ 405 /*! @{ */ 406 407 #define EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 408 #define EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT (0U) 409 #define EIM_EICHD0_WORD1_B0_3DATA_MASK_WIDTH (32U) 410 #define EIM_EICHD0_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) 411 /*! @} */ 412 413 /*! @name EICHD0_WORD2 - Error Injection Channel Descriptor 0, Word2 */ 414 /*! @{ */ 415 416 #define EIM_EICHD0_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 417 #define EIM_EICHD0_WORD2_B4_7DATA_MASK_SHIFT (0U) 418 #define EIM_EICHD0_WORD2_B4_7DATA_MASK_WIDTH (32U) 419 #define EIM_EICHD0_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD0_WORD2_B4_7DATA_MASK_MASK) 420 /*! @} */ 421 422 /*! @name EICHD1_WORD0 - Error Injection Channel Descriptor 1, Word0 */ 423 /*! @{ */ 424 425 #define EIM_EICHD1_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 426 #define EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT (24U) 427 #define EIM_EICHD1_WORD0_CHKBIT_MASK_WIDTH (8U) 428 #define EIM_EICHD1_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD1_WORD0_CHKBIT_MASK_MASK) 429 /*! @} */ 430 431 /*! @name EICHD1_WORD1 - Error Injection Channel Descriptor 1, Word1 */ 432 /*! @{ */ 433 434 #define EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 435 #define EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT (0U) 436 #define EIM_EICHD1_WORD1_B0_3DATA_MASK_WIDTH (32U) 437 #define EIM_EICHD1_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK) 438 /*! @} */ 439 440 /*! @name EICHD1_WORD2 - Error Injection Channel Descriptor 1, Word2 */ 441 /*! @{ */ 442 443 #define EIM_EICHD1_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 444 #define EIM_EICHD1_WORD2_B4_7DATA_MASK_SHIFT (0U) 445 #define EIM_EICHD1_WORD2_B4_7DATA_MASK_WIDTH (32U) 446 #define EIM_EICHD1_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD1_WORD2_B4_7DATA_MASK_MASK) 447 /*! @} */ 448 449 /*! @name EICHD2_WORD0 - Error Injection Channel Descriptor 2, Word0 */ 450 /*! @{ */ 451 452 #define EIM_EICHD2_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 453 #define EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT (24U) 454 #define EIM_EICHD2_WORD0_CHKBIT_MASK_WIDTH (8U) 455 #define EIM_EICHD2_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD2_WORD0_CHKBIT_MASK_MASK) 456 /*! @} */ 457 458 /*! @name EICHD2_WORD1 - Error Injection Channel Descriptor 2, Word1 */ 459 /*! @{ */ 460 461 #define EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 462 #define EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT (0U) 463 #define EIM_EICHD2_WORD1_B0_3DATA_MASK_WIDTH (32U) 464 #define EIM_EICHD2_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK) 465 /*! @} */ 466 467 /*! @name EICHD2_WORD2 - Error Injection Channel Descriptor 2, Word2 */ 468 /*! @{ */ 469 470 #define EIM_EICHD2_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 471 #define EIM_EICHD2_WORD2_B4_7DATA_MASK_SHIFT (0U) 472 #define EIM_EICHD2_WORD2_B4_7DATA_MASK_WIDTH (32U) 473 #define EIM_EICHD2_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD2_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD2_WORD2_B4_7DATA_MASK_MASK) 474 /*! @} */ 475 476 /*! @name EICHD3_WORD0 - Error Injection Channel Descriptor 3, Word0 */ 477 /*! @{ */ 478 479 #define EIM_EICHD3_WORD0_CHKBIT_MASK_MASK (0xFFFC0000U) 480 #define EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT (18U) 481 #define EIM_EICHD3_WORD0_CHKBIT_MASK_WIDTH (14U) 482 #define EIM_EICHD3_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD3_WORD0_CHKBIT_MASK_MASK) 483 /*! @} */ 484 485 /*! @name EICHD3_WORD1 - Error Injection Channel Descriptor 3, Word1 */ 486 /*! @{ */ 487 488 #define EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK (0xFFFU) 489 #define EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT (0U) 490 #define EIM_EICHD3_WORD1_B0_3DATA_MASK_WIDTH (12U) 491 #define EIM_EICHD3_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK) 492 /*! @} */ 493 494 /*! @name EICHD3_WORD2 - Error Injection Channel Descriptor 3, Word2 */ 495 /*! @{ */ 496 497 #define EIM_EICHD3_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 498 #define EIM_EICHD3_WORD2_B4_7DATA_MASK_SHIFT (0U) 499 #define EIM_EICHD3_WORD2_B4_7DATA_MASK_WIDTH (32U) 500 #define EIM_EICHD3_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD3_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD3_WORD2_B4_7DATA_MASK_MASK) 501 /*! @} */ 502 503 /*! @name EICHD4_WORD0 - Error Injection Channel Descriptor 4, Word0 */ 504 /*! @{ */ 505 506 #define EIM_EICHD4_WORD0_CHKBIT_MASK_MASK (0xFFFF0000U) 507 #define EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT (16U) 508 #define EIM_EICHD4_WORD0_CHKBIT_MASK_WIDTH (16U) 509 #define EIM_EICHD4_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD4_WORD0_CHKBIT_MASK_MASK) 510 /*! @} */ 511 512 /*! @name EICHD4_WORD1 - Error Injection Channel Descriptor 4, Word1 */ 513 /*! @{ */ 514 515 #define EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 516 #define EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT (0U) 517 #define EIM_EICHD4_WORD1_B0_3DATA_MASK_WIDTH (32U) 518 #define EIM_EICHD4_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK) 519 /*! @} */ 520 521 /*! @name EICHD4_WORD2 - Error Injection Channel Descriptor 4, Word2 */ 522 /*! @{ */ 523 524 #define EIM_EICHD4_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 525 #define EIM_EICHD4_WORD2_B4_7DATA_MASK_SHIFT (0U) 526 #define EIM_EICHD4_WORD2_B4_7DATA_MASK_WIDTH (32U) 527 #define EIM_EICHD4_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD4_WORD2_B4_7DATA_MASK_MASK) 528 /*! @} */ 529 530 /*! @name EICHD4_WORD3 - Error Injection Channel Descriptor 4, Word3 */ 531 /*! @{ */ 532 533 #define EIM_EICHD4_WORD3_B8_11DATA_MASK_MASK (0xFFFFFFFFU) 534 #define EIM_EICHD4_WORD3_B8_11DATA_MASK_SHIFT (0U) 535 #define EIM_EICHD4_WORD3_B8_11DATA_MASK_WIDTH (32U) 536 #define EIM_EICHD4_WORD3_B8_11DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD3_B8_11DATA_MASK_SHIFT)) & EIM_EICHD4_WORD3_B8_11DATA_MASK_MASK) 537 /*! @} */ 538 539 /*! @name EICHD4_WORD4 - Error Injection Channel Descriptor 4, Word4 */ 540 /*! @{ */ 541 542 #define EIM_EICHD4_WORD4_B12_15DATA_MASK_MASK (0xFFFFFFFFU) 543 #define EIM_EICHD4_WORD4_B12_15DATA_MASK_SHIFT (0U) 544 #define EIM_EICHD4_WORD4_B12_15DATA_MASK_WIDTH (32U) 545 #define EIM_EICHD4_WORD4_B12_15DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD4_B12_15DATA_MASK_SHIFT)) & EIM_EICHD4_WORD4_B12_15DATA_MASK_MASK) 546 /*! @} */ 547 548 /*! @name EICHD5_WORD0 - Error Injection Channel Descriptor 5, Word0 */ 549 /*! @{ */ 550 551 #define EIM_EICHD5_WORD0_CHKBIT_MASK_MASK (0xFFFFFFF0U) 552 #define EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT (4U) 553 #define EIM_EICHD5_WORD0_CHKBIT_MASK_WIDTH (28U) 554 #define EIM_EICHD5_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD5_WORD0_CHKBIT_MASK_MASK) 555 /*! @} */ 556 557 /*! @name EICHD5_WORD1 - Error Injection Channel Descriptor 5, Word1 */ 558 /*! @{ */ 559 560 #define EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK (0xFFU) 561 #define EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT (0U) 562 #define EIM_EICHD5_WORD1_B0_3DATA_MASK_WIDTH (8U) 563 #define EIM_EICHD5_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK) 564 /*! @} */ 565 566 /*! @name EICHD5_WORD2 - Error Injection Channel Descriptor 5, Word2 */ 567 /*! @{ */ 568 569 #define EIM_EICHD5_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 570 #define EIM_EICHD5_WORD2_B4_7DATA_MASK_SHIFT (0U) 571 #define EIM_EICHD5_WORD2_B4_7DATA_MASK_WIDTH (32U) 572 #define EIM_EICHD5_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD5_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD5_WORD2_B4_7DATA_MASK_MASK) 573 /*! @} */ 574 575 /*! @name EICHD5_WORD3 - Error Injection Channel Descriptor 5, Word3 */ 576 /*! @{ */ 577 578 #define EIM_EICHD5_WORD3_B8_11DATA_MASK_MASK (0xFFFFFFFFU) 579 #define EIM_EICHD5_WORD3_B8_11DATA_MASK_SHIFT (0U) 580 #define EIM_EICHD5_WORD3_B8_11DATA_MASK_WIDTH (32U) 581 #define EIM_EICHD5_WORD3_B8_11DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD5_WORD3_B8_11DATA_MASK_SHIFT)) & EIM_EICHD5_WORD3_B8_11DATA_MASK_MASK) 582 /*! @} */ 583 584 /*! @name EICHD5_WORD4 - Error Injection Channel Descriptor 5, Word4 */ 585 /*! @{ */ 586 587 #define EIM_EICHD5_WORD4_B12_15DATA_MASK_MASK (0xFFFFFFFFU) 588 #define EIM_EICHD5_WORD4_B12_15DATA_MASK_SHIFT (0U) 589 #define EIM_EICHD5_WORD4_B12_15DATA_MASK_WIDTH (32U) 590 #define EIM_EICHD5_WORD4_B12_15DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD5_WORD4_B12_15DATA_MASK_SHIFT)) & EIM_EICHD5_WORD4_B12_15DATA_MASK_MASK) 591 /*! @} */ 592 593 /*! @name EICHD6_WORD0 - Error Injection Channel Descriptor 6, Word0 */ 594 /*! @{ */ 595 596 #define EIM_EICHD6_WORD0_CHKBIT_MASK_MASK (0xFFFFFFF0U) 597 #define EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT (4U) 598 #define EIM_EICHD6_WORD0_CHKBIT_MASK_WIDTH (28U) 599 #define EIM_EICHD6_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD6_WORD0_CHKBIT_MASK_MASK) 600 /*! @} */ 601 602 /*! @name EICHD6_WORD1 - Error Injection Channel Descriptor 6, Word1 */ 603 /*! @{ */ 604 605 #define EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 606 #define EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT (0U) 607 #define EIM_EICHD6_WORD1_B0_3DATA_MASK_WIDTH (32U) 608 #define EIM_EICHD6_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK) 609 /*! @} */ 610 611 /*! @name EICHD6_WORD2 - Error Injection Channel Descriptor 6, Word2 */ 612 /*! @{ */ 613 614 #define EIM_EICHD6_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 615 #define EIM_EICHD6_WORD2_B4_7DATA_MASK_SHIFT (0U) 616 #define EIM_EICHD6_WORD2_B4_7DATA_MASK_WIDTH (32U) 617 #define EIM_EICHD6_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD6_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD6_WORD2_B4_7DATA_MASK_MASK) 618 /*! @} */ 619 620 /*! @name EICHD6_WORD3 - Error Injection Channel Descriptor 6, Word3 */ 621 /*! @{ */ 622 623 #define EIM_EICHD6_WORD3_B8_11DATA_MASK_MASK (0xFFFFFFFFU) 624 #define EIM_EICHD6_WORD3_B8_11DATA_MASK_SHIFT (0U) 625 #define EIM_EICHD6_WORD3_B8_11DATA_MASK_WIDTH (32U) 626 #define EIM_EICHD6_WORD3_B8_11DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD6_WORD3_B8_11DATA_MASK_SHIFT)) & EIM_EICHD6_WORD3_B8_11DATA_MASK_MASK) 627 /*! @} */ 628 629 /*! @name EICHD6_WORD4 - Error Injection Channel Descriptor 6, Word4 */ 630 /*! @{ */ 631 632 #define EIM_EICHD6_WORD4_B12_15DATA_MASK_MASK (0xFFFFFFFFU) 633 #define EIM_EICHD6_WORD4_B12_15DATA_MASK_SHIFT (0U) 634 #define EIM_EICHD6_WORD4_B12_15DATA_MASK_WIDTH (32U) 635 #define EIM_EICHD6_WORD4_B12_15DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD6_WORD4_B12_15DATA_MASK_SHIFT)) & EIM_EICHD6_WORD4_B12_15DATA_MASK_MASK) 636 /*! @} */ 637 638 /*! @name EICHD7_WORD0 - Error Injection Channel Descriptor 7, Word0 */ 639 /*! @{ */ 640 641 #define EIM_EICHD7_WORD0_CHKBIT_MASK_MASK (0xFFFFFFF0U) 642 #define EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT (4U) 643 #define EIM_EICHD7_WORD0_CHKBIT_MASK_WIDTH (28U) 644 #define EIM_EICHD7_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD7_WORD0_CHKBIT_MASK_MASK) 645 /*! @} */ 646 647 /*! @name EICHD7_WORD1 - Error Injection Channel Descriptor 7, Word1 */ 648 /*! @{ */ 649 650 #define EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 651 #define EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT (0U) 652 #define EIM_EICHD7_WORD1_B0_3DATA_MASK_WIDTH (32U) 653 #define EIM_EICHD7_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK) 654 /*! @} */ 655 656 /*! @name EICHD7_WORD2 - Error Injection Channel Descriptor 7, Word2 */ 657 /*! @{ */ 658 659 #define EIM_EICHD7_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 660 #define EIM_EICHD7_WORD2_B4_7DATA_MASK_SHIFT (0U) 661 #define EIM_EICHD7_WORD2_B4_7DATA_MASK_WIDTH (32U) 662 #define EIM_EICHD7_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD7_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD7_WORD2_B4_7DATA_MASK_MASK) 663 /*! @} */ 664 665 /*! @name EICHD7_WORD3 - Error Injection Channel Descriptor 7, Word3 */ 666 /*! @{ */ 667 668 #define EIM_EICHD7_WORD3_B8_11DATA_MASK_MASK (0xFFFFFFFFU) 669 #define EIM_EICHD7_WORD3_B8_11DATA_MASK_SHIFT (0U) 670 #define EIM_EICHD7_WORD3_B8_11DATA_MASK_WIDTH (32U) 671 #define EIM_EICHD7_WORD3_B8_11DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD7_WORD3_B8_11DATA_MASK_SHIFT)) & EIM_EICHD7_WORD3_B8_11DATA_MASK_MASK) 672 /*! @} */ 673 674 /*! @name EICHD7_WORD4 - Error Injection Channel Descriptor 7, Word4 */ 675 /*! @{ */ 676 677 #define EIM_EICHD7_WORD4_B12_15DATA_MASK_MASK (0xFFFFFFFFU) 678 #define EIM_EICHD7_WORD4_B12_15DATA_MASK_SHIFT (0U) 679 #define EIM_EICHD7_WORD4_B12_15DATA_MASK_WIDTH (32U) 680 #define EIM_EICHD7_WORD4_B12_15DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD7_WORD4_B12_15DATA_MASK_SHIFT)) & EIM_EICHD7_WORD4_B12_15DATA_MASK_MASK) 681 /*! @} */ 682 683 /*! @name EICHD8_WORD0 - Error Injection Channel Descriptor 8, Word0 */ 684 /*! @{ */ 685 686 #define EIM_EICHD8_WORD0_CHKBIT_MASK_MASK (0xFFFC0000U) 687 #define EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT (18U) 688 #define EIM_EICHD8_WORD0_CHKBIT_MASK_WIDTH (14U) 689 #define EIM_EICHD8_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD8_WORD0_CHKBIT_MASK_MASK) 690 /*! @} */ 691 692 /*! @name EICHD8_WORD1 - Error Injection Channel Descriptor 8, Word1 */ 693 /*! @{ */ 694 695 #define EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK (0xFFFU) 696 #define EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT (0U) 697 #define EIM_EICHD8_WORD1_B0_3DATA_MASK_WIDTH (12U) 698 #define EIM_EICHD8_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK) 699 /*! @} */ 700 701 /*! @name EICHD8_WORD2 - Error Injection Channel Descriptor 8, Word2 */ 702 /*! @{ */ 703 704 #define EIM_EICHD8_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 705 #define EIM_EICHD8_WORD2_B4_7DATA_MASK_SHIFT (0U) 706 #define EIM_EICHD8_WORD2_B4_7DATA_MASK_WIDTH (32U) 707 #define EIM_EICHD8_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD8_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD8_WORD2_B4_7DATA_MASK_MASK) 708 /*! @} */ 709 710 /*! @name EICHD9_WORD0 - Error Injection Channel Descriptor 9, Word0 */ 711 /*! @{ */ 712 713 #define EIM_EICHD9_WORD0_CHKBIT_MASK_MASK (0xFFFF0000U) 714 #define EIM_EICHD9_WORD0_CHKBIT_MASK_SHIFT (16U) 715 #define EIM_EICHD9_WORD0_CHKBIT_MASK_WIDTH (16U) 716 #define EIM_EICHD9_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD9_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD9_WORD0_CHKBIT_MASK_MASK) 717 /*! @} */ 718 719 /*! @name EICHD9_WORD1 - Error Injection Channel Descriptor 9, Word1 */ 720 /*! @{ */ 721 722 #define EIM_EICHD9_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 723 #define EIM_EICHD9_WORD1_B0_3DATA_MASK_SHIFT (0U) 724 #define EIM_EICHD9_WORD1_B0_3DATA_MASK_WIDTH (32U) 725 #define EIM_EICHD9_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD9_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD9_WORD1_B0_3DATA_MASK_MASK) 726 /*! @} */ 727 728 /*! @name EICHD9_WORD2 - Error Injection Channel Descriptor 9, Word2 */ 729 /*! @{ */ 730 731 #define EIM_EICHD9_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 732 #define EIM_EICHD9_WORD2_B4_7DATA_MASK_SHIFT (0U) 733 #define EIM_EICHD9_WORD2_B4_7DATA_MASK_WIDTH (32U) 734 #define EIM_EICHD9_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD9_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD9_WORD2_B4_7DATA_MASK_MASK) 735 /*! @} */ 736 737 /*! @name EICHD9_WORD3 - Error Injection Channel Descriptor 9, Word3 */ 738 /*! @{ */ 739 740 #define EIM_EICHD9_WORD3_B8_11DATA_MASK_MASK (0xFFFFFFFFU) 741 #define EIM_EICHD9_WORD3_B8_11DATA_MASK_SHIFT (0U) 742 #define EIM_EICHD9_WORD3_B8_11DATA_MASK_WIDTH (32U) 743 #define EIM_EICHD9_WORD3_B8_11DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD9_WORD3_B8_11DATA_MASK_SHIFT)) & EIM_EICHD9_WORD3_B8_11DATA_MASK_MASK) 744 /*! @} */ 745 746 /*! @name EICHD9_WORD4 - Error Injection Channel Descriptor 9, Word4 */ 747 /*! @{ */ 748 749 #define EIM_EICHD9_WORD4_B12_15DATA_MASK_MASK (0xFFFFFFFFU) 750 #define EIM_EICHD9_WORD4_B12_15DATA_MASK_SHIFT (0U) 751 #define EIM_EICHD9_WORD4_B12_15DATA_MASK_WIDTH (32U) 752 #define EIM_EICHD9_WORD4_B12_15DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD9_WORD4_B12_15DATA_MASK_SHIFT)) & EIM_EICHD9_WORD4_B12_15DATA_MASK_MASK) 753 /*! @} */ 754 755 /*! @name EICHD10_WORD0 - Error Injection Channel Descriptor 10, Word0 */ 756 /*! @{ */ 757 758 #define EIM_EICHD10_WORD0_CHKBIT_MASK_MASK (0xFFFFFFF0U) 759 #define EIM_EICHD10_WORD0_CHKBIT_MASK_SHIFT (4U) 760 #define EIM_EICHD10_WORD0_CHKBIT_MASK_WIDTH (28U) 761 #define EIM_EICHD10_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD10_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD10_WORD0_CHKBIT_MASK_MASK) 762 /*! @} */ 763 764 /*! @name EICHD10_WORD1 - Error Injection Channel Descriptor 10, Word1 */ 765 /*! @{ */ 766 767 #define EIM_EICHD10_WORD1_B0_3DATA_MASK_MASK (0xFFU) 768 #define EIM_EICHD10_WORD1_B0_3DATA_MASK_SHIFT (0U) 769 #define EIM_EICHD10_WORD1_B0_3DATA_MASK_WIDTH (8U) 770 #define EIM_EICHD10_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD10_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD10_WORD1_B0_3DATA_MASK_MASK) 771 /*! @} */ 772 773 /*! @name EICHD10_WORD2 - Error Injection Channel Descriptor 10, Word2 */ 774 /*! @{ */ 775 776 #define EIM_EICHD10_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 777 #define EIM_EICHD10_WORD2_B4_7DATA_MASK_SHIFT (0U) 778 #define EIM_EICHD10_WORD2_B4_7DATA_MASK_WIDTH (32U) 779 #define EIM_EICHD10_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD10_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD10_WORD2_B4_7DATA_MASK_MASK) 780 /*! @} */ 781 782 /*! @name EICHD10_WORD3 - Error Injection Channel Descriptor 10, Word3 */ 783 /*! @{ */ 784 785 #define EIM_EICHD10_WORD3_B8_11DATA_MASK_MASK (0xFFFFFFFFU) 786 #define EIM_EICHD10_WORD3_B8_11DATA_MASK_SHIFT (0U) 787 #define EIM_EICHD10_WORD3_B8_11DATA_MASK_WIDTH (32U) 788 #define EIM_EICHD10_WORD3_B8_11DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD10_WORD3_B8_11DATA_MASK_SHIFT)) & EIM_EICHD10_WORD3_B8_11DATA_MASK_MASK) 789 /*! @} */ 790 791 /*! @name EICHD10_WORD4 - Error Injection Channel Descriptor 10, Word4 */ 792 /*! @{ */ 793 794 #define EIM_EICHD10_WORD4_B12_15DATA_MASK_MASK (0xFFFFFFFFU) 795 #define EIM_EICHD10_WORD4_B12_15DATA_MASK_SHIFT (0U) 796 #define EIM_EICHD10_WORD4_B12_15DATA_MASK_WIDTH (32U) 797 #define EIM_EICHD10_WORD4_B12_15DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD10_WORD4_B12_15DATA_MASK_SHIFT)) & EIM_EICHD10_WORD4_B12_15DATA_MASK_MASK) 798 /*! @} */ 799 800 /*! @name EICHD11_WORD0 - Error Injection Channel Descriptor 11, Word0 */ 801 /*! @{ */ 802 803 #define EIM_EICHD11_WORD0_CHKBIT_MASK_MASK (0xFFFFFFF0U) 804 #define EIM_EICHD11_WORD0_CHKBIT_MASK_SHIFT (4U) 805 #define EIM_EICHD11_WORD0_CHKBIT_MASK_WIDTH (28U) 806 #define EIM_EICHD11_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD11_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD11_WORD0_CHKBIT_MASK_MASK) 807 /*! @} */ 808 809 /*! @name EICHD11_WORD1 - Error Injection Channel Descriptor 11, Word1 */ 810 /*! @{ */ 811 812 #define EIM_EICHD11_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 813 #define EIM_EICHD11_WORD1_B0_3DATA_MASK_SHIFT (0U) 814 #define EIM_EICHD11_WORD1_B0_3DATA_MASK_WIDTH (32U) 815 #define EIM_EICHD11_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD11_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD11_WORD1_B0_3DATA_MASK_MASK) 816 /*! @} */ 817 818 /*! @name EICHD11_WORD2 - Error Injection Channel Descriptor 11, Word2 */ 819 /*! @{ */ 820 821 #define EIM_EICHD11_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 822 #define EIM_EICHD11_WORD2_B4_7DATA_MASK_SHIFT (0U) 823 #define EIM_EICHD11_WORD2_B4_7DATA_MASK_WIDTH (32U) 824 #define EIM_EICHD11_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD11_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD11_WORD2_B4_7DATA_MASK_MASK) 825 /*! @} */ 826 827 /*! @name EICHD11_WORD3 - Error Injection Channel Descriptor 11, Word3 */ 828 /*! @{ */ 829 830 #define EIM_EICHD11_WORD3_B8_11DATA_MASK_MASK (0xFFFFFFFFU) 831 #define EIM_EICHD11_WORD3_B8_11DATA_MASK_SHIFT (0U) 832 #define EIM_EICHD11_WORD3_B8_11DATA_MASK_WIDTH (32U) 833 #define EIM_EICHD11_WORD3_B8_11DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD11_WORD3_B8_11DATA_MASK_SHIFT)) & EIM_EICHD11_WORD3_B8_11DATA_MASK_MASK) 834 /*! @} */ 835 836 /*! @name EICHD11_WORD4 - Error Injection Channel Descriptor 11, Word4 */ 837 /*! @{ */ 838 839 #define EIM_EICHD11_WORD4_B12_15DATA_MASK_MASK (0xFFFFFFFFU) 840 #define EIM_EICHD11_WORD4_B12_15DATA_MASK_SHIFT (0U) 841 #define EIM_EICHD11_WORD4_B12_15DATA_MASK_WIDTH (32U) 842 #define EIM_EICHD11_WORD4_B12_15DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD11_WORD4_B12_15DATA_MASK_SHIFT)) & EIM_EICHD11_WORD4_B12_15DATA_MASK_MASK) 843 /*! @} */ 844 845 /*! @name EICHD12_WORD0 - Error Injection Channel Descriptor 12, Word0 */ 846 /*! @{ */ 847 848 #define EIM_EICHD12_WORD0_CHKBIT_MASK_MASK (0xFFFFFFF0U) 849 #define EIM_EICHD12_WORD0_CHKBIT_MASK_SHIFT (4U) 850 #define EIM_EICHD12_WORD0_CHKBIT_MASK_WIDTH (28U) 851 #define EIM_EICHD12_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD12_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD12_WORD0_CHKBIT_MASK_MASK) 852 /*! @} */ 853 854 /*! @name EICHD12_WORD1 - Error Injection Channel Descriptor 12, Word1 */ 855 /*! @{ */ 856 857 #define EIM_EICHD12_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 858 #define EIM_EICHD12_WORD1_B0_3DATA_MASK_SHIFT (0U) 859 #define EIM_EICHD12_WORD1_B0_3DATA_MASK_WIDTH (32U) 860 #define EIM_EICHD12_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD12_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD12_WORD1_B0_3DATA_MASK_MASK) 861 /*! @} */ 862 863 /*! @name EICHD12_WORD2 - Error Injection Channel Descriptor 12, Word2 */ 864 /*! @{ */ 865 866 #define EIM_EICHD12_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 867 #define EIM_EICHD12_WORD2_B4_7DATA_MASK_SHIFT (0U) 868 #define EIM_EICHD12_WORD2_B4_7DATA_MASK_WIDTH (32U) 869 #define EIM_EICHD12_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD12_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD12_WORD2_B4_7DATA_MASK_MASK) 870 /*! @} */ 871 872 /*! @name EICHD12_WORD3 - Error Injection Channel Descriptor 12, Word3 */ 873 /*! @{ */ 874 875 #define EIM_EICHD12_WORD3_B8_11DATA_MASK_MASK (0xFFFFFFFFU) 876 #define EIM_EICHD12_WORD3_B8_11DATA_MASK_SHIFT (0U) 877 #define EIM_EICHD12_WORD3_B8_11DATA_MASK_WIDTH (32U) 878 #define EIM_EICHD12_WORD3_B8_11DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD12_WORD3_B8_11DATA_MASK_SHIFT)) & EIM_EICHD12_WORD3_B8_11DATA_MASK_MASK) 879 /*! @} */ 880 881 /*! @name EICHD12_WORD4 - Error Injection Channel Descriptor 12, Word4 */ 882 /*! @{ */ 883 884 #define EIM_EICHD12_WORD4_B12_15DATA_MASK_MASK (0xFFFFFFFFU) 885 #define EIM_EICHD12_WORD4_B12_15DATA_MASK_SHIFT (0U) 886 #define EIM_EICHD12_WORD4_B12_15DATA_MASK_WIDTH (32U) 887 #define EIM_EICHD12_WORD4_B12_15DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD12_WORD4_B12_15DATA_MASK_SHIFT)) & EIM_EICHD12_WORD4_B12_15DATA_MASK_MASK) 888 /*! @} */ 889 890 /*! @name EICHD13_WORD0 - Error Injection Channel Descriptor 13, Word0 */ 891 /*! @{ */ 892 893 #define EIM_EICHD13_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 894 #define EIM_EICHD13_WORD0_CHKBIT_MASK_SHIFT (24U) 895 #define EIM_EICHD13_WORD0_CHKBIT_MASK_WIDTH (8U) 896 #define EIM_EICHD13_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD13_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD13_WORD0_CHKBIT_MASK_MASK) 897 /*! @} */ 898 899 /*! @name EICHD13_WORD1 - Error Injection Channel Descriptor 13, Word1 */ 900 /*! @{ */ 901 902 #define EIM_EICHD13_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 903 #define EIM_EICHD13_WORD1_B0_3DATA_MASK_SHIFT (0U) 904 #define EIM_EICHD13_WORD1_B0_3DATA_MASK_WIDTH (32U) 905 #define EIM_EICHD13_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD13_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD13_WORD1_B0_3DATA_MASK_MASK) 906 /*! @} */ 907 908 /*! @name EICHD13_WORD2 - Error Injection Channel Descriptor 13, Word2 */ 909 /*! @{ */ 910 911 #define EIM_EICHD13_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 912 #define EIM_EICHD13_WORD2_B4_7DATA_MASK_SHIFT (0U) 913 #define EIM_EICHD13_WORD2_B4_7DATA_MASK_WIDTH (32U) 914 #define EIM_EICHD13_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD13_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD13_WORD2_B4_7DATA_MASK_MASK) 915 /*! @} */ 916 917 /*! @name EICHD14_WORD0 - Error Injection Channel Descriptor 14, Word0 */ 918 /*! @{ */ 919 920 #define EIM_EICHD14_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 921 #define EIM_EICHD14_WORD0_CHKBIT_MASK_SHIFT (24U) 922 #define EIM_EICHD14_WORD0_CHKBIT_MASK_WIDTH (8U) 923 #define EIM_EICHD14_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD14_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD14_WORD0_CHKBIT_MASK_MASK) 924 /*! @} */ 925 926 /*! @name EICHD14_WORD1 - Error Injection Channel Descriptor 14, Word1 */ 927 /*! @{ */ 928 929 #define EIM_EICHD14_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 930 #define EIM_EICHD14_WORD1_B0_3DATA_MASK_SHIFT (0U) 931 #define EIM_EICHD14_WORD1_B0_3DATA_MASK_WIDTH (32U) 932 #define EIM_EICHD14_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD14_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD14_WORD1_B0_3DATA_MASK_MASK) 933 /*! @} */ 934 935 /*! @name EICHD15_WORD0 - Error Injection Channel Descriptor 15, Word0 */ 936 /*! @{ */ 937 938 #define EIM_EICHD15_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 939 #define EIM_EICHD15_WORD0_CHKBIT_MASK_SHIFT (24U) 940 #define EIM_EICHD15_WORD0_CHKBIT_MASK_WIDTH (8U) 941 #define EIM_EICHD15_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD15_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD15_WORD0_CHKBIT_MASK_MASK) 942 /*! @} */ 943 944 /*! @name EICHD15_WORD1 - Error Injection Channel Descriptor 15, Word1 */ 945 /*! @{ */ 946 947 #define EIM_EICHD15_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 948 #define EIM_EICHD15_WORD1_B0_3DATA_MASK_SHIFT (0U) 949 #define EIM_EICHD15_WORD1_B0_3DATA_MASK_WIDTH (32U) 950 #define EIM_EICHD15_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD15_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD15_WORD1_B0_3DATA_MASK_MASK) 951 /*! @} */ 952 953 /*! @name EICHD16_WORD0 - Error Injection Channel Descriptor 16, Word0 */ 954 /*! @{ */ 955 956 #define EIM_EICHD16_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 957 #define EIM_EICHD16_WORD0_CHKBIT_MASK_SHIFT (24U) 958 #define EIM_EICHD16_WORD0_CHKBIT_MASK_WIDTH (8U) 959 #define EIM_EICHD16_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD16_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD16_WORD0_CHKBIT_MASK_MASK) 960 /*! @} */ 961 962 /*! @name EICHD16_WORD1 - Error Injection Channel Descriptor 16, Word1 */ 963 /*! @{ */ 964 965 #define EIM_EICHD16_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 966 #define EIM_EICHD16_WORD1_B0_3DATA_MASK_SHIFT (0U) 967 #define EIM_EICHD16_WORD1_B0_3DATA_MASK_WIDTH (32U) 968 #define EIM_EICHD16_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD16_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD16_WORD1_B0_3DATA_MASK_MASK) 969 /*! @} */ 970 971 /*! @name EICHD16_WORD2 - Error Injection Channel Descriptor 16, Word2 */ 972 /*! @{ */ 973 974 #define EIM_EICHD16_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 975 #define EIM_EICHD16_WORD2_B4_7DATA_MASK_SHIFT (0U) 976 #define EIM_EICHD16_WORD2_B4_7DATA_MASK_WIDTH (32U) 977 #define EIM_EICHD16_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD16_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD16_WORD2_B4_7DATA_MASK_MASK) 978 /*! @} */ 979 980 /*! @name EICHD17_WORD0 - Error Injection Channel Descriptor 17, Word0 */ 981 /*! @{ */ 982 983 #define EIM_EICHD17_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 984 #define EIM_EICHD17_WORD0_CHKBIT_MASK_SHIFT (24U) 985 #define EIM_EICHD17_WORD0_CHKBIT_MASK_WIDTH (8U) 986 #define EIM_EICHD17_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD17_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD17_WORD0_CHKBIT_MASK_MASK) 987 /*! @} */ 988 989 /*! @name EICHD17_WORD1 - Error Injection Channel Descriptor 17, Word1 */ 990 /*! @{ */ 991 992 #define EIM_EICHD17_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 993 #define EIM_EICHD17_WORD1_B0_3DATA_MASK_SHIFT (0U) 994 #define EIM_EICHD17_WORD1_B0_3DATA_MASK_WIDTH (32U) 995 #define EIM_EICHD17_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD17_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD17_WORD1_B0_3DATA_MASK_MASK) 996 /*! @} */ 997 998 /*! @name EICHD18_WORD0 - Error Injection Channel Descriptor 18, Word0 */ 999 /*! @{ */ 1000 1001 #define EIM_EICHD18_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 1002 #define EIM_EICHD18_WORD0_CHKBIT_MASK_SHIFT (24U) 1003 #define EIM_EICHD18_WORD0_CHKBIT_MASK_WIDTH (8U) 1004 #define EIM_EICHD18_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD18_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD18_WORD0_CHKBIT_MASK_MASK) 1005 /*! @} */ 1006 1007 /*! @name EICHD18_WORD1 - Error Injection Channel Descriptor 18, Word1 */ 1008 /*! @{ */ 1009 1010 #define EIM_EICHD18_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 1011 #define EIM_EICHD18_WORD1_B0_3DATA_MASK_SHIFT (0U) 1012 #define EIM_EICHD18_WORD1_B0_3DATA_MASK_WIDTH (32U) 1013 #define EIM_EICHD18_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD18_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD18_WORD1_B0_3DATA_MASK_MASK) 1014 /*! @} */ 1015 1016 /*! @name EICHD19_WORD1 - Error Injection Channel Descriptor 19, Word1 */ 1017 /*! @{ */ 1018 1019 #define EIM_EICHD19_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFU) 1020 #define EIM_EICHD19_WORD1_B0_3DATA_MASK_SHIFT (0U) 1021 #define EIM_EICHD19_WORD1_B0_3DATA_MASK_WIDTH (28U) 1022 #define EIM_EICHD19_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD19_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD19_WORD1_B0_3DATA_MASK_MASK) 1023 /*! @} */ 1024 1025 /*! @name EICHD19_WORD2 - Error Injection Channel Descriptor 19, Word2 */ 1026 /*! @{ */ 1027 1028 #define EIM_EICHD19_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1029 #define EIM_EICHD19_WORD2_B4_7DATA_MASK_SHIFT (0U) 1030 #define EIM_EICHD19_WORD2_B4_7DATA_MASK_WIDTH (32U) 1031 #define EIM_EICHD19_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD19_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD19_WORD2_B4_7DATA_MASK_MASK) 1032 /*! @} */ 1033 1034 /*! @name EICHD19_WORD3 - Error Injection Channel Descriptor 19, Word3 */ 1035 /*! @{ */ 1036 1037 #define EIM_EICHD19_WORD3_B8_11DATA_MASK_MASK (0xFFFFFFFFU) 1038 #define EIM_EICHD19_WORD3_B8_11DATA_MASK_SHIFT (0U) 1039 #define EIM_EICHD19_WORD3_B8_11DATA_MASK_WIDTH (32U) 1040 #define EIM_EICHD19_WORD3_B8_11DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD19_WORD3_B8_11DATA_MASK_SHIFT)) & EIM_EICHD19_WORD3_B8_11DATA_MASK_MASK) 1041 /*! @} */ 1042 1043 /*! @name EICHD19_WORD4 - Error Injection Channel Descriptor 19, Word4 */ 1044 /*! @{ */ 1045 1046 #define EIM_EICHD19_WORD4_B12_15DATA_MASK_MASK (0xFFFFFFFFU) 1047 #define EIM_EICHD19_WORD4_B12_15DATA_MASK_SHIFT (0U) 1048 #define EIM_EICHD19_WORD4_B12_15DATA_MASK_WIDTH (32U) 1049 #define EIM_EICHD19_WORD4_B12_15DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD19_WORD4_B12_15DATA_MASK_SHIFT)) & EIM_EICHD19_WORD4_B12_15DATA_MASK_MASK) 1050 /*! @} */ 1051 1052 /*! @name EICHD19_WORD5 - Error Injection Channel Descriptor 19, Word5 */ 1053 /*! @{ */ 1054 1055 #define EIM_EICHD19_WORD5_B16_19DATA_MASK_MASK (0xFFFFFFFFU) 1056 #define EIM_EICHD19_WORD5_B16_19DATA_MASK_SHIFT (0U) 1057 #define EIM_EICHD19_WORD5_B16_19DATA_MASK_WIDTH (32U) 1058 #define EIM_EICHD19_WORD5_B16_19DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD19_WORD5_B16_19DATA_MASK_SHIFT)) & EIM_EICHD19_WORD5_B16_19DATA_MASK_MASK) 1059 /*! @} */ 1060 1061 /*! @name EICHD19_WORD6 - Error Injection Channel Descriptor 19, Word6 */ 1062 /*! @{ */ 1063 1064 #define EIM_EICHD19_WORD6_B20_23DATA_MASK_MASK (0xFFFFFFFFU) 1065 #define EIM_EICHD19_WORD6_B20_23DATA_MASK_SHIFT (0U) 1066 #define EIM_EICHD19_WORD6_B20_23DATA_MASK_WIDTH (32U) 1067 #define EIM_EICHD19_WORD6_B20_23DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD19_WORD6_B20_23DATA_MASK_SHIFT)) & EIM_EICHD19_WORD6_B20_23DATA_MASK_MASK) 1068 /*! @} */ 1069 1070 /*! @name EICHD20_WORD1 - Error Injection Channel Descriptor 20, Word1 */ 1071 /*! @{ */ 1072 1073 #define EIM_EICHD20_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFU) 1074 #define EIM_EICHD20_WORD1_B0_3DATA_MASK_SHIFT (0U) 1075 #define EIM_EICHD20_WORD1_B0_3DATA_MASK_WIDTH (28U) 1076 #define EIM_EICHD20_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD20_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD20_WORD1_B0_3DATA_MASK_MASK) 1077 /*! @} */ 1078 1079 /*! @name EICHD20_WORD2 - Error Injection Channel Descriptor 20, Word2 */ 1080 /*! @{ */ 1081 1082 #define EIM_EICHD20_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1083 #define EIM_EICHD20_WORD2_B4_7DATA_MASK_SHIFT (0U) 1084 #define EIM_EICHD20_WORD2_B4_7DATA_MASK_WIDTH (32U) 1085 #define EIM_EICHD20_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD20_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD20_WORD2_B4_7DATA_MASK_MASK) 1086 /*! @} */ 1087 1088 /*! @name EICHD20_WORD3 - Error Injection Channel Descriptor 20, Word3 */ 1089 /*! @{ */ 1090 1091 #define EIM_EICHD20_WORD3_B8_11DATA_MASK_MASK (0xFFFFFFFFU) 1092 #define EIM_EICHD20_WORD3_B8_11DATA_MASK_SHIFT (0U) 1093 #define EIM_EICHD20_WORD3_B8_11DATA_MASK_WIDTH (32U) 1094 #define EIM_EICHD20_WORD3_B8_11DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD20_WORD3_B8_11DATA_MASK_SHIFT)) & EIM_EICHD20_WORD3_B8_11DATA_MASK_MASK) 1095 /*! @} */ 1096 1097 /*! @name EICHD20_WORD4 - Error Injection Channel Descriptor 20, Word4 */ 1098 /*! @{ */ 1099 1100 #define EIM_EICHD20_WORD4_B12_15DATA_MASK_MASK (0xFFFFFFFFU) 1101 #define EIM_EICHD20_WORD4_B12_15DATA_MASK_SHIFT (0U) 1102 #define EIM_EICHD20_WORD4_B12_15DATA_MASK_WIDTH (32U) 1103 #define EIM_EICHD20_WORD4_B12_15DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD20_WORD4_B12_15DATA_MASK_SHIFT)) & EIM_EICHD20_WORD4_B12_15DATA_MASK_MASK) 1104 /*! @} */ 1105 1106 /*! @name EICHD20_WORD5 - Error Injection Channel Descriptor 20, Word5 */ 1107 /*! @{ */ 1108 1109 #define EIM_EICHD20_WORD5_B16_19DATA_MASK_MASK (0xFFFFFFFFU) 1110 #define EIM_EICHD20_WORD5_B16_19DATA_MASK_SHIFT (0U) 1111 #define EIM_EICHD20_WORD5_B16_19DATA_MASK_WIDTH (32U) 1112 #define EIM_EICHD20_WORD5_B16_19DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD20_WORD5_B16_19DATA_MASK_SHIFT)) & EIM_EICHD20_WORD5_B16_19DATA_MASK_MASK) 1113 /*! @} */ 1114 1115 /*! @name EICHD20_WORD6 - Error Injection Channel Descriptor 20, Word6 */ 1116 /*! @{ */ 1117 1118 #define EIM_EICHD20_WORD6_B20_23DATA_MASK_MASK (0xFFFFFFFFU) 1119 #define EIM_EICHD20_WORD6_B20_23DATA_MASK_SHIFT (0U) 1120 #define EIM_EICHD20_WORD6_B20_23DATA_MASK_WIDTH (32U) 1121 #define EIM_EICHD20_WORD6_B20_23DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD20_WORD6_B20_23DATA_MASK_SHIFT)) & EIM_EICHD20_WORD6_B20_23DATA_MASK_MASK) 1122 /*! @} */ 1123 1124 /*! @name EICHD21_WORD1 - Error Injection Channel Descriptor 21, Word1 */ 1125 /*! @{ */ 1126 1127 #define EIM_EICHD21_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFU) 1128 #define EIM_EICHD21_WORD1_B0_3DATA_MASK_SHIFT (0U) 1129 #define EIM_EICHD21_WORD1_B0_3DATA_MASK_WIDTH (28U) 1130 #define EIM_EICHD21_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD21_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD21_WORD1_B0_3DATA_MASK_MASK) 1131 /*! @} */ 1132 1133 /*! @name EICHD21_WORD2 - Error Injection Channel Descriptor 21, Word2 */ 1134 /*! @{ */ 1135 1136 #define EIM_EICHD21_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1137 #define EIM_EICHD21_WORD2_B4_7DATA_MASK_SHIFT (0U) 1138 #define EIM_EICHD21_WORD2_B4_7DATA_MASK_WIDTH (32U) 1139 #define EIM_EICHD21_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD21_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD21_WORD2_B4_7DATA_MASK_MASK) 1140 /*! @} */ 1141 1142 /*! @name EICHD22_WORD1 - Error Injection Channel Descriptor 22, Word1 */ 1143 /*! @{ */ 1144 1145 #define EIM_EICHD22_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFU) 1146 #define EIM_EICHD22_WORD1_B0_3DATA_MASK_SHIFT (0U) 1147 #define EIM_EICHD22_WORD1_B0_3DATA_MASK_WIDTH (28U) 1148 #define EIM_EICHD22_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD22_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD22_WORD1_B0_3DATA_MASK_MASK) 1149 /*! @} */ 1150 1151 /*! @name EICHD22_WORD2 - Error Injection Channel Descriptor 22, Word2 */ 1152 /*! @{ */ 1153 1154 #define EIM_EICHD22_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1155 #define EIM_EICHD22_WORD2_B4_7DATA_MASK_SHIFT (0U) 1156 #define EIM_EICHD22_WORD2_B4_7DATA_MASK_WIDTH (32U) 1157 #define EIM_EICHD22_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD22_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD22_WORD2_B4_7DATA_MASK_MASK) 1158 /*! @} */ 1159 1160 /*! @name EICHD23_WORD1 - Error Injection Channel Descriptor 23, Word1 */ 1161 /*! @{ */ 1162 1163 #define EIM_EICHD23_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFU) 1164 #define EIM_EICHD23_WORD1_B0_3DATA_MASK_SHIFT (0U) 1165 #define EIM_EICHD23_WORD1_B0_3DATA_MASK_WIDTH (28U) 1166 #define EIM_EICHD23_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD23_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD23_WORD1_B0_3DATA_MASK_MASK) 1167 /*! @} */ 1168 1169 /*! @name EICHD23_WORD2 - Error Injection Channel Descriptor 23, Word2 */ 1170 /*! @{ */ 1171 1172 #define EIM_EICHD23_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1173 #define EIM_EICHD23_WORD2_B4_7DATA_MASK_SHIFT (0U) 1174 #define EIM_EICHD23_WORD2_B4_7DATA_MASK_WIDTH (32U) 1175 #define EIM_EICHD23_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD23_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD23_WORD2_B4_7DATA_MASK_MASK) 1176 /*! @} */ 1177 1178 /*! @name EICHD24_WORD1 - Error Injection Channel Descriptor 24, Word1 */ 1179 /*! @{ */ 1180 1181 #define EIM_EICHD24_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFU) 1182 #define EIM_EICHD24_WORD1_B0_3DATA_MASK_SHIFT (0U) 1183 #define EIM_EICHD24_WORD1_B0_3DATA_MASK_WIDTH (28U) 1184 #define EIM_EICHD24_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD24_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD24_WORD1_B0_3DATA_MASK_MASK) 1185 /*! @} */ 1186 1187 /*! @name EICHD24_WORD2 - Error Injection Channel Descriptor 24, Word2 */ 1188 /*! @{ */ 1189 1190 #define EIM_EICHD24_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1191 #define EIM_EICHD24_WORD2_B4_7DATA_MASK_SHIFT (0U) 1192 #define EIM_EICHD24_WORD2_B4_7DATA_MASK_WIDTH (32U) 1193 #define EIM_EICHD24_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD24_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD24_WORD2_B4_7DATA_MASK_MASK) 1194 /*! @} */ 1195 1196 /*! @name EICHD25_WORD1 - Error Injection Channel Descriptor 25, Word1 */ 1197 /*! @{ */ 1198 1199 #define EIM_EICHD25_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFU) 1200 #define EIM_EICHD25_WORD1_B0_3DATA_MASK_SHIFT (0U) 1201 #define EIM_EICHD25_WORD1_B0_3DATA_MASK_WIDTH (28U) 1202 #define EIM_EICHD25_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD25_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD25_WORD1_B0_3DATA_MASK_MASK) 1203 /*! @} */ 1204 1205 /*! @name EICHD25_WORD2 - Error Injection Channel Descriptor 25, Word2 */ 1206 /*! @{ */ 1207 1208 #define EIM_EICHD25_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1209 #define EIM_EICHD25_WORD2_B4_7DATA_MASK_SHIFT (0U) 1210 #define EIM_EICHD25_WORD2_B4_7DATA_MASK_WIDTH (32U) 1211 #define EIM_EICHD25_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD25_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD25_WORD2_B4_7DATA_MASK_MASK) 1212 /*! @} */ 1213 1214 /*! @name EICHD26_WORD1 - Error Injection Channel Descriptor 26, Word1 */ 1215 /*! @{ */ 1216 1217 #define EIM_EICHD26_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFU) 1218 #define EIM_EICHD26_WORD1_B0_3DATA_MASK_SHIFT (0U) 1219 #define EIM_EICHD26_WORD1_B0_3DATA_MASK_WIDTH (28U) 1220 #define EIM_EICHD26_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD26_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD26_WORD1_B0_3DATA_MASK_MASK) 1221 /*! @} */ 1222 1223 /*! @name EICHD26_WORD2 - Error Injection Channel Descriptor 26, Word2 */ 1224 /*! @{ */ 1225 1226 #define EIM_EICHD26_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1227 #define EIM_EICHD26_WORD2_B4_7DATA_MASK_SHIFT (0U) 1228 #define EIM_EICHD26_WORD2_B4_7DATA_MASK_WIDTH (32U) 1229 #define EIM_EICHD26_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD26_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD26_WORD2_B4_7DATA_MASK_MASK) 1230 /*! @} */ 1231 1232 /*! @name EICHD27_WORD1 - Error Injection Channel Descriptor 27, Word1 */ 1233 /*! @{ */ 1234 1235 #define EIM_EICHD27_WORD1_B0_3DATA_MASK_MASK (0x3FFFFFFFU) 1236 #define EIM_EICHD27_WORD1_B0_3DATA_MASK_SHIFT (0U) 1237 #define EIM_EICHD27_WORD1_B0_3DATA_MASK_WIDTH (30U) 1238 #define EIM_EICHD27_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD27_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD27_WORD1_B0_3DATA_MASK_MASK) 1239 /*! @} */ 1240 1241 /*! @name EICHD28_WORD1 - Error Injection Channel Descriptor 28, Word1 */ 1242 /*! @{ */ 1243 1244 #define EIM_EICHD28_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFU) 1245 #define EIM_EICHD28_WORD1_B0_3DATA_MASK_SHIFT (0U) 1246 #define EIM_EICHD28_WORD1_B0_3DATA_MASK_WIDTH (24U) 1247 #define EIM_EICHD28_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD28_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD28_WORD1_B0_3DATA_MASK_MASK) 1248 /*! @} */ 1249 1250 /*! @name EICHD29_WORD1 - Error Injection Channel Descriptor 29, Word1 */ 1251 /*! @{ */ 1252 1253 #define EIM_EICHD29_WORD1_B0_3DATA_MASK_MASK (0x3FFFFU) 1254 #define EIM_EICHD29_WORD1_B0_3DATA_MASK_SHIFT (0U) 1255 #define EIM_EICHD29_WORD1_B0_3DATA_MASK_WIDTH (18U) 1256 #define EIM_EICHD29_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD29_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD29_WORD1_B0_3DATA_MASK_MASK) 1257 /*! @} */ 1258 1259 /*! @name EICHD30_WORD1 - Error Injection Channel Descriptor 30, Word1 */ 1260 /*! @{ */ 1261 1262 #define EIM_EICHD30_WORD1_B0_3DATA_MASK_MASK (0x3FFFFU) 1263 #define EIM_EICHD30_WORD1_B0_3DATA_MASK_SHIFT (0U) 1264 #define EIM_EICHD30_WORD1_B0_3DATA_MASK_WIDTH (18U) 1265 #define EIM_EICHD30_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD30_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD30_WORD1_B0_3DATA_MASK_MASK) 1266 /*! @} */ 1267 1268 /*! 1269 * @} 1270 */ /* end of group EIM_Register_Masks */ 1271 1272 /*! 1273 * @} 1274 */ /* end of group EIM_Peripheral_Access_Layer */ 1275 1276 #endif /* #if !defined(S32K344_EIM_H_) */ 1277
