1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_AXBS_LITE.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_AXBS_LITE 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_AXBS_LITE_H_) /* Check if memory map has not been already included */ 58 #define S32K344_AXBS_LITE_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- AXBS_LITE Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup AXBS_LITE_Peripheral_Access_Layer AXBS_LITE Peripheral Access Layer 68 * @{ 69 */ 70 71 /** AXBS_LITE - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t PRS0; /**< Priority Slave Registers, offset: 0x0 */ 74 uint8_t RESERVED_0[12]; 75 __IO uint32_t CRS0; /**< Control Register, offset: 0x10 */ 76 uint8_t RESERVED_1[236]; 77 __IO uint32_t PRS1; /**< Priority Slave Registers, offset: 0x100 */ 78 uint8_t RESERVED_2[12]; 79 __IO uint32_t CRS1; /**< Control Register, offset: 0x110 */ 80 uint8_t RESERVED_3[236]; 81 __IO uint32_t PRS2; /**< Priority Slave Registers, offset: 0x200 */ 82 uint8_t RESERVED_4[12]; 83 __IO uint32_t CRS2; /**< Control Register, offset: 0x210 */ 84 uint8_t RESERVED_5[236]; 85 __IO uint32_t PRS3; /**< Priority Slave Registers, offset: 0x300 */ 86 uint8_t RESERVED_6[12]; 87 __IO uint32_t CRS3; /**< Control Register, offset: 0x310 */ 88 uint8_t RESERVED_7[236]; 89 __IO uint32_t PRS4; /**< Priority Slave Registers, offset: 0x400 */ 90 uint8_t RESERVED_8[12]; 91 __IO uint32_t CRS4; /**< Control Register, offset: 0x410 */ 92 uint8_t RESERVED_9[236]; 93 __IO uint32_t PRS5; /**< Priority Slave Registers, offset: 0x500 */ 94 uint8_t RESERVED_10[12]; 95 __IO uint32_t CRS5; /**< Control Register, offset: 0x510 */ 96 uint8_t RESERVED_11[236]; 97 __IO uint32_t PRS6; /**< Priority Slave Registers, offset: 0x600 */ 98 uint8_t RESERVED_12[12]; 99 __IO uint32_t CRS6; /**< Control Register, offset: 0x610 */ 100 } AXBS_LITE_Type, *AXBS_LITE_MemMapPtr; 101 102 /** Number of instances of the AXBS_LITE module. */ 103 #define AXBS_LITE_INSTANCE_COUNT (1u) 104 105 /* AXBS_LITE - Peripheral instance base addresses */ 106 /** Peripheral AXBS_LITE base address */ 107 #define IP_AXBS_LITE_BASE (0x40200000u) 108 /** Peripheral AXBS_LITE base pointer */ 109 #define IP_AXBS_LITE ((AXBS_LITE_Type *)IP_AXBS_LITE_BASE) 110 /** Array initializer of AXBS_LITE peripheral base addresses */ 111 #define IP_AXBS_LITE_BASE_ADDRS { IP_AXBS_LITE_BASE } 112 /** Array initializer of AXBS_LITE peripheral base pointers */ 113 #define IP_AXBS_LITE_BASE_PTRS { IP_AXBS_LITE } 114 115 /* ---------------------------------------------------------------------------- 116 -- AXBS_LITE Register Masks 117 ---------------------------------------------------------------------------- */ 118 119 /*! 120 * @addtogroup AXBS_LITE_Register_Masks AXBS_LITE Register Masks 121 * @{ 122 */ 123 124 /*! @name PRS0 - Priority Slave Registers */ 125 /*! @{ */ 126 127 #define AXBS_LITE_PRS0_M0_MASK (0x7U) 128 #define AXBS_LITE_PRS0_M0_SHIFT (0U) 129 #define AXBS_LITE_PRS0_M0_WIDTH (3U) 130 #define AXBS_LITE_PRS0_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS0_M0_SHIFT)) & AXBS_LITE_PRS0_M0_MASK) 131 132 #define AXBS_LITE_PRS0_M1_MASK (0x70U) 133 #define AXBS_LITE_PRS0_M1_SHIFT (4U) 134 #define AXBS_LITE_PRS0_M1_WIDTH (3U) 135 #define AXBS_LITE_PRS0_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS0_M1_SHIFT)) & AXBS_LITE_PRS0_M1_MASK) 136 137 #define AXBS_LITE_PRS0_M2_MASK (0x700U) 138 #define AXBS_LITE_PRS0_M2_SHIFT (8U) 139 #define AXBS_LITE_PRS0_M2_WIDTH (3U) 140 #define AXBS_LITE_PRS0_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS0_M2_SHIFT)) & AXBS_LITE_PRS0_M2_MASK) 141 142 #define AXBS_LITE_PRS0_M3_MASK (0x7000U) 143 #define AXBS_LITE_PRS0_M3_SHIFT (12U) 144 #define AXBS_LITE_PRS0_M3_WIDTH (3U) 145 #define AXBS_LITE_PRS0_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS0_M3_SHIFT)) & AXBS_LITE_PRS0_M3_MASK) 146 /*! @} */ 147 148 /*! @name CRS0 - Control Register */ 149 /*! @{ */ 150 151 #define AXBS_LITE_CRS0_PARK_MASK (0x7U) 152 #define AXBS_LITE_CRS0_PARK_SHIFT (0U) 153 #define AXBS_LITE_CRS0_PARK_WIDTH (3U) 154 #define AXBS_LITE_CRS0_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS0_PARK_SHIFT)) & AXBS_LITE_CRS0_PARK_MASK) 155 156 #define AXBS_LITE_CRS0_PCTL_MASK (0x30U) 157 #define AXBS_LITE_CRS0_PCTL_SHIFT (4U) 158 #define AXBS_LITE_CRS0_PCTL_WIDTH (2U) 159 #define AXBS_LITE_CRS0_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS0_PCTL_SHIFT)) & AXBS_LITE_CRS0_PCTL_MASK) 160 161 #define AXBS_LITE_CRS0_ARB_MASK (0x300U) 162 #define AXBS_LITE_CRS0_ARB_SHIFT (8U) 163 #define AXBS_LITE_CRS0_ARB_WIDTH (2U) 164 #define AXBS_LITE_CRS0_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS0_ARB_SHIFT)) & AXBS_LITE_CRS0_ARB_MASK) 165 166 #define AXBS_LITE_CRS0_HPE0_MASK (0x10000U) 167 #define AXBS_LITE_CRS0_HPE0_SHIFT (16U) 168 #define AXBS_LITE_CRS0_HPE0_WIDTH (1U) 169 #define AXBS_LITE_CRS0_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS0_HPE0_SHIFT)) & AXBS_LITE_CRS0_HPE0_MASK) 170 171 #define AXBS_LITE_CRS0_HPE1_MASK (0x20000U) 172 #define AXBS_LITE_CRS0_HPE1_SHIFT (17U) 173 #define AXBS_LITE_CRS0_HPE1_WIDTH (1U) 174 #define AXBS_LITE_CRS0_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS0_HPE1_SHIFT)) & AXBS_LITE_CRS0_HPE1_MASK) 175 176 #define AXBS_LITE_CRS0_HPE2_MASK (0x40000U) 177 #define AXBS_LITE_CRS0_HPE2_SHIFT (18U) 178 #define AXBS_LITE_CRS0_HPE2_WIDTH (1U) 179 #define AXBS_LITE_CRS0_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS0_HPE2_SHIFT)) & AXBS_LITE_CRS0_HPE2_MASK) 180 181 #define AXBS_LITE_CRS0_HPE3_MASK (0x80000U) 182 #define AXBS_LITE_CRS0_HPE3_SHIFT (19U) 183 #define AXBS_LITE_CRS0_HPE3_WIDTH (1U) 184 #define AXBS_LITE_CRS0_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS0_HPE3_SHIFT)) & AXBS_LITE_CRS0_HPE3_MASK) 185 186 #define AXBS_LITE_CRS0_HLP_MASK (0x40000000U) 187 #define AXBS_LITE_CRS0_HLP_SHIFT (30U) 188 #define AXBS_LITE_CRS0_HLP_WIDTH (1U) 189 #define AXBS_LITE_CRS0_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS0_HLP_SHIFT)) & AXBS_LITE_CRS0_HLP_MASK) 190 191 #define AXBS_LITE_CRS0_RO_MASK (0x80000000U) 192 #define AXBS_LITE_CRS0_RO_SHIFT (31U) 193 #define AXBS_LITE_CRS0_RO_WIDTH (1U) 194 #define AXBS_LITE_CRS0_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS0_RO_SHIFT)) & AXBS_LITE_CRS0_RO_MASK) 195 /*! @} */ 196 197 /*! @name PRS1 - Priority Slave Registers */ 198 /*! @{ */ 199 200 #define AXBS_LITE_PRS1_M0_MASK (0x7U) 201 #define AXBS_LITE_PRS1_M0_SHIFT (0U) 202 #define AXBS_LITE_PRS1_M0_WIDTH (3U) 203 #define AXBS_LITE_PRS1_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS1_M0_SHIFT)) & AXBS_LITE_PRS1_M0_MASK) 204 205 #define AXBS_LITE_PRS1_M1_MASK (0x70U) 206 #define AXBS_LITE_PRS1_M1_SHIFT (4U) 207 #define AXBS_LITE_PRS1_M1_WIDTH (3U) 208 #define AXBS_LITE_PRS1_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS1_M1_SHIFT)) & AXBS_LITE_PRS1_M1_MASK) 209 210 #define AXBS_LITE_PRS1_M2_MASK (0x700U) 211 #define AXBS_LITE_PRS1_M2_SHIFT (8U) 212 #define AXBS_LITE_PRS1_M2_WIDTH (3U) 213 #define AXBS_LITE_PRS1_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS1_M2_SHIFT)) & AXBS_LITE_PRS1_M2_MASK) 214 215 #define AXBS_LITE_PRS1_M3_MASK (0x7000U) 216 #define AXBS_LITE_PRS1_M3_SHIFT (12U) 217 #define AXBS_LITE_PRS1_M3_WIDTH (3U) 218 #define AXBS_LITE_PRS1_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS1_M3_SHIFT)) & AXBS_LITE_PRS1_M3_MASK) 219 /*! @} */ 220 221 /*! @name CRS1 - Control Register */ 222 /*! @{ */ 223 224 #define AXBS_LITE_CRS1_PARK_MASK (0x7U) 225 #define AXBS_LITE_CRS1_PARK_SHIFT (0U) 226 #define AXBS_LITE_CRS1_PARK_WIDTH (3U) 227 #define AXBS_LITE_CRS1_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS1_PARK_SHIFT)) & AXBS_LITE_CRS1_PARK_MASK) 228 229 #define AXBS_LITE_CRS1_PCTL_MASK (0x30U) 230 #define AXBS_LITE_CRS1_PCTL_SHIFT (4U) 231 #define AXBS_LITE_CRS1_PCTL_WIDTH (2U) 232 #define AXBS_LITE_CRS1_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS1_PCTL_SHIFT)) & AXBS_LITE_CRS1_PCTL_MASK) 233 234 #define AXBS_LITE_CRS1_ARB_MASK (0x300U) 235 #define AXBS_LITE_CRS1_ARB_SHIFT (8U) 236 #define AXBS_LITE_CRS1_ARB_WIDTH (2U) 237 #define AXBS_LITE_CRS1_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS1_ARB_SHIFT)) & AXBS_LITE_CRS1_ARB_MASK) 238 239 #define AXBS_LITE_CRS1_HPE0_MASK (0x10000U) 240 #define AXBS_LITE_CRS1_HPE0_SHIFT (16U) 241 #define AXBS_LITE_CRS1_HPE0_WIDTH (1U) 242 #define AXBS_LITE_CRS1_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS1_HPE0_SHIFT)) & AXBS_LITE_CRS1_HPE0_MASK) 243 244 #define AXBS_LITE_CRS1_HPE1_MASK (0x20000U) 245 #define AXBS_LITE_CRS1_HPE1_SHIFT (17U) 246 #define AXBS_LITE_CRS1_HPE1_WIDTH (1U) 247 #define AXBS_LITE_CRS1_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS1_HPE1_SHIFT)) & AXBS_LITE_CRS1_HPE1_MASK) 248 249 #define AXBS_LITE_CRS1_HPE2_MASK (0x40000U) 250 #define AXBS_LITE_CRS1_HPE2_SHIFT (18U) 251 #define AXBS_LITE_CRS1_HPE2_WIDTH (1U) 252 #define AXBS_LITE_CRS1_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS1_HPE2_SHIFT)) & AXBS_LITE_CRS1_HPE2_MASK) 253 254 #define AXBS_LITE_CRS1_HPE3_MASK (0x80000U) 255 #define AXBS_LITE_CRS1_HPE3_SHIFT (19U) 256 #define AXBS_LITE_CRS1_HPE3_WIDTH (1U) 257 #define AXBS_LITE_CRS1_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS1_HPE3_SHIFT)) & AXBS_LITE_CRS1_HPE3_MASK) 258 259 #define AXBS_LITE_CRS1_HLP_MASK (0x40000000U) 260 #define AXBS_LITE_CRS1_HLP_SHIFT (30U) 261 #define AXBS_LITE_CRS1_HLP_WIDTH (1U) 262 #define AXBS_LITE_CRS1_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS1_HLP_SHIFT)) & AXBS_LITE_CRS1_HLP_MASK) 263 264 #define AXBS_LITE_CRS1_RO_MASK (0x80000000U) 265 #define AXBS_LITE_CRS1_RO_SHIFT (31U) 266 #define AXBS_LITE_CRS1_RO_WIDTH (1U) 267 #define AXBS_LITE_CRS1_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS1_RO_SHIFT)) & AXBS_LITE_CRS1_RO_MASK) 268 /*! @} */ 269 270 /*! @name PRS2 - Priority Slave Registers */ 271 /*! @{ */ 272 273 #define AXBS_LITE_PRS2_M0_MASK (0x7U) 274 #define AXBS_LITE_PRS2_M0_SHIFT (0U) 275 #define AXBS_LITE_PRS2_M0_WIDTH (3U) 276 #define AXBS_LITE_PRS2_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS2_M0_SHIFT)) & AXBS_LITE_PRS2_M0_MASK) 277 278 #define AXBS_LITE_PRS2_M1_MASK (0x70U) 279 #define AXBS_LITE_PRS2_M1_SHIFT (4U) 280 #define AXBS_LITE_PRS2_M1_WIDTH (3U) 281 #define AXBS_LITE_PRS2_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS2_M1_SHIFT)) & AXBS_LITE_PRS2_M1_MASK) 282 283 #define AXBS_LITE_PRS2_M2_MASK (0x700U) 284 #define AXBS_LITE_PRS2_M2_SHIFT (8U) 285 #define AXBS_LITE_PRS2_M2_WIDTH (3U) 286 #define AXBS_LITE_PRS2_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS2_M2_SHIFT)) & AXBS_LITE_PRS2_M2_MASK) 287 288 #define AXBS_LITE_PRS2_M3_MASK (0x7000U) 289 #define AXBS_LITE_PRS2_M3_SHIFT (12U) 290 #define AXBS_LITE_PRS2_M3_WIDTH (3U) 291 #define AXBS_LITE_PRS2_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS2_M3_SHIFT)) & AXBS_LITE_PRS2_M3_MASK) 292 /*! @} */ 293 294 /*! @name CRS2 - Control Register */ 295 /*! @{ */ 296 297 #define AXBS_LITE_CRS2_PARK_MASK (0x7U) 298 #define AXBS_LITE_CRS2_PARK_SHIFT (0U) 299 #define AXBS_LITE_CRS2_PARK_WIDTH (3U) 300 #define AXBS_LITE_CRS2_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS2_PARK_SHIFT)) & AXBS_LITE_CRS2_PARK_MASK) 301 302 #define AXBS_LITE_CRS2_PCTL_MASK (0x30U) 303 #define AXBS_LITE_CRS2_PCTL_SHIFT (4U) 304 #define AXBS_LITE_CRS2_PCTL_WIDTH (2U) 305 #define AXBS_LITE_CRS2_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS2_PCTL_SHIFT)) & AXBS_LITE_CRS2_PCTL_MASK) 306 307 #define AXBS_LITE_CRS2_ARB_MASK (0x300U) 308 #define AXBS_LITE_CRS2_ARB_SHIFT (8U) 309 #define AXBS_LITE_CRS2_ARB_WIDTH (2U) 310 #define AXBS_LITE_CRS2_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS2_ARB_SHIFT)) & AXBS_LITE_CRS2_ARB_MASK) 311 312 #define AXBS_LITE_CRS2_HPE0_MASK (0x10000U) 313 #define AXBS_LITE_CRS2_HPE0_SHIFT (16U) 314 #define AXBS_LITE_CRS2_HPE0_WIDTH (1U) 315 #define AXBS_LITE_CRS2_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS2_HPE0_SHIFT)) & AXBS_LITE_CRS2_HPE0_MASK) 316 317 #define AXBS_LITE_CRS2_HPE1_MASK (0x20000U) 318 #define AXBS_LITE_CRS2_HPE1_SHIFT (17U) 319 #define AXBS_LITE_CRS2_HPE1_WIDTH (1U) 320 #define AXBS_LITE_CRS2_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS2_HPE1_SHIFT)) & AXBS_LITE_CRS2_HPE1_MASK) 321 322 #define AXBS_LITE_CRS2_HPE2_MASK (0x40000U) 323 #define AXBS_LITE_CRS2_HPE2_SHIFT (18U) 324 #define AXBS_LITE_CRS2_HPE2_WIDTH (1U) 325 #define AXBS_LITE_CRS2_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS2_HPE2_SHIFT)) & AXBS_LITE_CRS2_HPE2_MASK) 326 327 #define AXBS_LITE_CRS2_HPE3_MASK (0x80000U) 328 #define AXBS_LITE_CRS2_HPE3_SHIFT (19U) 329 #define AXBS_LITE_CRS2_HPE3_WIDTH (1U) 330 #define AXBS_LITE_CRS2_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS2_HPE3_SHIFT)) & AXBS_LITE_CRS2_HPE3_MASK) 331 332 #define AXBS_LITE_CRS2_HLP_MASK (0x40000000U) 333 #define AXBS_LITE_CRS2_HLP_SHIFT (30U) 334 #define AXBS_LITE_CRS2_HLP_WIDTH (1U) 335 #define AXBS_LITE_CRS2_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS2_HLP_SHIFT)) & AXBS_LITE_CRS2_HLP_MASK) 336 337 #define AXBS_LITE_CRS2_RO_MASK (0x80000000U) 338 #define AXBS_LITE_CRS2_RO_SHIFT (31U) 339 #define AXBS_LITE_CRS2_RO_WIDTH (1U) 340 #define AXBS_LITE_CRS2_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS2_RO_SHIFT)) & AXBS_LITE_CRS2_RO_MASK) 341 /*! @} */ 342 343 /*! @name PRS3 - Priority Slave Registers */ 344 /*! @{ */ 345 346 #define AXBS_LITE_PRS3_M0_MASK (0x7U) 347 #define AXBS_LITE_PRS3_M0_SHIFT (0U) 348 #define AXBS_LITE_PRS3_M0_WIDTH (3U) 349 #define AXBS_LITE_PRS3_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS3_M0_SHIFT)) & AXBS_LITE_PRS3_M0_MASK) 350 351 #define AXBS_LITE_PRS3_M1_MASK (0x70U) 352 #define AXBS_LITE_PRS3_M1_SHIFT (4U) 353 #define AXBS_LITE_PRS3_M1_WIDTH (3U) 354 #define AXBS_LITE_PRS3_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS3_M1_SHIFT)) & AXBS_LITE_PRS3_M1_MASK) 355 356 #define AXBS_LITE_PRS3_M2_MASK (0x700U) 357 #define AXBS_LITE_PRS3_M2_SHIFT (8U) 358 #define AXBS_LITE_PRS3_M2_WIDTH (3U) 359 #define AXBS_LITE_PRS3_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS3_M2_SHIFT)) & AXBS_LITE_PRS3_M2_MASK) 360 361 #define AXBS_LITE_PRS3_M3_MASK (0x7000U) 362 #define AXBS_LITE_PRS3_M3_SHIFT (12U) 363 #define AXBS_LITE_PRS3_M3_WIDTH (3U) 364 #define AXBS_LITE_PRS3_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS3_M3_SHIFT)) & AXBS_LITE_PRS3_M3_MASK) 365 /*! @} */ 366 367 /*! @name CRS3 - Control Register */ 368 /*! @{ */ 369 370 #define AXBS_LITE_CRS3_PARK_MASK (0x7U) 371 #define AXBS_LITE_CRS3_PARK_SHIFT (0U) 372 #define AXBS_LITE_CRS3_PARK_WIDTH (3U) 373 #define AXBS_LITE_CRS3_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS3_PARK_SHIFT)) & AXBS_LITE_CRS3_PARK_MASK) 374 375 #define AXBS_LITE_CRS3_PCTL_MASK (0x30U) 376 #define AXBS_LITE_CRS3_PCTL_SHIFT (4U) 377 #define AXBS_LITE_CRS3_PCTL_WIDTH (2U) 378 #define AXBS_LITE_CRS3_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS3_PCTL_SHIFT)) & AXBS_LITE_CRS3_PCTL_MASK) 379 380 #define AXBS_LITE_CRS3_ARB_MASK (0x300U) 381 #define AXBS_LITE_CRS3_ARB_SHIFT (8U) 382 #define AXBS_LITE_CRS3_ARB_WIDTH (2U) 383 #define AXBS_LITE_CRS3_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS3_ARB_SHIFT)) & AXBS_LITE_CRS3_ARB_MASK) 384 385 #define AXBS_LITE_CRS3_HPE0_MASK (0x10000U) 386 #define AXBS_LITE_CRS3_HPE0_SHIFT (16U) 387 #define AXBS_LITE_CRS3_HPE0_WIDTH (1U) 388 #define AXBS_LITE_CRS3_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS3_HPE0_SHIFT)) & AXBS_LITE_CRS3_HPE0_MASK) 389 390 #define AXBS_LITE_CRS3_HPE1_MASK (0x20000U) 391 #define AXBS_LITE_CRS3_HPE1_SHIFT (17U) 392 #define AXBS_LITE_CRS3_HPE1_WIDTH (1U) 393 #define AXBS_LITE_CRS3_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS3_HPE1_SHIFT)) & AXBS_LITE_CRS3_HPE1_MASK) 394 395 #define AXBS_LITE_CRS3_HPE2_MASK (0x40000U) 396 #define AXBS_LITE_CRS3_HPE2_SHIFT (18U) 397 #define AXBS_LITE_CRS3_HPE2_WIDTH (1U) 398 #define AXBS_LITE_CRS3_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS3_HPE2_SHIFT)) & AXBS_LITE_CRS3_HPE2_MASK) 399 400 #define AXBS_LITE_CRS3_HPE3_MASK (0x80000U) 401 #define AXBS_LITE_CRS3_HPE3_SHIFT (19U) 402 #define AXBS_LITE_CRS3_HPE3_WIDTH (1U) 403 #define AXBS_LITE_CRS3_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS3_HPE3_SHIFT)) & AXBS_LITE_CRS3_HPE3_MASK) 404 405 #define AXBS_LITE_CRS3_HLP_MASK (0x40000000U) 406 #define AXBS_LITE_CRS3_HLP_SHIFT (30U) 407 #define AXBS_LITE_CRS3_HLP_WIDTH (1U) 408 #define AXBS_LITE_CRS3_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS3_HLP_SHIFT)) & AXBS_LITE_CRS3_HLP_MASK) 409 410 #define AXBS_LITE_CRS3_RO_MASK (0x80000000U) 411 #define AXBS_LITE_CRS3_RO_SHIFT (31U) 412 #define AXBS_LITE_CRS3_RO_WIDTH (1U) 413 #define AXBS_LITE_CRS3_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS3_RO_SHIFT)) & AXBS_LITE_CRS3_RO_MASK) 414 /*! @} */ 415 416 /*! @name PRS4 - Priority Slave Registers */ 417 /*! @{ */ 418 419 #define AXBS_LITE_PRS4_M0_MASK (0x7U) 420 #define AXBS_LITE_PRS4_M0_SHIFT (0U) 421 #define AXBS_LITE_PRS4_M0_WIDTH (3U) 422 #define AXBS_LITE_PRS4_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS4_M0_SHIFT)) & AXBS_LITE_PRS4_M0_MASK) 423 424 #define AXBS_LITE_PRS4_M1_MASK (0x70U) 425 #define AXBS_LITE_PRS4_M1_SHIFT (4U) 426 #define AXBS_LITE_PRS4_M1_WIDTH (3U) 427 #define AXBS_LITE_PRS4_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS4_M1_SHIFT)) & AXBS_LITE_PRS4_M1_MASK) 428 429 #define AXBS_LITE_PRS4_M2_MASK (0x700U) 430 #define AXBS_LITE_PRS4_M2_SHIFT (8U) 431 #define AXBS_LITE_PRS4_M2_WIDTH (3U) 432 #define AXBS_LITE_PRS4_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS4_M2_SHIFT)) & AXBS_LITE_PRS4_M2_MASK) 433 434 #define AXBS_LITE_PRS4_M3_MASK (0x7000U) 435 #define AXBS_LITE_PRS4_M3_SHIFT (12U) 436 #define AXBS_LITE_PRS4_M3_WIDTH (3U) 437 #define AXBS_LITE_PRS4_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS4_M3_SHIFT)) & AXBS_LITE_PRS4_M3_MASK) 438 /*! @} */ 439 440 /*! @name CRS4 - Control Register */ 441 /*! @{ */ 442 443 #define AXBS_LITE_CRS4_PARK_MASK (0x7U) 444 #define AXBS_LITE_CRS4_PARK_SHIFT (0U) 445 #define AXBS_LITE_CRS4_PARK_WIDTH (3U) 446 #define AXBS_LITE_CRS4_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS4_PARK_SHIFT)) & AXBS_LITE_CRS4_PARK_MASK) 447 448 #define AXBS_LITE_CRS4_PCTL_MASK (0x30U) 449 #define AXBS_LITE_CRS4_PCTL_SHIFT (4U) 450 #define AXBS_LITE_CRS4_PCTL_WIDTH (2U) 451 #define AXBS_LITE_CRS4_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS4_PCTL_SHIFT)) & AXBS_LITE_CRS4_PCTL_MASK) 452 453 #define AXBS_LITE_CRS4_ARB_MASK (0x300U) 454 #define AXBS_LITE_CRS4_ARB_SHIFT (8U) 455 #define AXBS_LITE_CRS4_ARB_WIDTH (2U) 456 #define AXBS_LITE_CRS4_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS4_ARB_SHIFT)) & AXBS_LITE_CRS4_ARB_MASK) 457 458 #define AXBS_LITE_CRS4_HPE0_MASK (0x10000U) 459 #define AXBS_LITE_CRS4_HPE0_SHIFT (16U) 460 #define AXBS_LITE_CRS4_HPE0_WIDTH (1U) 461 #define AXBS_LITE_CRS4_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS4_HPE0_SHIFT)) & AXBS_LITE_CRS4_HPE0_MASK) 462 463 #define AXBS_LITE_CRS4_HPE1_MASK (0x20000U) 464 #define AXBS_LITE_CRS4_HPE1_SHIFT (17U) 465 #define AXBS_LITE_CRS4_HPE1_WIDTH (1U) 466 #define AXBS_LITE_CRS4_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS4_HPE1_SHIFT)) & AXBS_LITE_CRS4_HPE1_MASK) 467 468 #define AXBS_LITE_CRS4_HPE2_MASK (0x40000U) 469 #define AXBS_LITE_CRS4_HPE2_SHIFT (18U) 470 #define AXBS_LITE_CRS4_HPE2_WIDTH (1U) 471 #define AXBS_LITE_CRS4_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS4_HPE2_SHIFT)) & AXBS_LITE_CRS4_HPE2_MASK) 472 473 #define AXBS_LITE_CRS4_HPE3_MASK (0x80000U) 474 #define AXBS_LITE_CRS4_HPE3_SHIFT (19U) 475 #define AXBS_LITE_CRS4_HPE3_WIDTH (1U) 476 #define AXBS_LITE_CRS4_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS4_HPE3_SHIFT)) & AXBS_LITE_CRS4_HPE3_MASK) 477 478 #define AXBS_LITE_CRS4_HLP_MASK (0x40000000U) 479 #define AXBS_LITE_CRS4_HLP_SHIFT (30U) 480 #define AXBS_LITE_CRS4_HLP_WIDTH (1U) 481 #define AXBS_LITE_CRS4_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS4_HLP_SHIFT)) & AXBS_LITE_CRS4_HLP_MASK) 482 483 #define AXBS_LITE_CRS4_RO_MASK (0x80000000U) 484 #define AXBS_LITE_CRS4_RO_SHIFT (31U) 485 #define AXBS_LITE_CRS4_RO_WIDTH (1U) 486 #define AXBS_LITE_CRS4_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS4_RO_SHIFT)) & AXBS_LITE_CRS4_RO_MASK) 487 /*! @} */ 488 489 /*! @name PRS5 - Priority Slave Registers */ 490 /*! @{ */ 491 492 #define AXBS_LITE_PRS5_M0_MASK (0x7U) 493 #define AXBS_LITE_PRS5_M0_SHIFT (0U) 494 #define AXBS_LITE_PRS5_M0_WIDTH (3U) 495 #define AXBS_LITE_PRS5_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS5_M0_SHIFT)) & AXBS_LITE_PRS5_M0_MASK) 496 497 #define AXBS_LITE_PRS5_M1_MASK (0x70U) 498 #define AXBS_LITE_PRS5_M1_SHIFT (4U) 499 #define AXBS_LITE_PRS5_M1_WIDTH (3U) 500 #define AXBS_LITE_PRS5_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS5_M1_SHIFT)) & AXBS_LITE_PRS5_M1_MASK) 501 502 #define AXBS_LITE_PRS5_M2_MASK (0x700U) 503 #define AXBS_LITE_PRS5_M2_SHIFT (8U) 504 #define AXBS_LITE_PRS5_M2_WIDTH (3U) 505 #define AXBS_LITE_PRS5_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS5_M2_SHIFT)) & AXBS_LITE_PRS5_M2_MASK) 506 507 #define AXBS_LITE_PRS5_M3_MASK (0x7000U) 508 #define AXBS_LITE_PRS5_M3_SHIFT (12U) 509 #define AXBS_LITE_PRS5_M3_WIDTH (3U) 510 #define AXBS_LITE_PRS5_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS5_M3_SHIFT)) & AXBS_LITE_PRS5_M3_MASK) 511 /*! @} */ 512 513 /*! @name CRS5 - Control Register */ 514 /*! @{ */ 515 516 #define AXBS_LITE_CRS5_PARK_MASK (0x7U) 517 #define AXBS_LITE_CRS5_PARK_SHIFT (0U) 518 #define AXBS_LITE_CRS5_PARK_WIDTH (3U) 519 #define AXBS_LITE_CRS5_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS5_PARK_SHIFT)) & AXBS_LITE_CRS5_PARK_MASK) 520 521 #define AXBS_LITE_CRS5_PCTL_MASK (0x30U) 522 #define AXBS_LITE_CRS5_PCTL_SHIFT (4U) 523 #define AXBS_LITE_CRS5_PCTL_WIDTH (2U) 524 #define AXBS_LITE_CRS5_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS5_PCTL_SHIFT)) & AXBS_LITE_CRS5_PCTL_MASK) 525 526 #define AXBS_LITE_CRS5_ARB_MASK (0x300U) 527 #define AXBS_LITE_CRS5_ARB_SHIFT (8U) 528 #define AXBS_LITE_CRS5_ARB_WIDTH (2U) 529 #define AXBS_LITE_CRS5_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS5_ARB_SHIFT)) & AXBS_LITE_CRS5_ARB_MASK) 530 531 #define AXBS_LITE_CRS5_HPE0_MASK (0x10000U) 532 #define AXBS_LITE_CRS5_HPE0_SHIFT (16U) 533 #define AXBS_LITE_CRS5_HPE0_WIDTH (1U) 534 #define AXBS_LITE_CRS5_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS5_HPE0_SHIFT)) & AXBS_LITE_CRS5_HPE0_MASK) 535 536 #define AXBS_LITE_CRS5_HPE1_MASK (0x20000U) 537 #define AXBS_LITE_CRS5_HPE1_SHIFT (17U) 538 #define AXBS_LITE_CRS5_HPE1_WIDTH (1U) 539 #define AXBS_LITE_CRS5_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS5_HPE1_SHIFT)) & AXBS_LITE_CRS5_HPE1_MASK) 540 541 #define AXBS_LITE_CRS5_HPE2_MASK (0x40000U) 542 #define AXBS_LITE_CRS5_HPE2_SHIFT (18U) 543 #define AXBS_LITE_CRS5_HPE2_WIDTH (1U) 544 #define AXBS_LITE_CRS5_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS5_HPE2_SHIFT)) & AXBS_LITE_CRS5_HPE2_MASK) 545 546 #define AXBS_LITE_CRS5_HPE3_MASK (0x80000U) 547 #define AXBS_LITE_CRS5_HPE3_SHIFT (19U) 548 #define AXBS_LITE_CRS5_HPE3_WIDTH (1U) 549 #define AXBS_LITE_CRS5_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS5_HPE3_SHIFT)) & AXBS_LITE_CRS5_HPE3_MASK) 550 551 #define AXBS_LITE_CRS5_HLP_MASK (0x40000000U) 552 #define AXBS_LITE_CRS5_HLP_SHIFT (30U) 553 #define AXBS_LITE_CRS5_HLP_WIDTH (1U) 554 #define AXBS_LITE_CRS5_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS5_HLP_SHIFT)) & AXBS_LITE_CRS5_HLP_MASK) 555 556 #define AXBS_LITE_CRS5_RO_MASK (0x80000000U) 557 #define AXBS_LITE_CRS5_RO_SHIFT (31U) 558 #define AXBS_LITE_CRS5_RO_WIDTH (1U) 559 #define AXBS_LITE_CRS5_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS5_RO_SHIFT)) & AXBS_LITE_CRS5_RO_MASK) 560 /*! @} */ 561 562 /*! @name PRS6 - Priority Slave Registers */ 563 /*! @{ */ 564 565 #define AXBS_LITE_PRS6_M0_MASK (0x7U) 566 #define AXBS_LITE_PRS6_M0_SHIFT (0U) 567 #define AXBS_LITE_PRS6_M0_WIDTH (3U) 568 #define AXBS_LITE_PRS6_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS6_M0_SHIFT)) & AXBS_LITE_PRS6_M0_MASK) 569 570 #define AXBS_LITE_PRS6_M1_MASK (0x70U) 571 #define AXBS_LITE_PRS6_M1_SHIFT (4U) 572 #define AXBS_LITE_PRS6_M1_WIDTH (3U) 573 #define AXBS_LITE_PRS6_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS6_M1_SHIFT)) & AXBS_LITE_PRS6_M1_MASK) 574 575 #define AXBS_LITE_PRS6_M2_MASK (0x700U) 576 #define AXBS_LITE_PRS6_M2_SHIFT (8U) 577 #define AXBS_LITE_PRS6_M2_WIDTH (3U) 578 #define AXBS_LITE_PRS6_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS6_M2_SHIFT)) & AXBS_LITE_PRS6_M2_MASK) 579 580 #define AXBS_LITE_PRS6_M3_MASK (0x7000U) 581 #define AXBS_LITE_PRS6_M3_SHIFT (12U) 582 #define AXBS_LITE_PRS6_M3_WIDTH (3U) 583 #define AXBS_LITE_PRS6_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_PRS6_M3_SHIFT)) & AXBS_LITE_PRS6_M3_MASK) 584 /*! @} */ 585 586 /*! @name CRS6 - Control Register */ 587 /*! @{ */ 588 589 #define AXBS_LITE_CRS6_PARK_MASK (0x7U) 590 #define AXBS_LITE_CRS6_PARK_SHIFT (0U) 591 #define AXBS_LITE_CRS6_PARK_WIDTH (3U) 592 #define AXBS_LITE_CRS6_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS6_PARK_SHIFT)) & AXBS_LITE_CRS6_PARK_MASK) 593 594 #define AXBS_LITE_CRS6_PCTL_MASK (0x30U) 595 #define AXBS_LITE_CRS6_PCTL_SHIFT (4U) 596 #define AXBS_LITE_CRS6_PCTL_WIDTH (2U) 597 #define AXBS_LITE_CRS6_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS6_PCTL_SHIFT)) & AXBS_LITE_CRS6_PCTL_MASK) 598 599 #define AXBS_LITE_CRS6_ARB_MASK (0x300U) 600 #define AXBS_LITE_CRS6_ARB_SHIFT (8U) 601 #define AXBS_LITE_CRS6_ARB_WIDTH (2U) 602 #define AXBS_LITE_CRS6_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS6_ARB_SHIFT)) & AXBS_LITE_CRS6_ARB_MASK) 603 604 #define AXBS_LITE_CRS6_HPE0_MASK (0x10000U) 605 #define AXBS_LITE_CRS6_HPE0_SHIFT (16U) 606 #define AXBS_LITE_CRS6_HPE0_WIDTH (1U) 607 #define AXBS_LITE_CRS6_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS6_HPE0_SHIFT)) & AXBS_LITE_CRS6_HPE0_MASK) 608 609 #define AXBS_LITE_CRS6_HPE1_MASK (0x20000U) 610 #define AXBS_LITE_CRS6_HPE1_SHIFT (17U) 611 #define AXBS_LITE_CRS6_HPE1_WIDTH (1U) 612 #define AXBS_LITE_CRS6_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS6_HPE1_SHIFT)) & AXBS_LITE_CRS6_HPE1_MASK) 613 614 #define AXBS_LITE_CRS6_HPE2_MASK (0x40000U) 615 #define AXBS_LITE_CRS6_HPE2_SHIFT (18U) 616 #define AXBS_LITE_CRS6_HPE2_WIDTH (1U) 617 #define AXBS_LITE_CRS6_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS6_HPE2_SHIFT)) & AXBS_LITE_CRS6_HPE2_MASK) 618 619 #define AXBS_LITE_CRS6_HPE3_MASK (0x80000U) 620 #define AXBS_LITE_CRS6_HPE3_SHIFT (19U) 621 #define AXBS_LITE_CRS6_HPE3_WIDTH (1U) 622 #define AXBS_LITE_CRS6_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS6_HPE3_SHIFT)) & AXBS_LITE_CRS6_HPE3_MASK) 623 624 #define AXBS_LITE_CRS6_HLP_MASK (0x40000000U) 625 #define AXBS_LITE_CRS6_HLP_SHIFT (30U) 626 #define AXBS_LITE_CRS6_HLP_WIDTH (1U) 627 #define AXBS_LITE_CRS6_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS6_HLP_SHIFT)) & AXBS_LITE_CRS6_HLP_MASK) 628 629 #define AXBS_LITE_CRS6_RO_MASK (0x80000000U) 630 #define AXBS_LITE_CRS6_RO_SHIFT (31U) 631 #define AXBS_LITE_CRS6_RO_WIDTH (1U) 632 #define AXBS_LITE_CRS6_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_LITE_CRS6_RO_SHIFT)) & AXBS_LITE_CRS6_RO_MASK) 633 /*! @} */ 634 635 /*! 636 * @} 637 */ /* end of group AXBS_LITE_Register_Masks */ 638 639 /*! 640 * @} 641 */ /* end of group AXBS_LITE_Peripheral_Access_Layer */ 642 643 #endif /* #if !defined(S32K344_AXBS_LITE_H_) */ 644
