1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K148_SCB.h 10 * @version 1.0 11 * @date 2021-02-18 12 * @brief Peripheral Access Layer for S32K148_SCB 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K148_SCB_H_) /* Check if memory map has not been already included */ 58 #define S32K148_SCB_H_ 59 60 #include "S32K148_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- S32_SCB Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup S32_SCB_Peripheral_Access_Layer S32_SCB Peripheral Access Layer 68 * @{ 69 */ 70 71 72 /** S32_SCB - Size of Registers Arrays */ 73 74 /** S32_SCB - Register Layout Typedef */ 75 typedef struct { 76 uint8_t RESERVED_0[8]; 77 __IO uint32_t ACTLR; /**< Auxiliary Control Register,, offset: 0x8 */ 78 uint8_t RESERVED_1[3316]; 79 __I uint32_t CPUID; /**< CPUID Base Register, offset: 0xD00 */ 80 __IO uint32_t ICSR; /**< Interrupt Control and State Register, offset: 0xD04 */ 81 __IO uint32_t VTOR; /**< Vector Table Offset Register, offset: 0xD08 */ 82 __IO uint32_t AIRCR; /**< Application Interrupt and Reset Control Register, offset: 0xD0C */ 83 __IO uint32_t SCR; /**< System Control Register, offset: 0xD10 */ 84 __IO uint32_t CCR; /**< Configuration and Control Register, offset: 0xD14 */ 85 __IO uint32_t SHPR1; /**< System Handler Priority Register 1, offset: 0xD18 */ 86 __IO uint32_t SHPR2; /**< System Handler Priority Register 2, offset: 0xD1C */ 87 __IO uint32_t SHPR3; /**< System Handler Priority Register 3, offset: 0xD20 */ 88 __IO uint32_t SHCSR; /**< System Handler Control and State Register, offset: 0xD24 */ 89 __IO uint32_t CFSR; /**< Configurable Fault Status Registers, offset: 0xD28 */ 90 __IO uint32_t HFSR; /**< HardFault Status register, offset: 0xD2C */ 91 __IO uint32_t DFSR; /**< Debug Fault Status Register, offset: 0xD30 */ 92 __IO uint32_t MMFAR; /**< MemManage Address Register, offset: 0xD34 */ 93 __IO uint32_t BFAR; /**< BusFault Address Register, offset: 0xD38 */ 94 __IO uint32_t AFSR; /**< Auxiliary Fault Status Register, offset: 0xD3C */ 95 uint8_t RESERVED_2[72]; 96 __IO uint32_t CPACR; /**< Coprocessor Access Control Register, offset: 0xD88 */ 97 uint8_t RESERVED_3[424]; 98 __IO uint32_t FPCCR; /**< Floating-point Context Control Register, offset: 0xF34 */ 99 __IO uint32_t FPCAR; /**< Floating-point Context Address Register, offset: 0xF38 */ 100 __IO uint32_t FPDSCR; /**< Floating-point Default Status Control Register, offset: 0xF3C */ 101 } S32_SCB_Type, *S32_SCB_MemMapPtr; 102 103 /** Number of instances of the S32_SCB module. */ 104 #define S32_SCB_INSTANCE_COUNT (1u) 105 106 107 /* S32_SCB - Peripheral instance base addresses */ 108 /** Peripheral S32_SCB base address */ 109 #define S32_SCB_BASE (0xE000E000u) 110 /** Peripheral S32_SCB base pointer */ 111 #define S32_SCB ((S32_SCB_Type *)S32_SCB_BASE) 112 /** Array initializer of S32_SCB peripheral base addresses */ 113 #define S32_SCB_BASE_ADDRS { S32_SCB_BASE } 114 /** Array initializer of S32_SCB peripheral base pointers */ 115 #define S32_SCB_BASE_PTRS { S32_SCB } 116 117 /* ---------------------------------------------------------------------------- 118 -- S32_SCB Register Masks 119 ---------------------------------------------------------------------------- */ 120 121 /*! 122 * @addtogroup S32_SCB_Register_Masks S32_SCB Register Masks 123 * @{ 124 */ 125 126 /* ACTLR Bit Fields */ 127 #define S32_SCB_ACTLR_DISMCYCINT_MASK 0x1u 128 #define S32_SCB_ACTLR_DISMCYCINT_SHIFT 0u 129 #define S32_SCB_ACTLR_DISMCYCINT_WIDTH 1u 130 #define S32_SCB_ACTLR_DISMCYCINT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISMCYCINT_SHIFT))&S32_SCB_ACTLR_DISMCYCINT_MASK) 131 #define S32_SCB_ACTLR_DISDEFWBUF_MASK 0x2u 132 #define S32_SCB_ACTLR_DISDEFWBUF_SHIFT 1u 133 #define S32_SCB_ACTLR_DISDEFWBUF_WIDTH 1u 134 #define S32_SCB_ACTLR_DISDEFWBUF(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISDEFWBUF_SHIFT))&S32_SCB_ACTLR_DISDEFWBUF_MASK) 135 #define S32_SCB_ACTLR_DISFOLD_MASK 0x4u 136 #define S32_SCB_ACTLR_DISFOLD_SHIFT 2u 137 #define S32_SCB_ACTLR_DISFOLD_WIDTH 1u 138 #define S32_SCB_ACTLR_DISFOLD(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISFOLD_SHIFT))&S32_SCB_ACTLR_DISFOLD_MASK) 139 #define S32_SCB_ACTLR_DISFPCA_MASK 0x100u 140 #define S32_SCB_ACTLR_DISFPCA_SHIFT 8u 141 #define S32_SCB_ACTLR_DISFPCA_WIDTH 1u 142 #define S32_SCB_ACTLR_DISFPCA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISFPCA_SHIFT))&S32_SCB_ACTLR_DISFPCA_MASK) 143 #define S32_SCB_ACTLR_DISOOFP_MASK 0x200u 144 #define S32_SCB_ACTLR_DISOOFP_SHIFT 9u 145 #define S32_SCB_ACTLR_DISOOFP_WIDTH 1u 146 #define S32_SCB_ACTLR_DISOOFP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISOOFP_SHIFT))&S32_SCB_ACTLR_DISOOFP_MASK) 147 /* CPUID Bit Fields */ 148 #define S32_SCB_CPUID_REVISION_MASK 0xFu 149 #define S32_SCB_CPUID_REVISION_SHIFT 0u 150 #define S32_SCB_CPUID_REVISION_WIDTH 4u 151 #define S32_SCB_CPUID_REVISION(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_REVISION_SHIFT))&S32_SCB_CPUID_REVISION_MASK) 152 #define S32_SCB_CPUID_PARTNO_MASK 0xFFF0u 153 #define S32_SCB_CPUID_PARTNO_SHIFT 4u 154 #define S32_SCB_CPUID_PARTNO_WIDTH 12u 155 #define S32_SCB_CPUID_PARTNO(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_PARTNO_SHIFT))&S32_SCB_CPUID_PARTNO_MASK) 156 #define S32_SCB_CPUID_VARIANT_MASK 0xF00000u 157 #define S32_SCB_CPUID_VARIANT_SHIFT 20u 158 #define S32_SCB_CPUID_VARIANT_WIDTH 4u 159 #define S32_SCB_CPUID_VARIANT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_VARIANT_SHIFT))&S32_SCB_CPUID_VARIANT_MASK) 160 #define S32_SCB_CPUID_IMPLEMENTER_MASK 0xFF000000u 161 #define S32_SCB_CPUID_IMPLEMENTER_SHIFT 24u 162 #define S32_SCB_CPUID_IMPLEMENTER_WIDTH 8u 163 #define S32_SCB_CPUID_IMPLEMENTER(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_IMPLEMENTER_SHIFT))&S32_SCB_CPUID_IMPLEMENTER_MASK) 164 /* ICSR Bit Fields */ 165 #define S32_SCB_ICSR_VECTACTIVE_MASK 0x1FFu 166 #define S32_SCB_ICSR_VECTACTIVE_SHIFT 0u 167 #define S32_SCB_ICSR_VECTACTIVE_WIDTH 9u 168 #define S32_SCB_ICSR_VECTACTIVE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_VECTACTIVE_SHIFT))&S32_SCB_ICSR_VECTACTIVE_MASK) 169 #define S32_SCB_ICSR_RETTOBASE_MASK 0x800u 170 #define S32_SCB_ICSR_RETTOBASE_SHIFT 11u 171 #define S32_SCB_ICSR_RETTOBASE_WIDTH 1u 172 #define S32_SCB_ICSR_RETTOBASE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_RETTOBASE_SHIFT))&S32_SCB_ICSR_RETTOBASE_MASK) 173 #define S32_SCB_ICSR_VECTPENDING_MASK 0x3F000u 174 #define S32_SCB_ICSR_VECTPENDING_SHIFT 12u 175 #define S32_SCB_ICSR_VECTPENDING_WIDTH 6u 176 #define S32_SCB_ICSR_VECTPENDING(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_VECTPENDING_SHIFT))&S32_SCB_ICSR_VECTPENDING_MASK) 177 #define S32_SCB_ICSR_ISRPENDING_MASK 0x400000u 178 #define S32_SCB_ICSR_ISRPENDING_SHIFT 22u 179 #define S32_SCB_ICSR_ISRPENDING_WIDTH 1u 180 #define S32_SCB_ICSR_ISRPENDING(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_ISRPENDING_SHIFT))&S32_SCB_ICSR_ISRPENDING_MASK) 181 #define S32_SCB_ICSR_ISRPREEMPT_MASK 0x800000u 182 #define S32_SCB_ICSR_ISRPREEMPT_SHIFT 23u 183 #define S32_SCB_ICSR_ISRPREEMPT_WIDTH 1u 184 #define S32_SCB_ICSR_ISRPREEMPT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_ISRPREEMPT_SHIFT))&S32_SCB_ICSR_ISRPREEMPT_MASK) 185 #define S32_SCB_ICSR_PENDSTCLR_MASK 0x2000000u 186 #define S32_SCB_ICSR_PENDSTCLR_SHIFT 25u 187 #define S32_SCB_ICSR_PENDSTCLR_WIDTH 1u 188 #define S32_SCB_ICSR_PENDSTCLR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSTCLR_SHIFT))&S32_SCB_ICSR_PENDSTCLR_MASK) 189 #define S32_SCB_ICSR_PENDSTSET_MASK 0x4000000u 190 #define S32_SCB_ICSR_PENDSTSET_SHIFT 26u 191 #define S32_SCB_ICSR_PENDSTSET_WIDTH 1u 192 #define S32_SCB_ICSR_PENDSTSET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSTSET_SHIFT))&S32_SCB_ICSR_PENDSTSET_MASK) 193 #define S32_SCB_ICSR_PENDSVCLR_MASK 0x8000000u 194 #define S32_SCB_ICSR_PENDSVCLR_SHIFT 27u 195 #define S32_SCB_ICSR_PENDSVCLR_WIDTH 1u 196 #define S32_SCB_ICSR_PENDSVCLR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSVCLR_SHIFT))&S32_SCB_ICSR_PENDSVCLR_MASK) 197 #define S32_SCB_ICSR_PENDSVSET_MASK 0x10000000u 198 #define S32_SCB_ICSR_PENDSVSET_SHIFT 28u 199 #define S32_SCB_ICSR_PENDSVSET_WIDTH 1u 200 #define S32_SCB_ICSR_PENDSVSET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSVSET_SHIFT))&S32_SCB_ICSR_PENDSVSET_MASK) 201 #define S32_SCB_ICSR_NMIPENDSET_MASK 0x80000000u 202 #define S32_SCB_ICSR_NMIPENDSET_SHIFT 31u 203 #define S32_SCB_ICSR_NMIPENDSET_WIDTH 1u 204 #define S32_SCB_ICSR_NMIPENDSET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_NMIPENDSET_SHIFT))&S32_SCB_ICSR_NMIPENDSET_MASK) 205 /* VTOR Bit Fields */ 206 #define S32_SCB_VTOR_TBLOFF_MASK 0xFFFFFF80u 207 #define S32_SCB_VTOR_TBLOFF_SHIFT 7u 208 #define S32_SCB_VTOR_TBLOFF_WIDTH 25u 209 #define S32_SCB_VTOR_TBLOFF(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_VTOR_TBLOFF_SHIFT))&S32_SCB_VTOR_TBLOFF_MASK) 210 /* AIRCR Bit Fields */ 211 #define S32_SCB_AIRCR_VECTRESET_MASK 0x1u 212 #define S32_SCB_AIRCR_VECTRESET_SHIFT 0u 213 #define S32_SCB_AIRCR_VECTRESET_WIDTH 1u 214 #define S32_SCB_AIRCR_VECTRESET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_VECTRESET_SHIFT))&S32_SCB_AIRCR_VECTRESET_MASK) 215 #define S32_SCB_AIRCR_VECTCLRACTIVE_MASK 0x2u 216 #define S32_SCB_AIRCR_VECTCLRACTIVE_SHIFT 1u 217 #define S32_SCB_AIRCR_VECTCLRACTIVE_WIDTH 1u 218 #define S32_SCB_AIRCR_VECTCLRACTIVE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_VECTCLRACTIVE_SHIFT))&S32_SCB_AIRCR_VECTCLRACTIVE_MASK) 219 #define S32_SCB_AIRCR_SYSRESETREQ_MASK 0x4u 220 #define S32_SCB_AIRCR_SYSRESETREQ_SHIFT 2u 221 #define S32_SCB_AIRCR_SYSRESETREQ_WIDTH 1u 222 #define S32_SCB_AIRCR_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_SYSRESETREQ_SHIFT))&S32_SCB_AIRCR_SYSRESETREQ_MASK) 223 #define S32_SCB_AIRCR_PRIGROUP_MASK 0x700u 224 #define S32_SCB_AIRCR_PRIGROUP_SHIFT 8u 225 #define S32_SCB_AIRCR_PRIGROUP_WIDTH 3u 226 #define S32_SCB_AIRCR_PRIGROUP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_PRIGROUP_SHIFT))&S32_SCB_AIRCR_PRIGROUP_MASK) 227 #define S32_SCB_AIRCR_ENDIANNESS_MASK 0x8000u 228 #define S32_SCB_AIRCR_ENDIANNESS_SHIFT 15u 229 #define S32_SCB_AIRCR_ENDIANNESS_WIDTH 1u 230 #define S32_SCB_AIRCR_ENDIANNESS(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_ENDIANNESS_SHIFT))&S32_SCB_AIRCR_ENDIANNESS_MASK) 231 #define S32_SCB_AIRCR_VECTKEY_MASK 0xFFFF0000u 232 #define S32_SCB_AIRCR_VECTKEY_SHIFT 16u 233 #define S32_SCB_AIRCR_VECTKEY_WIDTH 16u 234 #define S32_SCB_AIRCR_VECTKEY(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_VECTKEY_SHIFT))&S32_SCB_AIRCR_VECTKEY_MASK) 235 /* SCR Bit Fields */ 236 #define S32_SCB_SCR_SLEEPONEXIT_MASK 0x2u 237 #define S32_SCB_SCR_SLEEPONEXIT_SHIFT 1u 238 #define S32_SCB_SCR_SLEEPONEXIT_WIDTH 1u 239 #define S32_SCB_SCR_SLEEPONEXIT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SLEEPONEXIT_SHIFT))&S32_SCB_SCR_SLEEPONEXIT_MASK) 240 #define S32_SCB_SCR_SLEEPDEEP_MASK 0x4u 241 #define S32_SCB_SCR_SLEEPDEEP_SHIFT 2u 242 #define S32_SCB_SCR_SLEEPDEEP_WIDTH 1u 243 #define S32_SCB_SCR_SLEEPDEEP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SLEEPDEEP_SHIFT))&S32_SCB_SCR_SLEEPDEEP_MASK) 244 #define S32_SCB_SCR_SEVONPEND_MASK 0x10u 245 #define S32_SCB_SCR_SEVONPEND_SHIFT 4u 246 #define S32_SCB_SCR_SEVONPEND_WIDTH 1u 247 #define S32_SCB_SCR_SEVONPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SEVONPEND_SHIFT))&S32_SCB_SCR_SEVONPEND_MASK) 248 /* CCR Bit Fields */ 249 #define S32_SCB_CCR_NONBASETHRDENA_MASK 0x1u 250 #define S32_SCB_CCR_NONBASETHRDENA_SHIFT 0u 251 #define S32_SCB_CCR_NONBASETHRDENA_WIDTH 1u 252 #define S32_SCB_CCR_NONBASETHRDENA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_NONBASETHRDENA_SHIFT))&S32_SCB_CCR_NONBASETHRDENA_MASK) 253 #define S32_SCB_CCR_USERSETMPEND_MASK 0x2u 254 #define S32_SCB_CCR_USERSETMPEND_SHIFT 1u 255 #define S32_SCB_CCR_USERSETMPEND_WIDTH 1u 256 #define S32_SCB_CCR_USERSETMPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_USERSETMPEND_SHIFT))&S32_SCB_CCR_USERSETMPEND_MASK) 257 #define S32_SCB_CCR_UNALIGN_TRP_MASK 0x8u 258 #define S32_SCB_CCR_UNALIGN_TRP_SHIFT 3u 259 #define S32_SCB_CCR_UNALIGN_TRP_WIDTH 1u 260 #define S32_SCB_CCR_UNALIGN_TRP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_UNALIGN_TRP_SHIFT))&S32_SCB_CCR_UNALIGN_TRP_MASK) 261 #define S32_SCB_CCR_DIV_0_TRP_MASK 0x10u 262 #define S32_SCB_CCR_DIV_0_TRP_SHIFT 4u 263 #define S32_SCB_CCR_DIV_0_TRP_WIDTH 1u 264 #define S32_SCB_CCR_DIV_0_TRP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_DIV_0_TRP_SHIFT))&S32_SCB_CCR_DIV_0_TRP_MASK) 265 #define S32_SCB_CCR_BFHFNMIGN_MASK 0x100u 266 #define S32_SCB_CCR_BFHFNMIGN_SHIFT 8u 267 #define S32_SCB_CCR_BFHFNMIGN_WIDTH 1u 268 #define S32_SCB_CCR_BFHFNMIGN(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_BFHFNMIGN_SHIFT))&S32_SCB_CCR_BFHFNMIGN_MASK) 269 #define S32_SCB_CCR_STKALIGN_MASK 0x200u 270 #define S32_SCB_CCR_STKALIGN_SHIFT 9u 271 #define S32_SCB_CCR_STKALIGN_WIDTH 1u 272 #define S32_SCB_CCR_STKALIGN(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_STKALIGN_SHIFT))&S32_SCB_CCR_STKALIGN_MASK) 273 /* SHPR1 Bit Fields */ 274 #define S32_SCB_SHPR1_PRI_4_MASK 0xFFu 275 #define S32_SCB_SHPR1_PRI_4_SHIFT 0u 276 #define S32_SCB_SHPR1_PRI_4_WIDTH 8u 277 #define S32_SCB_SHPR1_PRI_4(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR1_PRI_4_SHIFT))&S32_SCB_SHPR1_PRI_4_MASK) 278 #define S32_SCB_SHPR1_PRI_5_MASK 0xFF00u 279 #define S32_SCB_SHPR1_PRI_5_SHIFT 8u 280 #define S32_SCB_SHPR1_PRI_5_WIDTH 8u 281 #define S32_SCB_SHPR1_PRI_5(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR1_PRI_5_SHIFT))&S32_SCB_SHPR1_PRI_5_MASK) 282 #define S32_SCB_SHPR1_PRI_6_MASK 0xFF0000u 283 #define S32_SCB_SHPR1_PRI_6_SHIFT 16u 284 #define S32_SCB_SHPR1_PRI_6_WIDTH 8u 285 #define S32_SCB_SHPR1_PRI_6(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR1_PRI_6_SHIFT))&S32_SCB_SHPR1_PRI_6_MASK) 286 /* SHPR2 Bit Fields */ 287 #define S32_SCB_SHPR2_PRI_11_MASK 0xFF000000u 288 #define S32_SCB_SHPR2_PRI_11_SHIFT 24u 289 #define S32_SCB_SHPR2_PRI_11_WIDTH 8u 290 #define S32_SCB_SHPR2_PRI_11(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR2_PRI_11_SHIFT))&S32_SCB_SHPR2_PRI_11_MASK) 291 /* SHPR3 Bit Fields */ 292 #define S32_SCB_SHPR3_PRI_12_MASK 0xFFu 293 #define S32_SCB_SHPR3_PRI_12_SHIFT 0u 294 #define S32_SCB_SHPR3_PRI_12_WIDTH 8u 295 #define S32_SCB_SHPR3_PRI_12(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR3_PRI_12_SHIFT))&S32_SCB_SHPR3_PRI_12_MASK) 296 #define S32_SCB_SHPR3_PRI_14_MASK 0xFF0000u 297 #define S32_SCB_SHPR3_PRI_14_SHIFT 16u 298 #define S32_SCB_SHPR3_PRI_14_WIDTH 8u 299 #define S32_SCB_SHPR3_PRI_14(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR3_PRI_14_SHIFT))&S32_SCB_SHPR3_PRI_14_MASK) 300 #define S32_SCB_SHPR3_PRI_15_MASK 0xFF000000u 301 #define S32_SCB_SHPR3_PRI_15_SHIFT 24u 302 #define S32_SCB_SHPR3_PRI_15_WIDTH 8u 303 #define S32_SCB_SHPR3_PRI_15(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR3_PRI_15_SHIFT))&S32_SCB_SHPR3_PRI_15_MASK) 304 /* SHCSR Bit Fields */ 305 #define S32_SCB_SHCSR_MEMFAULTACT_MASK 0x1u 306 #define S32_SCB_SHCSR_MEMFAULTACT_SHIFT 0u 307 #define S32_SCB_SHCSR_MEMFAULTACT_WIDTH 1u 308 #define S32_SCB_SHCSR_MEMFAULTACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MEMFAULTACT_SHIFT))&S32_SCB_SHCSR_MEMFAULTACT_MASK) 309 #define S32_SCB_SHCSR_BUSFAULTACT_MASK 0x2u 310 #define S32_SCB_SHCSR_BUSFAULTACT_SHIFT 1u 311 #define S32_SCB_SHCSR_BUSFAULTACT_WIDTH 1u 312 #define S32_SCB_SHCSR_BUSFAULTACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_BUSFAULTACT_SHIFT))&S32_SCB_SHCSR_BUSFAULTACT_MASK) 313 #define S32_SCB_SHCSR_USGFAULTACT_MASK 0x8u 314 #define S32_SCB_SHCSR_USGFAULTACT_SHIFT 3u 315 #define S32_SCB_SHCSR_USGFAULTACT_WIDTH 1u 316 #define S32_SCB_SHCSR_USGFAULTACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_USGFAULTACT_SHIFT))&S32_SCB_SHCSR_USGFAULTACT_MASK) 317 #define S32_SCB_SHCSR_SVCALLACT_MASK 0x80u 318 #define S32_SCB_SHCSR_SVCALLACT_SHIFT 7u 319 #define S32_SCB_SHCSR_SVCALLACT_WIDTH 1u 320 #define S32_SCB_SHCSR_SVCALLACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_SVCALLACT_SHIFT))&S32_SCB_SHCSR_SVCALLACT_MASK) 321 #define S32_SCB_SHCSR_MONITORACT_MASK 0x100u 322 #define S32_SCB_SHCSR_MONITORACT_SHIFT 8u 323 #define S32_SCB_SHCSR_MONITORACT_WIDTH 1u 324 #define S32_SCB_SHCSR_MONITORACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MONITORACT_SHIFT))&S32_SCB_SHCSR_MONITORACT_MASK) 325 #define S32_SCB_SHCSR_PENDSVACT_MASK 0x400u 326 #define S32_SCB_SHCSR_PENDSVACT_SHIFT 10u 327 #define S32_SCB_SHCSR_PENDSVACT_WIDTH 1u 328 #define S32_SCB_SHCSR_PENDSVACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_PENDSVACT_SHIFT))&S32_SCB_SHCSR_PENDSVACT_MASK) 329 #define S32_SCB_SHCSR_SYSTICKACT_MASK 0x800u 330 #define S32_SCB_SHCSR_SYSTICKACT_SHIFT 11u 331 #define S32_SCB_SHCSR_SYSTICKACT_WIDTH 1u 332 #define S32_SCB_SHCSR_SYSTICKACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_SYSTICKACT_SHIFT))&S32_SCB_SHCSR_SYSTICKACT_MASK) 333 #define S32_SCB_SHCSR_USGFAULTPENDED_MASK 0x1000u 334 #define S32_SCB_SHCSR_USGFAULTPENDED_SHIFT 12u 335 #define S32_SCB_SHCSR_USGFAULTPENDED_WIDTH 1u 336 #define S32_SCB_SHCSR_USGFAULTPENDED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_USGFAULTPENDED_SHIFT))&S32_SCB_SHCSR_USGFAULTPENDED_MASK) 337 #define S32_SCB_SHCSR_MEMFAULTPENDED_MASK 0x2000u 338 #define S32_SCB_SHCSR_MEMFAULTPENDED_SHIFT 13u 339 #define S32_SCB_SHCSR_MEMFAULTPENDED_WIDTH 1u 340 #define S32_SCB_SHCSR_MEMFAULTPENDED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MEMFAULTPENDED_SHIFT))&S32_SCB_SHCSR_MEMFAULTPENDED_MASK) 341 #define S32_SCB_SHCSR_BUSFAULTPENDED_MASK 0x4000u 342 #define S32_SCB_SHCSR_BUSFAULTPENDED_SHIFT 14u 343 #define S32_SCB_SHCSR_BUSFAULTPENDED_WIDTH 1u 344 #define S32_SCB_SHCSR_BUSFAULTPENDED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_BUSFAULTPENDED_SHIFT))&S32_SCB_SHCSR_BUSFAULTPENDED_MASK) 345 #define S32_SCB_SHCSR_SVCALLPENDED_MASK 0x8000u 346 #define S32_SCB_SHCSR_SVCALLPENDED_SHIFT 15u 347 #define S32_SCB_SHCSR_SVCALLPENDED_WIDTH 1u 348 #define S32_SCB_SHCSR_SVCALLPENDED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_SVCALLPENDED_SHIFT))&S32_SCB_SHCSR_SVCALLPENDED_MASK) 349 #define S32_SCB_SHCSR_MEMFAULTENA_MASK 0x10000u 350 #define S32_SCB_SHCSR_MEMFAULTENA_SHIFT 16u 351 #define S32_SCB_SHCSR_MEMFAULTENA_WIDTH 1u 352 #define S32_SCB_SHCSR_MEMFAULTENA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MEMFAULTENA_SHIFT))&S32_SCB_SHCSR_MEMFAULTENA_MASK) 353 #define S32_SCB_SHCSR_BUSFAULTENA_MASK 0x20000u 354 #define S32_SCB_SHCSR_BUSFAULTENA_SHIFT 17u 355 #define S32_SCB_SHCSR_BUSFAULTENA_WIDTH 1u 356 #define S32_SCB_SHCSR_BUSFAULTENA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_BUSFAULTENA_SHIFT))&S32_SCB_SHCSR_BUSFAULTENA_MASK) 357 #define S32_SCB_SHCSR_USGFAULTENA_MASK 0x40000u 358 #define S32_SCB_SHCSR_USGFAULTENA_SHIFT 18u 359 #define S32_SCB_SHCSR_USGFAULTENA_WIDTH 1u 360 #define S32_SCB_SHCSR_USGFAULTENA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_USGFAULTENA_SHIFT))&S32_SCB_SHCSR_USGFAULTENA_MASK) 361 /* CFSR Bit Fields */ 362 #define S32_SCB_CFSR_IACCVIOL_MASK 0x1u 363 #define S32_SCB_CFSR_IACCVIOL_SHIFT 0u 364 #define S32_SCB_CFSR_IACCVIOL_WIDTH 1u 365 #define S32_SCB_CFSR_IACCVIOL(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_IACCVIOL_SHIFT))&S32_SCB_CFSR_IACCVIOL_MASK) 366 #define S32_SCB_CFSR_DACCVIOL_MASK 0x2u 367 #define S32_SCB_CFSR_DACCVIOL_SHIFT 1u 368 #define S32_SCB_CFSR_DACCVIOL_WIDTH 1u 369 #define S32_SCB_CFSR_DACCVIOL(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_DACCVIOL_SHIFT))&S32_SCB_CFSR_DACCVIOL_MASK) 370 #define S32_SCB_CFSR_MUNSTKERR_MASK 0x8u 371 #define S32_SCB_CFSR_MUNSTKERR_SHIFT 3u 372 #define S32_SCB_CFSR_MUNSTKERR_WIDTH 1u 373 #define S32_SCB_CFSR_MUNSTKERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MUNSTKERR_SHIFT))&S32_SCB_CFSR_MUNSTKERR_MASK) 374 #define S32_SCB_CFSR_MSTKERR_MASK 0x10u 375 #define S32_SCB_CFSR_MSTKERR_SHIFT 4u 376 #define S32_SCB_CFSR_MSTKERR_WIDTH 1u 377 #define S32_SCB_CFSR_MSTKERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MSTKERR_SHIFT))&S32_SCB_CFSR_MSTKERR_MASK) 378 #define S32_SCB_CFSR_MLSPERR_MASK 0x20u 379 #define S32_SCB_CFSR_MLSPERR_SHIFT 5u 380 #define S32_SCB_CFSR_MLSPERR_WIDTH 1u 381 #define S32_SCB_CFSR_MLSPERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MLSPERR_SHIFT))&S32_SCB_CFSR_MLSPERR_MASK) 382 #define S32_SCB_CFSR_MMARVALID_MASK 0x80u 383 #define S32_SCB_CFSR_MMARVALID_SHIFT 7u 384 #define S32_SCB_CFSR_MMARVALID_WIDTH 1u 385 #define S32_SCB_CFSR_MMARVALID(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MMARVALID_SHIFT))&S32_SCB_CFSR_MMARVALID_MASK) 386 #define S32_SCB_CFSR_IBUSERR_MASK 0x100u 387 #define S32_SCB_CFSR_IBUSERR_SHIFT 8u 388 #define S32_SCB_CFSR_IBUSERR_WIDTH 1u 389 #define S32_SCB_CFSR_IBUSERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_IBUSERR_SHIFT))&S32_SCB_CFSR_IBUSERR_MASK) 390 #define S32_SCB_CFSR_PRECISERR_MASK 0x200u 391 #define S32_SCB_CFSR_PRECISERR_SHIFT 9u 392 #define S32_SCB_CFSR_PRECISERR_WIDTH 1u 393 #define S32_SCB_CFSR_PRECISERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_PRECISERR_SHIFT))&S32_SCB_CFSR_PRECISERR_MASK) 394 #define S32_SCB_CFSR_IMPRECISERR_MASK 0x400u 395 #define S32_SCB_CFSR_IMPRECISERR_SHIFT 10u 396 #define S32_SCB_CFSR_IMPRECISERR_WIDTH 1u 397 #define S32_SCB_CFSR_IMPRECISERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_IMPRECISERR_SHIFT))&S32_SCB_CFSR_IMPRECISERR_MASK) 398 #define S32_SCB_CFSR_UNSTKERR_MASK 0x800u 399 #define S32_SCB_CFSR_UNSTKERR_SHIFT 11u 400 #define S32_SCB_CFSR_UNSTKERR_WIDTH 1u 401 #define S32_SCB_CFSR_UNSTKERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_UNSTKERR_SHIFT))&S32_SCB_CFSR_UNSTKERR_MASK) 402 #define S32_SCB_CFSR_STKERR_MASK 0x1000u 403 #define S32_SCB_CFSR_STKERR_SHIFT 12u 404 #define S32_SCB_CFSR_STKERR_WIDTH 1u 405 #define S32_SCB_CFSR_STKERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_STKERR_SHIFT))&S32_SCB_CFSR_STKERR_MASK) 406 #define S32_SCB_CFSR_LSPERR_MASK 0x2000u 407 #define S32_SCB_CFSR_LSPERR_SHIFT 13u 408 #define S32_SCB_CFSR_LSPERR_WIDTH 1u 409 #define S32_SCB_CFSR_LSPERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_LSPERR_SHIFT))&S32_SCB_CFSR_LSPERR_MASK) 410 #define S32_SCB_CFSR_BFARVALID_MASK 0x8000u 411 #define S32_SCB_CFSR_BFARVALID_SHIFT 15u 412 #define S32_SCB_CFSR_BFARVALID_WIDTH 1u 413 #define S32_SCB_CFSR_BFARVALID(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_BFARVALID_SHIFT))&S32_SCB_CFSR_BFARVALID_MASK) 414 #define S32_SCB_CFSR_UNDEFINSTR_MASK 0x10000u 415 #define S32_SCB_CFSR_UNDEFINSTR_SHIFT 16u 416 #define S32_SCB_CFSR_UNDEFINSTR_WIDTH 1u 417 #define S32_SCB_CFSR_UNDEFINSTR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_UNDEFINSTR_SHIFT))&S32_SCB_CFSR_UNDEFINSTR_MASK) 418 #define S32_SCB_CFSR_INVSTATE_MASK 0x20000u 419 #define S32_SCB_CFSR_INVSTATE_SHIFT 17u 420 #define S32_SCB_CFSR_INVSTATE_WIDTH 1u 421 #define S32_SCB_CFSR_INVSTATE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_INVSTATE_SHIFT))&S32_SCB_CFSR_INVSTATE_MASK) 422 #define S32_SCB_CFSR_INVPC_MASK 0x40000u 423 #define S32_SCB_CFSR_INVPC_SHIFT 18u 424 #define S32_SCB_CFSR_INVPC_WIDTH 1u 425 #define S32_SCB_CFSR_INVPC(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_INVPC_SHIFT))&S32_SCB_CFSR_INVPC_MASK) 426 #define S32_SCB_CFSR_NOCP_MASK 0x80000u 427 #define S32_SCB_CFSR_NOCP_SHIFT 19u 428 #define S32_SCB_CFSR_NOCP_WIDTH 1u 429 #define S32_SCB_CFSR_NOCP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_NOCP_SHIFT))&S32_SCB_CFSR_NOCP_MASK) 430 #define S32_SCB_CFSR_UNALIGNED_MASK 0x1000000u 431 #define S32_SCB_CFSR_UNALIGNED_SHIFT 24u 432 #define S32_SCB_CFSR_UNALIGNED_WIDTH 1u 433 #define S32_SCB_CFSR_UNALIGNED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_UNALIGNED_SHIFT))&S32_SCB_CFSR_UNALIGNED_MASK) 434 #define S32_SCB_CFSR_DIVBYZERO_MASK 0x2000000u 435 #define S32_SCB_CFSR_DIVBYZERO_SHIFT 25u 436 #define S32_SCB_CFSR_DIVBYZERO_WIDTH 1u 437 #define S32_SCB_CFSR_DIVBYZERO(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_DIVBYZERO_SHIFT))&S32_SCB_CFSR_DIVBYZERO_MASK) 438 /* HFSR Bit Fields */ 439 #define S32_SCB_HFSR_VECTTBL_MASK 0x2u 440 #define S32_SCB_HFSR_VECTTBL_SHIFT 1u 441 #define S32_SCB_HFSR_VECTTBL_WIDTH 1u 442 #define S32_SCB_HFSR_VECTTBL(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_HFSR_VECTTBL_SHIFT))&S32_SCB_HFSR_VECTTBL_MASK) 443 #define S32_SCB_HFSR_FORCED_MASK 0x40000000u 444 #define S32_SCB_HFSR_FORCED_SHIFT 30u 445 #define S32_SCB_HFSR_FORCED_WIDTH 1u 446 #define S32_SCB_HFSR_FORCED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_HFSR_FORCED_SHIFT))&S32_SCB_HFSR_FORCED_MASK) 447 #define S32_SCB_HFSR_DEBUGEVT_MASK 0x80000000u 448 #define S32_SCB_HFSR_DEBUGEVT_SHIFT 31u 449 #define S32_SCB_HFSR_DEBUGEVT_WIDTH 1u 450 #define S32_SCB_HFSR_DEBUGEVT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_HFSR_DEBUGEVT_SHIFT))&S32_SCB_HFSR_DEBUGEVT_MASK) 451 /* DFSR Bit Fields */ 452 #define S32_SCB_DFSR_HALTED_MASK 0x1u 453 #define S32_SCB_DFSR_HALTED_SHIFT 0u 454 #define S32_SCB_DFSR_HALTED_WIDTH 1u 455 #define S32_SCB_DFSR_HALTED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_HALTED_SHIFT))&S32_SCB_DFSR_HALTED_MASK) 456 #define S32_SCB_DFSR_BKPT_MASK 0x2u 457 #define S32_SCB_DFSR_BKPT_SHIFT 1u 458 #define S32_SCB_DFSR_BKPT_WIDTH 1u 459 #define S32_SCB_DFSR_BKPT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_BKPT_SHIFT))&S32_SCB_DFSR_BKPT_MASK) 460 #define S32_SCB_DFSR_DWTTRAP_MASK 0x4u 461 #define S32_SCB_DFSR_DWTTRAP_SHIFT 2u 462 #define S32_SCB_DFSR_DWTTRAP_WIDTH 1u 463 #define S32_SCB_DFSR_DWTTRAP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_DWTTRAP_SHIFT))&S32_SCB_DFSR_DWTTRAP_MASK) 464 #define S32_SCB_DFSR_VCATCH_MASK 0x8u 465 #define S32_SCB_DFSR_VCATCH_SHIFT 3u 466 #define S32_SCB_DFSR_VCATCH_WIDTH 1u 467 #define S32_SCB_DFSR_VCATCH(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_VCATCH_SHIFT))&S32_SCB_DFSR_VCATCH_MASK) 468 #define S32_SCB_DFSR_EXTERNAL_MASK 0x10u 469 #define S32_SCB_DFSR_EXTERNAL_SHIFT 4u 470 #define S32_SCB_DFSR_EXTERNAL_WIDTH 1u 471 #define S32_SCB_DFSR_EXTERNAL(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_EXTERNAL_SHIFT))&S32_SCB_DFSR_EXTERNAL_MASK) 472 /* MMFAR Bit Fields */ 473 #define S32_SCB_MMFAR_ADDRESS_MASK 0xFFFFFFFFu 474 #define S32_SCB_MMFAR_ADDRESS_SHIFT 0u 475 #define S32_SCB_MMFAR_ADDRESS_WIDTH 32u 476 #define S32_SCB_MMFAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_MMFAR_ADDRESS_SHIFT))&S32_SCB_MMFAR_ADDRESS_MASK) 477 /* BFAR Bit Fields */ 478 #define S32_SCB_BFAR_ADDRESS_MASK 0xFFFFFFFFu 479 #define S32_SCB_BFAR_ADDRESS_SHIFT 0u 480 #define S32_SCB_BFAR_ADDRESS_WIDTH 32u 481 #define S32_SCB_BFAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_BFAR_ADDRESS_SHIFT))&S32_SCB_BFAR_ADDRESS_MASK) 482 /* AFSR Bit Fields */ 483 #define S32_SCB_AFSR_AUXFAULT_MASK 0xFFFFFFFFu 484 #define S32_SCB_AFSR_AUXFAULT_SHIFT 0u 485 #define S32_SCB_AFSR_AUXFAULT_WIDTH 32u 486 #define S32_SCB_AFSR_AUXFAULT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AFSR_AUXFAULT_SHIFT))&S32_SCB_AFSR_AUXFAULT_MASK) 487 /* CPACR Bit Fields */ 488 #define S32_SCB_CPACR_CP10_MASK 0x300000u 489 #define S32_SCB_CPACR_CP10_SHIFT 20u 490 #define S32_SCB_CPACR_CP10_WIDTH 2u 491 #define S32_SCB_CPACR_CP10(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPACR_CP10_SHIFT))&S32_SCB_CPACR_CP10_MASK) 492 #define S32_SCB_CPACR_CP11_MASK 0xC00000u 493 #define S32_SCB_CPACR_CP11_SHIFT 22u 494 #define S32_SCB_CPACR_CP11_WIDTH 2u 495 #define S32_SCB_CPACR_CP11(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPACR_CP11_SHIFT))&S32_SCB_CPACR_CP11_MASK) 496 /* FPCCR Bit Fields */ 497 #define S32_SCB_FPCCR_LSPACT_MASK 0x1u 498 #define S32_SCB_FPCCR_LSPACT_SHIFT 0u 499 #define S32_SCB_FPCCR_LSPACT_WIDTH 1u 500 #define S32_SCB_FPCCR_LSPACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_LSPACT_SHIFT))&S32_SCB_FPCCR_LSPACT_MASK) 501 #define S32_SCB_FPCCR_USER_MASK 0x2u 502 #define S32_SCB_FPCCR_USER_SHIFT 1u 503 #define S32_SCB_FPCCR_USER_WIDTH 1u 504 #define S32_SCB_FPCCR_USER(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_USER_SHIFT))&S32_SCB_FPCCR_USER_MASK) 505 #define S32_SCB_FPCCR_THREAD_MASK 0x8u 506 #define S32_SCB_FPCCR_THREAD_SHIFT 3u 507 #define S32_SCB_FPCCR_THREAD_WIDTH 1u 508 #define S32_SCB_FPCCR_THREAD(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_THREAD_SHIFT))&S32_SCB_FPCCR_THREAD_MASK) 509 #define S32_SCB_FPCCR_HFRDY_MASK 0x10u 510 #define S32_SCB_FPCCR_HFRDY_SHIFT 4u 511 #define S32_SCB_FPCCR_HFRDY_WIDTH 1u 512 #define S32_SCB_FPCCR_HFRDY(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_HFRDY_SHIFT))&S32_SCB_FPCCR_HFRDY_MASK) 513 #define S32_SCB_FPCCR_MMRDY_MASK 0x20u 514 #define S32_SCB_FPCCR_MMRDY_SHIFT 5u 515 #define S32_SCB_FPCCR_MMRDY_WIDTH 1u 516 #define S32_SCB_FPCCR_MMRDY(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_MMRDY_SHIFT))&S32_SCB_FPCCR_MMRDY_MASK) 517 #define S32_SCB_FPCCR_BFRDY_MASK 0x40u 518 #define S32_SCB_FPCCR_BFRDY_SHIFT 6u 519 #define S32_SCB_FPCCR_BFRDY_WIDTH 1u 520 #define S32_SCB_FPCCR_BFRDY(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_BFRDY_SHIFT))&S32_SCB_FPCCR_BFRDY_MASK) 521 #define S32_SCB_FPCCR_MONRDY_MASK 0x100u 522 #define S32_SCB_FPCCR_MONRDY_SHIFT 8u 523 #define S32_SCB_FPCCR_MONRDY_WIDTH 1u 524 #define S32_SCB_FPCCR_MONRDY(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_MONRDY_SHIFT))&S32_SCB_FPCCR_MONRDY_MASK) 525 #define S32_SCB_FPCCR_LSPEN_MASK 0x40000000u 526 #define S32_SCB_FPCCR_LSPEN_SHIFT 30u 527 #define S32_SCB_FPCCR_LSPEN_WIDTH 1u 528 #define S32_SCB_FPCCR_LSPEN(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_LSPEN_SHIFT))&S32_SCB_FPCCR_LSPEN_MASK) 529 #define S32_SCB_FPCCR_ASPEN_MASK 0x80000000u 530 #define S32_SCB_FPCCR_ASPEN_SHIFT 31u 531 #define S32_SCB_FPCCR_ASPEN_WIDTH 1u 532 #define S32_SCB_FPCCR_ASPEN(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_ASPEN_SHIFT))&S32_SCB_FPCCR_ASPEN_MASK) 533 /* FPCAR Bit Fields */ 534 #define S32_SCB_FPCAR_ADDRESS_MASK 0xFFFFFFF8u 535 #define S32_SCB_FPCAR_ADDRESS_SHIFT 3u 536 #define S32_SCB_FPCAR_ADDRESS_WIDTH 29u 537 #define S32_SCB_FPCAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCAR_ADDRESS_SHIFT))&S32_SCB_FPCAR_ADDRESS_MASK) 538 /* FPDSCR Bit Fields */ 539 #define S32_SCB_FPDSCR_RMode_MASK 0xC00000u 540 #define S32_SCB_FPDSCR_RMode_SHIFT 22u 541 #define S32_SCB_FPDSCR_RMode_WIDTH 2u 542 #define S32_SCB_FPDSCR_RMode(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPDSCR_RMode_SHIFT))&S32_SCB_FPDSCR_RMode_MASK) 543 #define S32_SCB_FPDSCR_FZ_MASK 0x1000000u 544 #define S32_SCB_FPDSCR_FZ_SHIFT 24u 545 #define S32_SCB_FPDSCR_FZ_WIDTH 1u 546 #define S32_SCB_FPDSCR_FZ(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPDSCR_FZ_SHIFT))&S32_SCB_FPDSCR_FZ_MASK) 547 #define S32_SCB_FPDSCR_DN_MASK 0x2000000u 548 #define S32_SCB_FPDSCR_DN_SHIFT 25u 549 #define S32_SCB_FPDSCR_DN_WIDTH 1u 550 #define S32_SCB_FPDSCR_DN(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPDSCR_DN_SHIFT))&S32_SCB_FPDSCR_DN_MASK) 551 #define S32_SCB_FPDSCR_AHP_MASK 0x4000000u 552 #define S32_SCB_FPDSCR_AHP_SHIFT 26u 553 #define S32_SCB_FPDSCR_AHP_WIDTH 1u 554 #define S32_SCB_FPDSCR_AHP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPDSCR_AHP_SHIFT))&S32_SCB_FPDSCR_AHP_MASK) 555 556 /*! 557 * @} 558 */ /* end of group S32_SCB_Register_Masks */ 559 560 561 /*! 562 * @} 563 */ /* end of group S32_SCB_Peripheral_Access_Layer */ 564 565 #endif /* #if !defined(S32K148_SCB_H_) */ 566
