1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K148_SAI.h 10 * @version 1.1 11 * @date 2022-02-02 12 * @brief Peripheral Access Layer for S32K148_SAI 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K148_SAI_H_) /* Check if memory map has not been already included */ 58 #define S32K148_SAI_H_ 59 60 #include "S32K148_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SAI Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SAI_Peripheral_Access_Layer SAI Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SAI - Size of Registers Arrays */ 72 #define SAI_TDR_COUNT 4u 73 #define SAI_TFR_COUNT 4u 74 #define SAI_RDR_COUNT 4u 75 #define SAI_RFR_COUNT 4u 76 77 /** SAI - Register Layout Typedef */ 78 typedef struct { 79 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ 80 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ 81 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x8 */ 82 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0xC */ 83 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x10 */ 84 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0x14 */ 85 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x18 */ 86 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x1C */ 87 __O uint32_t TDR[SAI_TDR_COUNT]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ 88 uint8_t RESERVED_0[16]; 89 __I uint32_t TFR[SAI_TFR_COUNT]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ 90 uint8_t RESERVED_1[16]; 91 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ 92 uint8_t RESERVED_2[36]; 93 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x88 */ 94 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x8C */ 95 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x90 */ 96 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x94 */ 97 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x98 */ 98 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x9C */ 99 __I uint32_t RDR[SAI_RDR_COUNT]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ 100 uint8_t RESERVED_3[16]; 101 __I uint32_t RFR[SAI_RFR_COUNT]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ 102 uint8_t RESERVED_4[16]; 103 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ 104 } SAI_Type, *SAI_MemMapPtr; 105 106 /** Number of instances of the SAI module. */ 107 #define SAI_INSTANCE_COUNT (2u) 108 109 /* SAI - Peripheral instance base addresses */ 110 /** Peripheral SAI0 base address */ 111 #define IP_SAI0_BASE (0x40054000u) 112 /** Peripheral SAI0 base pointer */ 113 #define IP_SAI0 ((SAI_Type *)IP_SAI0_BASE) 114 /** Peripheral SAI1 base address */ 115 #define IP_SAI1_BASE (0x40055000u) 116 /** Peripheral SAI1 base pointer */ 117 #define IP_SAI1 ((SAI_Type *)IP_SAI1_BASE) 118 /** Array initializer of SAI peripheral base addresses */ 119 #define IP_SAI_BASE_ADDRS { IP_SAI0_BASE, IP_SAI1_BASE } 120 /** Array initializer of SAI peripheral base pointers */ 121 #define IP_SAI_BASE_PTRS { IP_SAI0, IP_SAI1 } 122 123 /* ---------------------------------------------------------------------------- 124 -- SAI Register Masks 125 ---------------------------------------------------------------------------- */ 126 127 /*! 128 * @addtogroup SAI_Register_Masks SAI Register Masks 129 * @{ 130 */ 131 132 /*! @name VERID - Version ID Register */ 133 /*! @{ */ 134 135 #define SAI_VERID_FEATURE_MASK (0xFFFFU) 136 #define SAI_VERID_FEATURE_SHIFT (0U) 137 #define SAI_VERID_FEATURE_WIDTH (16U) 138 #define SAI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << SAI_VERID_FEATURE_SHIFT)) & SAI_VERID_FEATURE_MASK) 139 140 #define SAI_VERID_MINOR_MASK (0xFF0000U) 141 #define SAI_VERID_MINOR_SHIFT (16U) 142 #define SAI_VERID_MINOR_WIDTH (8U) 143 #define SAI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SAI_VERID_MINOR_SHIFT)) & SAI_VERID_MINOR_MASK) 144 145 #define SAI_VERID_MAJOR_MASK (0xFF000000U) 146 #define SAI_VERID_MAJOR_SHIFT (24U) 147 #define SAI_VERID_MAJOR_WIDTH (8U) 148 #define SAI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SAI_VERID_MAJOR_SHIFT)) & SAI_VERID_MAJOR_MASK) 149 /*! @} */ 150 151 /*! @name PARAM - Parameter Register */ 152 /*! @{ */ 153 154 #define SAI_PARAM_DATALINE_MASK (0xFU) 155 #define SAI_PARAM_DATALINE_SHIFT (0U) 156 #define SAI_PARAM_DATALINE_WIDTH (4U) 157 #define SAI_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << SAI_PARAM_DATALINE_SHIFT)) & SAI_PARAM_DATALINE_MASK) 158 159 #define SAI_PARAM_FIFO_MASK (0xF00U) 160 #define SAI_PARAM_FIFO_SHIFT (8U) 161 #define SAI_PARAM_FIFO_WIDTH (4U) 162 #define SAI_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << SAI_PARAM_FIFO_SHIFT)) & SAI_PARAM_FIFO_MASK) 163 164 #define SAI_PARAM_FRAME_MASK (0xF0000U) 165 #define SAI_PARAM_FRAME_SHIFT (16U) 166 #define SAI_PARAM_FRAME_WIDTH (4U) 167 #define SAI_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << SAI_PARAM_FRAME_SHIFT)) & SAI_PARAM_FRAME_MASK) 168 /*! @} */ 169 170 /*! @name TCSR - SAI Transmit Control Register */ 171 /*! @{ */ 172 173 #define SAI_TCSR_FRDE_MASK (0x1U) 174 #define SAI_TCSR_FRDE_SHIFT (0U) 175 #define SAI_TCSR_FRDE_WIDTH (1U) 176 #define SAI_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCSR_FRDE_SHIFT)) & SAI_TCSR_FRDE_MASK) 177 178 #define SAI_TCSR_FWDE_MASK (0x2U) 179 #define SAI_TCSR_FWDE_SHIFT (1U) 180 #define SAI_TCSR_FWDE_WIDTH (1U) 181 #define SAI_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCSR_FWDE_SHIFT)) & SAI_TCSR_FWDE_MASK) 182 183 #define SAI_TCSR_FRIE_MASK (0x100U) 184 #define SAI_TCSR_FRIE_SHIFT (8U) 185 #define SAI_TCSR_FRIE_WIDTH (1U) 186 #define SAI_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCSR_FRIE_SHIFT)) & SAI_TCSR_FRIE_MASK) 187 188 #define SAI_TCSR_FWIE_MASK (0x200U) 189 #define SAI_TCSR_FWIE_SHIFT (9U) 190 #define SAI_TCSR_FWIE_WIDTH (1U) 191 #define SAI_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCSR_FWIE_SHIFT)) & SAI_TCSR_FWIE_MASK) 192 193 #define SAI_TCSR_FEIE_MASK (0x400U) 194 #define SAI_TCSR_FEIE_SHIFT (10U) 195 #define SAI_TCSR_FEIE_WIDTH (1U) 196 #define SAI_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCSR_FEIE_SHIFT)) & SAI_TCSR_FEIE_MASK) 197 198 #define SAI_TCSR_SEIE_MASK (0x800U) 199 #define SAI_TCSR_SEIE_SHIFT (11U) 200 #define SAI_TCSR_SEIE_WIDTH (1U) 201 #define SAI_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCSR_SEIE_SHIFT)) & SAI_TCSR_SEIE_MASK) 202 203 #define SAI_TCSR_WSIE_MASK (0x1000U) 204 #define SAI_TCSR_WSIE_SHIFT (12U) 205 #define SAI_TCSR_WSIE_WIDTH (1U) 206 #define SAI_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCSR_WSIE_SHIFT)) & SAI_TCSR_WSIE_MASK) 207 208 #define SAI_TCSR_FRF_MASK (0x10000U) 209 #define SAI_TCSR_FRF_SHIFT (16U) 210 #define SAI_TCSR_FRF_WIDTH (1U) 211 #define SAI_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCSR_FRF_SHIFT)) & SAI_TCSR_FRF_MASK) 212 213 #define SAI_TCSR_FWF_MASK (0x20000U) 214 #define SAI_TCSR_FWF_SHIFT (17U) 215 #define SAI_TCSR_FWF_WIDTH (1U) 216 #define SAI_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCSR_FWF_SHIFT)) & SAI_TCSR_FWF_MASK) 217 218 #define SAI_TCSR_FEF_MASK (0x40000U) 219 #define SAI_TCSR_FEF_SHIFT (18U) 220 #define SAI_TCSR_FEF_WIDTH (1U) 221 #define SAI_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCSR_FEF_SHIFT)) & SAI_TCSR_FEF_MASK) 222 223 #define SAI_TCSR_SEF_MASK (0x80000U) 224 #define SAI_TCSR_SEF_SHIFT (19U) 225 #define SAI_TCSR_SEF_WIDTH (1U) 226 #define SAI_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCSR_SEF_SHIFT)) & SAI_TCSR_SEF_MASK) 227 228 #define SAI_TCSR_WSF_MASK (0x100000U) 229 #define SAI_TCSR_WSF_SHIFT (20U) 230 #define SAI_TCSR_WSF_WIDTH (1U) 231 #define SAI_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCSR_WSF_SHIFT)) & SAI_TCSR_WSF_MASK) 232 233 #define SAI_TCSR_SR_MASK (0x1000000U) 234 #define SAI_TCSR_SR_SHIFT (24U) 235 #define SAI_TCSR_SR_WIDTH (1U) 236 #define SAI_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCSR_SR_SHIFT)) & SAI_TCSR_SR_MASK) 237 238 #define SAI_TCSR_FR_MASK (0x2000000U) 239 #define SAI_TCSR_FR_SHIFT (25U) 240 #define SAI_TCSR_FR_WIDTH (1U) 241 #define SAI_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCSR_FR_SHIFT)) & SAI_TCSR_FR_MASK) 242 243 #define SAI_TCSR_BCE_MASK (0x10000000U) 244 #define SAI_TCSR_BCE_SHIFT (28U) 245 #define SAI_TCSR_BCE_WIDTH (1U) 246 #define SAI_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCSR_BCE_SHIFT)) & SAI_TCSR_BCE_MASK) 247 248 #define SAI_TCSR_DBGE_MASK (0x20000000U) 249 #define SAI_TCSR_DBGE_SHIFT (29U) 250 #define SAI_TCSR_DBGE_WIDTH (1U) 251 #define SAI_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCSR_DBGE_SHIFT)) & SAI_TCSR_DBGE_MASK) 252 253 #define SAI_TCSR_TE_MASK (0x80000000U) 254 #define SAI_TCSR_TE_SHIFT (31U) 255 #define SAI_TCSR_TE_WIDTH (1U) 256 #define SAI_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCSR_TE_SHIFT)) & SAI_TCSR_TE_MASK) 257 /*! @} */ 258 259 /*! @name TCR1 - SAI Transmit Configuration 1 Register */ 260 /*! @{ */ 261 262 #define SAI_TCR1_TFW_MASK (0x7U) 263 #define SAI_TCR1_TFW_SHIFT (0U) 264 #define SAI_TCR1_TFW_WIDTH (3U) 265 #define SAI_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR1_TFW_SHIFT)) & SAI_TCR1_TFW_MASK) 266 /*! @} */ 267 268 /*! @name TCR2 - SAI Transmit Configuration 2 Register */ 269 /*! @{ */ 270 271 #define SAI_TCR2_DIV_MASK (0xFFU) 272 #define SAI_TCR2_DIV_SHIFT (0U) 273 #define SAI_TCR2_DIV_WIDTH (8U) 274 #define SAI_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR2_DIV_SHIFT)) & SAI_TCR2_DIV_MASK) 275 276 #define SAI_TCR2_BCD_MASK (0x1000000U) 277 #define SAI_TCR2_BCD_SHIFT (24U) 278 #define SAI_TCR2_BCD_WIDTH (1U) 279 #define SAI_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR2_BCD_SHIFT)) & SAI_TCR2_BCD_MASK) 280 281 #define SAI_TCR2_BCP_MASK (0x2000000U) 282 #define SAI_TCR2_BCP_SHIFT (25U) 283 #define SAI_TCR2_BCP_WIDTH (1U) 284 #define SAI_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR2_BCP_SHIFT)) & SAI_TCR2_BCP_MASK) 285 286 #define SAI_TCR2_MSEL_MASK (0xC000000U) 287 #define SAI_TCR2_MSEL_SHIFT (26U) 288 #define SAI_TCR2_MSEL_WIDTH (2U) 289 #define SAI_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR2_MSEL_SHIFT)) & SAI_TCR2_MSEL_MASK) 290 291 #define SAI_TCR2_BCI_MASK (0x10000000U) 292 #define SAI_TCR2_BCI_SHIFT (28U) 293 #define SAI_TCR2_BCI_WIDTH (1U) 294 #define SAI_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR2_BCI_SHIFT)) & SAI_TCR2_BCI_MASK) 295 296 #define SAI_TCR2_SYNC_MASK (0xC0000000U) 297 #define SAI_TCR2_SYNC_SHIFT (30U) 298 #define SAI_TCR2_SYNC_WIDTH (2U) 299 #define SAI_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR2_SYNC_SHIFT)) & SAI_TCR2_SYNC_MASK) 300 /*! @} */ 301 302 /*! @name TCR3 - SAI Transmit Configuration 3 Register */ 303 /*! @{ */ 304 305 #define SAI_TCR3_WDFL_MASK (0xFU) 306 #define SAI_TCR3_WDFL_SHIFT (0U) 307 #define SAI_TCR3_WDFL_WIDTH (4U) 308 #define SAI_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR3_WDFL_SHIFT)) & SAI_TCR3_WDFL_MASK) 309 310 #define SAI_TCR3_TCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ 311 #define SAI_TCR3_TCE_SHIFT (16U) 312 #define SAI_TCR3_TCE_WIDTH (4U) 313 #define SAI_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR3_TCE_SHIFT)) & SAI_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ 314 315 #define SAI_TCR3_CFR_MASK (0xF000000U) 316 #define SAI_TCR3_CFR_SHIFT (24U) 317 #define SAI_TCR3_CFR_WIDTH (4U) 318 #define SAI_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR3_CFR_SHIFT)) & SAI_TCR3_CFR_MASK) 319 /*! @} */ 320 321 /*! @name TCR4 - SAI Transmit Configuration 4 Register */ 322 /*! @{ */ 323 324 #define SAI_TCR4_FSD_MASK (0x1U) 325 #define SAI_TCR4_FSD_SHIFT (0U) 326 #define SAI_TCR4_FSD_WIDTH (1U) 327 #define SAI_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR4_FSD_SHIFT)) & SAI_TCR4_FSD_MASK) 328 329 #define SAI_TCR4_FSP_MASK (0x2U) 330 #define SAI_TCR4_FSP_SHIFT (1U) 331 #define SAI_TCR4_FSP_WIDTH (1U) 332 #define SAI_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR4_FSP_SHIFT)) & SAI_TCR4_FSP_MASK) 333 334 #define SAI_TCR4_ONDEM_MASK (0x4U) 335 #define SAI_TCR4_ONDEM_SHIFT (2U) 336 #define SAI_TCR4_ONDEM_WIDTH (1U) 337 #define SAI_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR4_ONDEM_SHIFT)) & SAI_TCR4_ONDEM_MASK) 338 339 #define SAI_TCR4_FSE_MASK (0x8U) 340 #define SAI_TCR4_FSE_SHIFT (3U) 341 #define SAI_TCR4_FSE_WIDTH (1U) 342 #define SAI_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR4_FSE_SHIFT)) & SAI_TCR4_FSE_MASK) 343 344 #define SAI_TCR4_MF_MASK (0x10U) 345 #define SAI_TCR4_MF_SHIFT (4U) 346 #define SAI_TCR4_MF_WIDTH (1U) 347 #define SAI_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR4_MF_SHIFT)) & SAI_TCR4_MF_MASK) 348 349 #define SAI_TCR4_CHMOD_MASK (0x20U) 350 #define SAI_TCR4_CHMOD_SHIFT (5U) 351 #define SAI_TCR4_CHMOD_WIDTH (1U) 352 #define SAI_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR4_CHMOD_SHIFT)) & SAI_TCR4_CHMOD_MASK) 353 354 #define SAI_TCR4_SYWD_MASK (0x1F00U) 355 #define SAI_TCR4_SYWD_SHIFT (8U) 356 #define SAI_TCR4_SYWD_WIDTH (5U) 357 #define SAI_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR4_SYWD_SHIFT)) & SAI_TCR4_SYWD_MASK) 358 359 #define SAI_TCR4_FRSZ_MASK (0xF0000U) 360 #define SAI_TCR4_FRSZ_SHIFT (16U) 361 #define SAI_TCR4_FRSZ_WIDTH (4U) 362 #define SAI_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR4_FRSZ_SHIFT)) & SAI_TCR4_FRSZ_MASK) 363 364 #define SAI_TCR4_FPACK_MASK (0x3000000U) 365 #define SAI_TCR4_FPACK_SHIFT (24U) 366 #define SAI_TCR4_FPACK_WIDTH (2U) 367 #define SAI_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR4_FPACK_SHIFT)) & SAI_TCR4_FPACK_MASK) 368 369 #define SAI_TCR4_FCOMB_MASK (0xC000000U) 370 #define SAI_TCR4_FCOMB_SHIFT (26U) 371 #define SAI_TCR4_FCOMB_WIDTH (2U) 372 #define SAI_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR4_FCOMB_SHIFT)) & SAI_TCR4_FCOMB_MASK) 373 374 #define SAI_TCR4_FCONT_MASK (0x10000000U) 375 #define SAI_TCR4_FCONT_SHIFT (28U) 376 #define SAI_TCR4_FCONT_WIDTH (1U) 377 #define SAI_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR4_FCONT_SHIFT)) & SAI_TCR4_FCONT_MASK) 378 /*! @} */ 379 380 /*! @name TCR5 - SAI Transmit Configuration 5 Register */ 381 /*! @{ */ 382 383 #define SAI_TCR5_FBT_MASK (0x1F00U) 384 #define SAI_TCR5_FBT_SHIFT (8U) 385 #define SAI_TCR5_FBT_WIDTH (5U) 386 #define SAI_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR5_FBT_SHIFT)) & SAI_TCR5_FBT_MASK) 387 388 #define SAI_TCR5_W0W_MASK (0x1F0000U) 389 #define SAI_TCR5_W0W_SHIFT (16U) 390 #define SAI_TCR5_W0W_WIDTH (5U) 391 #define SAI_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR5_W0W_SHIFT)) & SAI_TCR5_W0W_MASK) 392 393 #define SAI_TCR5_WNW_MASK (0x1F000000U) 394 #define SAI_TCR5_WNW_SHIFT (24U) 395 #define SAI_TCR5_WNW_WIDTH (5U) 396 #define SAI_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << SAI_TCR5_WNW_SHIFT)) & SAI_TCR5_WNW_MASK) 397 /*! @} */ 398 399 /*! @name TDR - SAI Transmit Data Register */ 400 /*! @{ */ 401 402 #define SAI_TDR_TDR_MASK (0xFFFFFFFFU) 403 #define SAI_TDR_TDR_SHIFT (0U) 404 #define SAI_TDR_TDR_WIDTH (32U) 405 #define SAI_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << SAI_TDR_TDR_SHIFT)) & SAI_TDR_TDR_MASK) 406 /*! @} */ 407 408 /*! @name TFR - SAI Transmit FIFO Register */ 409 /*! @{ */ 410 411 #define SAI_TFR_RFP_MASK (0xFU) 412 #define SAI_TFR_RFP_SHIFT (0U) 413 #define SAI_TFR_RFP_WIDTH (4U) 414 #define SAI_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << SAI_TFR_RFP_SHIFT)) & SAI_TFR_RFP_MASK) 415 416 #define SAI_TFR_WFP_MASK (0xF0000U) 417 #define SAI_TFR_WFP_SHIFT (16U) 418 #define SAI_TFR_WFP_WIDTH (4U) 419 #define SAI_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << SAI_TFR_WFP_SHIFT)) & SAI_TFR_WFP_MASK) 420 421 #define SAI_TFR_WCP_MASK (0x80000000U) 422 #define SAI_TFR_WCP_SHIFT (31U) 423 #define SAI_TFR_WCP_WIDTH (1U) 424 #define SAI_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << SAI_TFR_WCP_SHIFT)) & SAI_TFR_WCP_MASK) 425 /*! @} */ 426 427 /*! @name TMR - SAI Transmit Mask Register */ 428 /*! @{ */ 429 430 #define SAI_TMR_TWM_MASK (0xFFFFU) 431 #define SAI_TMR_TWM_SHIFT (0U) 432 #define SAI_TMR_TWM_WIDTH (16U) 433 #define SAI_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << SAI_TMR_TWM_SHIFT)) & SAI_TMR_TWM_MASK) 434 /*! @} */ 435 436 /*! @name RCSR - SAI Receive Control Register */ 437 /*! @{ */ 438 439 #define SAI_RCSR_FRDE_MASK (0x1U) 440 #define SAI_RCSR_FRDE_SHIFT (0U) 441 #define SAI_RCSR_FRDE_WIDTH (1U) 442 #define SAI_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCSR_FRDE_SHIFT)) & SAI_RCSR_FRDE_MASK) 443 444 #define SAI_RCSR_FWDE_MASK (0x2U) 445 #define SAI_RCSR_FWDE_SHIFT (1U) 446 #define SAI_RCSR_FWDE_WIDTH (1U) 447 #define SAI_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCSR_FWDE_SHIFT)) & SAI_RCSR_FWDE_MASK) 448 449 #define SAI_RCSR_FRIE_MASK (0x100U) 450 #define SAI_RCSR_FRIE_SHIFT (8U) 451 #define SAI_RCSR_FRIE_WIDTH (1U) 452 #define SAI_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCSR_FRIE_SHIFT)) & SAI_RCSR_FRIE_MASK) 453 454 #define SAI_RCSR_FWIE_MASK (0x200U) 455 #define SAI_RCSR_FWIE_SHIFT (9U) 456 #define SAI_RCSR_FWIE_WIDTH (1U) 457 #define SAI_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCSR_FWIE_SHIFT)) & SAI_RCSR_FWIE_MASK) 458 459 #define SAI_RCSR_FEIE_MASK (0x400U) 460 #define SAI_RCSR_FEIE_SHIFT (10U) 461 #define SAI_RCSR_FEIE_WIDTH (1U) 462 #define SAI_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCSR_FEIE_SHIFT)) & SAI_RCSR_FEIE_MASK) 463 464 #define SAI_RCSR_SEIE_MASK (0x800U) 465 #define SAI_RCSR_SEIE_SHIFT (11U) 466 #define SAI_RCSR_SEIE_WIDTH (1U) 467 #define SAI_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCSR_SEIE_SHIFT)) & SAI_RCSR_SEIE_MASK) 468 469 #define SAI_RCSR_WSIE_MASK (0x1000U) 470 #define SAI_RCSR_WSIE_SHIFT (12U) 471 #define SAI_RCSR_WSIE_WIDTH (1U) 472 #define SAI_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCSR_WSIE_SHIFT)) & SAI_RCSR_WSIE_MASK) 473 474 #define SAI_RCSR_FRF_MASK (0x10000U) 475 #define SAI_RCSR_FRF_SHIFT (16U) 476 #define SAI_RCSR_FRF_WIDTH (1U) 477 #define SAI_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCSR_FRF_SHIFT)) & SAI_RCSR_FRF_MASK) 478 479 #define SAI_RCSR_FWF_MASK (0x20000U) 480 #define SAI_RCSR_FWF_SHIFT (17U) 481 #define SAI_RCSR_FWF_WIDTH (1U) 482 #define SAI_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCSR_FWF_SHIFT)) & SAI_RCSR_FWF_MASK) 483 484 #define SAI_RCSR_FEF_MASK (0x40000U) 485 #define SAI_RCSR_FEF_SHIFT (18U) 486 #define SAI_RCSR_FEF_WIDTH (1U) 487 #define SAI_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCSR_FEF_SHIFT)) & SAI_RCSR_FEF_MASK) 488 489 #define SAI_RCSR_SEF_MASK (0x80000U) 490 #define SAI_RCSR_SEF_SHIFT (19U) 491 #define SAI_RCSR_SEF_WIDTH (1U) 492 #define SAI_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCSR_SEF_SHIFT)) & SAI_RCSR_SEF_MASK) 493 494 #define SAI_RCSR_WSF_MASK (0x100000U) 495 #define SAI_RCSR_WSF_SHIFT (20U) 496 #define SAI_RCSR_WSF_WIDTH (1U) 497 #define SAI_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCSR_WSF_SHIFT)) & SAI_RCSR_WSF_MASK) 498 499 #define SAI_RCSR_SR_MASK (0x1000000U) 500 #define SAI_RCSR_SR_SHIFT (24U) 501 #define SAI_RCSR_SR_WIDTH (1U) 502 #define SAI_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCSR_SR_SHIFT)) & SAI_RCSR_SR_MASK) 503 504 #define SAI_RCSR_FR_MASK (0x2000000U) 505 #define SAI_RCSR_FR_SHIFT (25U) 506 #define SAI_RCSR_FR_WIDTH (1U) 507 #define SAI_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCSR_FR_SHIFT)) & SAI_RCSR_FR_MASK) 508 509 #define SAI_RCSR_BCE_MASK (0x10000000U) 510 #define SAI_RCSR_BCE_SHIFT (28U) 511 #define SAI_RCSR_BCE_WIDTH (1U) 512 #define SAI_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCSR_BCE_SHIFT)) & SAI_RCSR_BCE_MASK) 513 514 #define SAI_RCSR_DBGE_MASK (0x20000000U) 515 #define SAI_RCSR_DBGE_SHIFT (29U) 516 #define SAI_RCSR_DBGE_WIDTH (1U) 517 #define SAI_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCSR_DBGE_SHIFT)) & SAI_RCSR_DBGE_MASK) 518 519 #define SAI_RCSR_RE_MASK (0x80000000U) 520 #define SAI_RCSR_RE_SHIFT (31U) 521 #define SAI_RCSR_RE_WIDTH (1U) 522 #define SAI_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCSR_RE_SHIFT)) & SAI_RCSR_RE_MASK) 523 /*! @} */ 524 525 /*! @name RCR1 - SAI Receive Configuration 1 Register */ 526 /*! @{ */ 527 528 #define SAI_RCR1_RFW_MASK (0x7U) 529 #define SAI_RCR1_RFW_SHIFT (0U) 530 #define SAI_RCR1_RFW_WIDTH (3U) 531 #define SAI_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR1_RFW_SHIFT)) & SAI_RCR1_RFW_MASK) 532 /*! @} */ 533 534 /*! @name RCR2 - SAI Receive Configuration 2 Register */ 535 /*! @{ */ 536 537 #define SAI_RCR2_DIV_MASK (0xFFU) 538 #define SAI_RCR2_DIV_SHIFT (0U) 539 #define SAI_RCR2_DIV_WIDTH (8U) 540 #define SAI_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR2_DIV_SHIFT)) & SAI_RCR2_DIV_MASK) 541 542 #define SAI_RCR2_BCD_MASK (0x1000000U) 543 #define SAI_RCR2_BCD_SHIFT (24U) 544 #define SAI_RCR2_BCD_WIDTH (1U) 545 #define SAI_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR2_BCD_SHIFT)) & SAI_RCR2_BCD_MASK) 546 547 #define SAI_RCR2_BCP_MASK (0x2000000U) 548 #define SAI_RCR2_BCP_SHIFT (25U) 549 #define SAI_RCR2_BCP_WIDTH (1U) 550 #define SAI_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR2_BCP_SHIFT)) & SAI_RCR2_BCP_MASK) 551 552 #define SAI_RCR2_MSEL_MASK (0xC000000U) 553 #define SAI_RCR2_MSEL_SHIFT (26U) 554 #define SAI_RCR2_MSEL_WIDTH (2U) 555 #define SAI_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR2_MSEL_SHIFT)) & SAI_RCR2_MSEL_MASK) 556 557 #define SAI_RCR2_BCI_MASK (0x10000000U) 558 #define SAI_RCR2_BCI_SHIFT (28U) 559 #define SAI_RCR2_BCI_WIDTH (1U) 560 #define SAI_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR2_BCI_SHIFT)) & SAI_RCR2_BCI_MASK) 561 562 #define SAI_RCR2_SYNC_MASK (0xC0000000U) 563 #define SAI_RCR2_SYNC_SHIFT (30U) 564 #define SAI_RCR2_SYNC_WIDTH (2U) 565 #define SAI_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR2_SYNC_SHIFT)) & SAI_RCR2_SYNC_MASK) 566 /*! @} */ 567 568 /*! @name RCR3 - SAI Receive Configuration 3 Register */ 569 /*! @{ */ 570 571 #define SAI_RCR3_WDFL_MASK (0xFU) 572 #define SAI_RCR3_WDFL_SHIFT (0U) 573 #define SAI_RCR3_WDFL_WIDTH (4U) 574 #define SAI_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR3_WDFL_SHIFT)) & SAI_RCR3_WDFL_MASK) 575 576 #define SAI_RCR3_RCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ 577 #define SAI_RCR3_RCE_SHIFT (16U) 578 #define SAI_RCR3_RCE_WIDTH (4U) 579 #define SAI_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR3_RCE_SHIFT)) & SAI_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ 580 581 #define SAI_RCR3_CFR_MASK (0xF000000U) 582 #define SAI_RCR3_CFR_SHIFT (24U) 583 #define SAI_RCR3_CFR_WIDTH (4U) 584 #define SAI_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR3_CFR_SHIFT)) & SAI_RCR3_CFR_MASK) 585 /*! @} */ 586 587 /*! @name RCR4 - SAI Receive Configuration 4 Register */ 588 /*! @{ */ 589 590 #define SAI_RCR4_FSD_MASK (0x1U) 591 #define SAI_RCR4_FSD_SHIFT (0U) 592 #define SAI_RCR4_FSD_WIDTH (1U) 593 #define SAI_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR4_FSD_SHIFT)) & SAI_RCR4_FSD_MASK) 594 595 #define SAI_RCR4_FSP_MASK (0x2U) 596 #define SAI_RCR4_FSP_SHIFT (1U) 597 #define SAI_RCR4_FSP_WIDTH (1U) 598 #define SAI_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR4_FSP_SHIFT)) & SAI_RCR4_FSP_MASK) 599 600 #define SAI_RCR4_ONDEM_MASK (0x4U) 601 #define SAI_RCR4_ONDEM_SHIFT (2U) 602 #define SAI_RCR4_ONDEM_WIDTH (1U) 603 #define SAI_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR4_ONDEM_SHIFT)) & SAI_RCR4_ONDEM_MASK) 604 605 #define SAI_RCR4_FSE_MASK (0x8U) 606 #define SAI_RCR4_FSE_SHIFT (3U) 607 #define SAI_RCR4_FSE_WIDTH (1U) 608 #define SAI_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR4_FSE_SHIFT)) & SAI_RCR4_FSE_MASK) 609 610 #define SAI_RCR4_MF_MASK (0x10U) 611 #define SAI_RCR4_MF_SHIFT (4U) 612 #define SAI_RCR4_MF_WIDTH (1U) 613 #define SAI_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR4_MF_SHIFT)) & SAI_RCR4_MF_MASK) 614 615 #define SAI_RCR4_SYWD_MASK (0x1F00U) 616 #define SAI_RCR4_SYWD_SHIFT (8U) 617 #define SAI_RCR4_SYWD_WIDTH (5U) 618 #define SAI_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR4_SYWD_SHIFT)) & SAI_RCR4_SYWD_MASK) 619 620 #define SAI_RCR4_FRSZ_MASK (0xF0000U) 621 #define SAI_RCR4_FRSZ_SHIFT (16U) 622 #define SAI_RCR4_FRSZ_WIDTH (4U) 623 #define SAI_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR4_FRSZ_SHIFT)) & SAI_RCR4_FRSZ_MASK) 624 625 #define SAI_RCR4_FPACK_MASK (0x3000000U) 626 #define SAI_RCR4_FPACK_SHIFT (24U) 627 #define SAI_RCR4_FPACK_WIDTH (2U) 628 #define SAI_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR4_FPACK_SHIFT)) & SAI_RCR4_FPACK_MASK) 629 630 #define SAI_RCR4_FCOMB_MASK (0xC000000U) 631 #define SAI_RCR4_FCOMB_SHIFT (26U) 632 #define SAI_RCR4_FCOMB_WIDTH (2U) 633 #define SAI_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR4_FCOMB_SHIFT)) & SAI_RCR4_FCOMB_MASK) 634 635 #define SAI_RCR4_FCONT_MASK (0x10000000U) 636 #define SAI_RCR4_FCONT_SHIFT (28U) 637 #define SAI_RCR4_FCONT_WIDTH (1U) 638 #define SAI_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR4_FCONT_SHIFT)) & SAI_RCR4_FCONT_MASK) 639 /*! @} */ 640 641 /*! @name RCR5 - SAI Receive Configuration 5 Register */ 642 /*! @{ */ 643 644 #define SAI_RCR5_FBT_MASK (0x1F00U) 645 #define SAI_RCR5_FBT_SHIFT (8U) 646 #define SAI_RCR5_FBT_WIDTH (5U) 647 #define SAI_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR5_FBT_SHIFT)) & SAI_RCR5_FBT_MASK) 648 649 #define SAI_RCR5_W0W_MASK (0x1F0000U) 650 #define SAI_RCR5_W0W_SHIFT (16U) 651 #define SAI_RCR5_W0W_WIDTH (5U) 652 #define SAI_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR5_W0W_SHIFT)) & SAI_RCR5_W0W_MASK) 653 654 #define SAI_RCR5_WNW_MASK (0x1F000000U) 655 #define SAI_RCR5_WNW_SHIFT (24U) 656 #define SAI_RCR5_WNW_WIDTH (5U) 657 #define SAI_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << SAI_RCR5_WNW_SHIFT)) & SAI_RCR5_WNW_MASK) 658 /*! @} */ 659 660 /*! @name RDR - SAI Receive Data Register */ 661 /*! @{ */ 662 663 #define SAI_RDR_RDR_MASK (0xFFFFFFFFU) 664 #define SAI_RDR_RDR_SHIFT (0U) 665 #define SAI_RDR_RDR_WIDTH (32U) 666 #define SAI_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << SAI_RDR_RDR_SHIFT)) & SAI_RDR_RDR_MASK) 667 /*! @} */ 668 669 /*! @name RFR - SAI Receive FIFO Register */ 670 /*! @{ */ 671 672 #define SAI_RFR_RFP_MASK (0xFU) 673 #define SAI_RFR_RFP_SHIFT (0U) 674 #define SAI_RFR_RFP_WIDTH (4U) 675 #define SAI_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << SAI_RFR_RFP_SHIFT)) & SAI_RFR_RFP_MASK) 676 677 #define SAI_RFR_RCP_MASK (0x8000U) 678 #define SAI_RFR_RCP_SHIFT (15U) 679 #define SAI_RFR_RCP_WIDTH (1U) 680 #define SAI_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << SAI_RFR_RCP_SHIFT)) & SAI_RFR_RCP_MASK) 681 682 #define SAI_RFR_WFP_MASK (0xF0000U) 683 #define SAI_RFR_WFP_SHIFT (16U) 684 #define SAI_RFR_WFP_WIDTH (4U) 685 #define SAI_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << SAI_RFR_WFP_SHIFT)) & SAI_RFR_WFP_MASK) 686 /*! @} */ 687 688 /*! @name RMR - SAI Receive Mask Register */ 689 /*! @{ */ 690 691 #define SAI_RMR_RWM_MASK (0xFFFFU) 692 #define SAI_RMR_RWM_SHIFT (0U) 693 #define SAI_RMR_RWM_WIDTH (16U) 694 #define SAI_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << SAI_RMR_RWM_SHIFT)) & SAI_RMR_RWM_MASK) 695 /*! @} */ 696 697 /*! 698 * @} 699 */ /* end of group SAI_Register_Masks */ 700 701 /*! 702 * @} 703 */ /* end of group SAI_Peripheral_Access_Layer */ 704 705 #endif /* #if !defined(S32K148_SAI_H_) */ 706
