1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K148_QuadSPI.h 10 * @version 1.1 11 * @date 2022-02-02 12 * @brief Peripheral Access Layer for S32K148_QuadSPI 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K148_QuadSPI_H_) /* Check if memory map has not been already included */ 58 #define S32K148_QuadSPI_H_ 59 60 #include "S32K148_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- QuadSPI Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup QuadSPI_Peripheral_Access_Layer QuadSPI Peripheral Access Layer 68 * @{ 69 */ 70 71 /** QuadSPI - Size of Registers Arrays */ 72 #define QuadSPI_RBDR_COUNT 32u 73 #define QuadSPI_LUT_COUNT 64u 74 75 /** QuadSPI - Register Layout Typedef */ 76 typedef struct { 77 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ 78 uint8_t RESERVED_0[4]; 79 __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ 80 __IO uint32_t FLSHCR; /**< Flash Configuration Register, offset: 0xC */ 81 __IO uint32_t BUF0CR; /**< Buffer0 Configuration Register, offset: 0x10 */ 82 __IO uint32_t BUF1CR; /**< Buffer1 Configuration Register, offset: 0x14 */ 83 __IO uint32_t BUF2CR; /**< Buffer2 Configuration Register, offset: 0x18 */ 84 __IO uint32_t BUF3CR; /**< Buffer3 Configuration Register, offset: 0x1C */ 85 __IO uint32_t BFGENCR; /**< Buffer Generic Configuration Register, offset: 0x20 */ 86 __IO uint32_t SOCCR; /**< SOC Configuration Register, offset: 0x24 */ 87 uint8_t RESERVED_1[8]; 88 __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ 89 __IO uint32_t BUF1IND; /**< Buffer1 Top Index Register, offset: 0x34 */ 90 __IO uint32_t BUF2IND; /**< Buffer2 Top Index Register, offset: 0x38 */ 91 uint8_t RESERVED_2[196]; 92 __IO uint32_t SFAR; /**< Serial Flash Address Register, offset: 0x100 */ 93 __IO uint32_t SFACR; /**< Serial Flash Address Configuration Register, offset: 0x104 */ 94 __IO uint32_t SMPR; /**< Sampling Register, offset: 0x108 */ 95 __I uint32_t RBSR; /**< RX Buffer Status Register, offset: 0x10C */ 96 __IO uint32_t RBCT; /**< RX Buffer Control Register, offset: 0x110 */ 97 uint8_t RESERVED_3[60]; 98 __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ 99 __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ 100 __IO uint32_t TBCT; /**< Tx Buffer Control Register, offset: 0x158 */ 101 __I uint32_t SR; /**< Status Register, offset: 0x15C */ 102 __IO uint32_t FR; /**< Flag Register, offset: 0x160 */ 103 __IO uint32_t RSER; /**< Interrupt and DMA Request Select and Enable Register, offset: 0x164 */ 104 __I uint32_t SPNDST; /**< Sequence Suspend Status Register, offset: 0x168 */ 105 __O uint32_t SPTRCLR; /**< Sequence Pointer Clear Register, offset: 0x16C */ 106 uint8_t RESERVED_4[16]; 107 __IO uint32_t SFA1AD; /**< Serial Flash A1 Top Address, offset: 0x180 */ 108 __IO uint32_t SFA2AD; /**< Serial Flash A2 Top Address, offset: 0x184 */ 109 __IO uint32_t SFB1AD; /**< Serial Flash B1 Top Address, offset: 0x188 */ 110 __IO uint32_t SFB2AD; /**< Serial Flash B2 Top Address, offset: 0x18C */ 111 uint8_t RESERVED_5[112]; 112 __I uint32_t RBDR[QuadSPI_RBDR_COUNT]; /**< RX Buffer Data Register, array offset: 0x200, array step: 0x4 */ 113 uint8_t RESERVED_6[128]; 114 __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x300 */ 115 __IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x304 */ 116 uint8_t RESERVED_7[8]; 117 __IO uint32_t LUT[QuadSPI_LUT_COUNT]; /**< Look-up Table register, array offset: 0x310, array step: 0x4 */ 118 } QuadSPI_Type, *QuadSPI_MemMapPtr; 119 120 /** Number of instances of the QuadSPI module. */ 121 #define QuadSPI_INSTANCE_COUNT (1u) 122 123 /* QuadSPI - Peripheral instance base addresses */ 124 /** Peripheral QuadSPI base address */ 125 #define IP_QuadSPI_BASE (0x40076000u) 126 /** Peripheral QuadSPI base pointer */ 127 #define IP_QuadSPI ((QuadSPI_Type *)IP_QuadSPI_BASE) 128 /** Array initializer of QuadSPI peripheral base addresses */ 129 #define IP_QuadSPI_BASE_ADDRS { IP_QuadSPI_BASE } 130 /** Array initializer of QuadSPI peripheral base pointers */ 131 #define IP_QuadSPI_BASE_PTRS { IP_QuadSPI } 132 133 /* ---------------------------------------------------------------------------- 134 -- QuadSPI Register Masks 135 ---------------------------------------------------------------------------- */ 136 137 /*! 138 * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks 139 * @{ 140 */ 141 142 /*! @name MCR - Module Configuration Register */ 143 /*! @{ */ 144 145 #define QuadSPI_MCR_SWRSTSD_MASK (0x1U) 146 #define QuadSPI_MCR_SWRSTSD_SHIFT (0U) 147 #define QuadSPI_MCR_SWRSTSD_WIDTH (1U) 148 #define QuadSPI_MCR_SWRSTSD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTSD_SHIFT)) & QuadSPI_MCR_SWRSTSD_MASK) 149 150 #define QuadSPI_MCR_SWRSTHD_MASK (0x2U) 151 #define QuadSPI_MCR_SWRSTHD_SHIFT (1U) 152 #define QuadSPI_MCR_SWRSTHD_WIDTH (1U) 153 #define QuadSPI_MCR_SWRSTHD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK) 154 155 #define QuadSPI_MCR_END_CFG_MASK (0xCU) 156 #define QuadSPI_MCR_END_CFG_SHIFT (2U) 157 #define QuadSPI_MCR_END_CFG_WIDTH (2U) 158 #define QuadSPI_MCR_END_CFG(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_END_CFG_SHIFT)) & QuadSPI_MCR_END_CFG_MASK) 159 160 #define QuadSPI_MCR_DQS_OUT_EN_MASK (0x10U) 161 #define QuadSPI_MCR_DQS_OUT_EN_SHIFT (4U) 162 #define QuadSPI_MCR_DQS_OUT_EN_WIDTH (1U) 163 #define QuadSPI_MCR_DQS_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_OUT_EN_SHIFT)) & QuadSPI_MCR_DQS_OUT_EN_MASK) 164 165 #define QuadSPI_MCR_DQS_LAT_EN_MASK (0x20U) 166 #define QuadSPI_MCR_DQS_LAT_EN_SHIFT (5U) 167 #define QuadSPI_MCR_DQS_LAT_EN_WIDTH (1U) 168 #define QuadSPI_MCR_DQS_LAT_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_LAT_EN_SHIFT)) & QuadSPI_MCR_DQS_LAT_EN_MASK) 169 170 #define QuadSPI_MCR_DQS_EN_MASK (0x40U) 171 #define QuadSPI_MCR_DQS_EN_SHIFT (6U) 172 #define QuadSPI_MCR_DQS_EN_WIDTH (1U) 173 #define QuadSPI_MCR_DQS_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_EN_SHIFT)) & QuadSPI_MCR_DQS_EN_MASK) 174 175 #define QuadSPI_MCR_DDR_EN_MASK (0x80U) 176 #define QuadSPI_MCR_DDR_EN_SHIFT (7U) 177 #define QuadSPI_MCR_DDR_EN_WIDTH (1U) 178 #define QuadSPI_MCR_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DDR_EN_SHIFT)) & QuadSPI_MCR_DDR_EN_MASK) 179 180 #define QuadSPI_MCR_VAR_LAT_EN_MASK (0x100U) 181 #define QuadSPI_MCR_VAR_LAT_EN_SHIFT (8U) 182 #define QuadSPI_MCR_VAR_LAT_EN_WIDTH (1U) 183 #define QuadSPI_MCR_VAR_LAT_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_VAR_LAT_EN_SHIFT)) & QuadSPI_MCR_VAR_LAT_EN_MASK) 184 185 #define QuadSPI_MCR_CLR_RXF_MASK (0x400U) 186 #define QuadSPI_MCR_CLR_RXF_SHIFT (10U) 187 #define QuadSPI_MCR_CLR_RXF_WIDTH (1U) 188 #define QuadSPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_RXF_SHIFT)) & QuadSPI_MCR_CLR_RXF_MASK) 189 190 #define QuadSPI_MCR_CLR_TXF_MASK (0x800U) 191 #define QuadSPI_MCR_CLR_TXF_SHIFT (11U) 192 #define QuadSPI_MCR_CLR_TXF_WIDTH (1U) 193 #define QuadSPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_TXF_SHIFT)) & QuadSPI_MCR_CLR_TXF_MASK) 194 195 #define QuadSPI_MCR_MDIS_MASK (0x4000U) 196 #define QuadSPI_MCR_MDIS_SHIFT (14U) 197 #define QuadSPI_MCR_MDIS_WIDTH (1U) 198 #define QuadSPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_MDIS_SHIFT)) & QuadSPI_MCR_MDIS_MASK) 199 200 #define QuadSPI_MCR_DOZE_MASK (0x8000U) 201 #define QuadSPI_MCR_DOZE_SHIFT (15U) 202 #define QuadSPI_MCR_DOZE_WIDTH (1U) 203 #define QuadSPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DOZE_SHIFT)) & QuadSPI_MCR_DOZE_MASK) 204 205 #define QuadSPI_MCR_ISD2FA_MASK (0x10000U) 206 #define QuadSPI_MCR_ISD2FA_SHIFT (16U) 207 #define QuadSPI_MCR_ISD2FA_WIDTH (1U) 208 #define QuadSPI_MCR_ISD2FA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_ISD2FA_SHIFT)) & QuadSPI_MCR_ISD2FA_MASK) 209 210 #define QuadSPI_MCR_ISD3FA_MASK (0x20000U) 211 #define QuadSPI_MCR_ISD3FA_SHIFT (17U) 212 #define QuadSPI_MCR_ISD3FA_WIDTH (1U) 213 #define QuadSPI_MCR_ISD3FA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_ISD3FA_SHIFT)) & QuadSPI_MCR_ISD3FA_MASK) 214 215 #define QuadSPI_MCR_ISD2FB_MASK (0x40000U) 216 #define QuadSPI_MCR_ISD2FB_SHIFT (18U) 217 #define QuadSPI_MCR_ISD2FB_WIDTH (1U) 218 #define QuadSPI_MCR_ISD2FB(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_ISD2FB_SHIFT)) & QuadSPI_MCR_ISD2FB_MASK) 219 220 #define QuadSPI_MCR_ISD3FB_MASK (0x80000U) 221 #define QuadSPI_MCR_ISD3FB_SHIFT (19U) 222 #define QuadSPI_MCR_ISD3FB_WIDTH (1U) 223 #define QuadSPI_MCR_ISD3FB(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_ISD3FB_SHIFT)) & QuadSPI_MCR_ISD3FB_MASK) 224 225 #define QuadSPI_MCR_SCLKCFG_MASK (0xFF000000U) 226 #define QuadSPI_MCR_SCLKCFG_SHIFT (24U) 227 #define QuadSPI_MCR_SCLKCFG_WIDTH (8U) 228 #define QuadSPI_MCR_SCLKCFG(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SCLKCFG_SHIFT)) & QuadSPI_MCR_SCLKCFG_MASK) 229 /*! @} */ 230 231 /*! @name IPCR - IP Configuration Register */ 232 /*! @{ */ 233 234 #define QuadSPI_IPCR_IDATSZ_MASK (0xFFFFU) 235 #define QuadSPI_IPCR_IDATSZ_SHIFT (0U) 236 #define QuadSPI_IPCR_IDATSZ_WIDTH (16U) 237 #define QuadSPI_IPCR_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_IDATSZ_SHIFT)) & QuadSPI_IPCR_IDATSZ_MASK) 238 239 #define QuadSPI_IPCR_SEQID_MASK (0xF000000U) 240 #define QuadSPI_IPCR_SEQID_SHIFT (24U) 241 #define QuadSPI_IPCR_SEQID_WIDTH (4U) 242 #define QuadSPI_IPCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK) 243 /*! @} */ 244 245 /*! @name FLSHCR - Flash Configuration Register */ 246 /*! @{ */ 247 248 #define QuadSPI_FLSHCR_TCSS_MASK (0xFU) 249 #define QuadSPI_FLSHCR_TCSS_SHIFT (0U) 250 #define QuadSPI_FLSHCR_TCSS_WIDTH (4U) 251 #define QuadSPI_FLSHCR_TCSS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSS_SHIFT)) & QuadSPI_FLSHCR_TCSS_MASK) 252 253 #define QuadSPI_FLSHCR_TCSH_MASK (0xF00U) 254 #define QuadSPI_FLSHCR_TCSH_SHIFT (8U) 255 #define QuadSPI_FLSHCR_TCSH_WIDTH (4U) 256 #define QuadSPI_FLSHCR_TCSH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSH_SHIFT)) & QuadSPI_FLSHCR_TCSH_MASK) 257 258 #define QuadSPI_FLSHCR_TDH_MASK (0x30000U) 259 #define QuadSPI_FLSHCR_TDH_SHIFT (16U) 260 #define QuadSPI_FLSHCR_TDH_WIDTH (2U) 261 #define QuadSPI_FLSHCR_TDH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK) 262 /*! @} */ 263 264 /*! @name BUF0CR - Buffer0 Configuration Register */ 265 /*! @{ */ 266 267 #define QuadSPI_BUF0CR_MSTRID_MASK (0xFU) 268 #define QuadSPI_BUF0CR_MSTRID_SHIFT (0U) 269 #define QuadSPI_BUF0CR_MSTRID_WIDTH (4U) 270 #define QuadSPI_BUF0CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_MSTRID_SHIFT)) & QuadSPI_BUF0CR_MSTRID_MASK) 271 272 #define QuadSPI_BUF0CR_ADATSZ_MASK (0xFF00U) 273 #define QuadSPI_BUF0CR_ADATSZ_SHIFT (8U) 274 #define QuadSPI_BUF0CR_ADATSZ_WIDTH (8U) 275 #define QuadSPI_BUF0CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_ADATSZ_SHIFT)) & QuadSPI_BUF0CR_ADATSZ_MASK) 276 277 #define QuadSPI_BUF0CR_HP_EN_MASK (0x80000000U) 278 #define QuadSPI_BUF0CR_HP_EN_SHIFT (31U) 279 #define QuadSPI_BUF0CR_HP_EN_WIDTH (1U) 280 #define QuadSPI_BUF0CR_HP_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_HP_EN_SHIFT)) & QuadSPI_BUF0CR_HP_EN_MASK) 281 /*! @} */ 282 283 /*! @name BUF1CR - Buffer1 Configuration Register */ 284 /*! @{ */ 285 286 #define QuadSPI_BUF1CR_MSTRID_MASK (0xFU) 287 #define QuadSPI_BUF1CR_MSTRID_SHIFT (0U) 288 #define QuadSPI_BUF1CR_MSTRID_WIDTH (4U) 289 #define QuadSPI_BUF1CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_MSTRID_SHIFT)) & QuadSPI_BUF1CR_MSTRID_MASK) 290 291 #define QuadSPI_BUF1CR_ADATSZ_MASK (0xFF00U) 292 #define QuadSPI_BUF1CR_ADATSZ_SHIFT (8U) 293 #define QuadSPI_BUF1CR_ADATSZ_WIDTH (8U) 294 #define QuadSPI_BUF1CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_ADATSZ_SHIFT)) & QuadSPI_BUF1CR_ADATSZ_MASK) 295 /*! @} */ 296 297 /*! @name BUF2CR - Buffer2 Configuration Register */ 298 /*! @{ */ 299 300 #define QuadSPI_BUF2CR_MSTRID_MASK (0xFU) 301 #define QuadSPI_BUF2CR_MSTRID_SHIFT (0U) 302 #define QuadSPI_BUF2CR_MSTRID_WIDTH (4U) 303 #define QuadSPI_BUF2CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_MSTRID_SHIFT)) & QuadSPI_BUF2CR_MSTRID_MASK) 304 305 #define QuadSPI_BUF2CR_ADATSZ_MASK (0xFF00U) 306 #define QuadSPI_BUF2CR_ADATSZ_SHIFT (8U) 307 #define QuadSPI_BUF2CR_ADATSZ_WIDTH (8U) 308 #define QuadSPI_BUF2CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_ADATSZ_SHIFT)) & QuadSPI_BUF2CR_ADATSZ_MASK) 309 /*! @} */ 310 311 /*! @name BUF3CR - Buffer3 Configuration Register */ 312 /*! @{ */ 313 314 #define QuadSPI_BUF3CR_MSTRID_MASK (0xFU) 315 #define QuadSPI_BUF3CR_MSTRID_SHIFT (0U) 316 #define QuadSPI_BUF3CR_MSTRID_WIDTH (4U) 317 #define QuadSPI_BUF3CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_MSTRID_SHIFT)) & QuadSPI_BUF3CR_MSTRID_MASK) 318 319 #define QuadSPI_BUF3CR_ADATSZ_MASK (0xFF00U) 320 #define QuadSPI_BUF3CR_ADATSZ_SHIFT (8U) 321 #define QuadSPI_BUF3CR_ADATSZ_WIDTH (8U) 322 #define QuadSPI_BUF3CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ADATSZ_SHIFT)) & QuadSPI_BUF3CR_ADATSZ_MASK) 323 324 #define QuadSPI_BUF3CR_ALLMST_MASK (0x80000000U) 325 #define QuadSPI_BUF3CR_ALLMST_SHIFT (31U) 326 #define QuadSPI_BUF3CR_ALLMST_WIDTH (1U) 327 #define QuadSPI_BUF3CR_ALLMST(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ALLMST_SHIFT)) & QuadSPI_BUF3CR_ALLMST_MASK) 328 /*! @} */ 329 330 /*! @name BFGENCR - Buffer Generic Configuration Register */ 331 /*! @{ */ 332 333 #define QuadSPI_BFGENCR_SEQID_MASK (0xF000U) 334 #define QuadSPI_BFGENCR_SEQID_SHIFT (12U) 335 #define QuadSPI_BFGENCR_SEQID_WIDTH (4U) 336 #define QuadSPI_BFGENCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_SEQID_SHIFT)) & QuadSPI_BFGENCR_SEQID_MASK) 337 /*! @} */ 338 339 /*! @name SOCCR - SOC Configuration Register */ 340 /*! @{ */ 341 342 #define QuadSPI_SOCCR_SOCCFG_MASK (0xFFFFFFFFU) 343 #define QuadSPI_SOCCR_SOCCFG_SHIFT (0U) 344 #define QuadSPI_SOCCR_SOCCFG_WIDTH (32U) 345 #define QuadSPI_SOCCR_SOCCFG(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_SOCCFG_SHIFT)) & QuadSPI_SOCCR_SOCCFG_MASK) 346 /*! @} */ 347 348 /*! @name BUF0IND - Buffer0 Top Index Register */ 349 /*! @{ */ 350 351 #define QuadSPI_BUF0IND_TPINDX0_MASK (0xFFFFFFF8U) 352 #define QuadSPI_BUF0IND_TPINDX0_SHIFT (3U) 353 #define QuadSPI_BUF0IND_TPINDX0_WIDTH (29U) 354 #define QuadSPI_BUF0IND_TPINDX0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0IND_TPINDX0_SHIFT)) & QuadSPI_BUF0IND_TPINDX0_MASK) 355 /*! @} */ 356 357 /*! @name BUF1IND - Buffer1 Top Index Register */ 358 /*! @{ */ 359 360 #define QuadSPI_BUF1IND_TPINDX1_MASK (0xFFFFFFF8U) 361 #define QuadSPI_BUF1IND_TPINDX1_SHIFT (3U) 362 #define QuadSPI_BUF1IND_TPINDX1_WIDTH (29U) 363 #define QuadSPI_BUF1IND_TPINDX1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1IND_TPINDX1_SHIFT)) & QuadSPI_BUF1IND_TPINDX1_MASK) 364 /*! @} */ 365 366 /*! @name BUF2IND - Buffer2 Top Index Register */ 367 /*! @{ */ 368 369 #define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U) 370 #define QuadSPI_BUF2IND_TPINDX2_SHIFT (3U) 371 #define QuadSPI_BUF2IND_TPINDX2_WIDTH (29U) 372 #define QuadSPI_BUF2IND_TPINDX2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK) 373 /*! @} */ 374 375 /*! @name SFAR - Serial Flash Address Register */ 376 /*! @{ */ 377 378 #define QuadSPI_SFAR_SFADR_MASK (0xFFFFFFFFU) 379 #define QuadSPI_SFAR_SFADR_SHIFT (0U) 380 #define QuadSPI_SFAR_SFADR_WIDTH (32U) 381 #define QuadSPI_SFAR_SFADR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFAR_SFADR_SHIFT)) & QuadSPI_SFAR_SFADR_MASK) 382 /*! @} */ 383 384 /*! @name SFACR - Serial Flash Address Configuration Register */ 385 /*! @{ */ 386 387 #define QuadSPI_SFACR_CAS_MASK (0xFU) 388 #define QuadSPI_SFACR_CAS_SHIFT (0U) 389 #define QuadSPI_SFACR_CAS_WIDTH (4U) 390 #define QuadSPI_SFACR_CAS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFACR_CAS_SHIFT)) & QuadSPI_SFACR_CAS_MASK) 391 392 #define QuadSPI_SFACR_WA_MASK (0x10000U) 393 #define QuadSPI_SFACR_WA_SHIFT (16U) 394 #define QuadSPI_SFACR_WA_WIDTH (1U) 395 #define QuadSPI_SFACR_WA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFACR_WA_SHIFT)) & QuadSPI_SFACR_WA_MASK) 396 /*! @} */ 397 398 /*! @name SMPR - Sampling Register */ 399 /*! @{ */ 400 401 #define QuadSPI_SMPR_FSPHS_MASK (0x20U) 402 #define QuadSPI_SMPR_FSPHS_SHIFT (5U) 403 #define QuadSPI_SMPR_FSPHS_WIDTH (1U) 404 #define QuadSPI_SMPR_FSPHS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_FSPHS_SHIFT)) & QuadSPI_SMPR_FSPHS_MASK) 405 406 #define QuadSPI_SMPR_FSDLY_MASK (0x40U) 407 #define QuadSPI_SMPR_FSDLY_SHIFT (6U) 408 #define QuadSPI_SMPR_FSDLY_WIDTH (1U) 409 #define QuadSPI_SMPR_FSDLY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_FSDLY_SHIFT)) & QuadSPI_SMPR_FSDLY_MASK) 410 /*! @} */ 411 412 /*! @name RBSR - RX Buffer Status Register */ 413 /*! @{ */ 414 415 #define QuadSPI_RBSR_RDBFL_MASK (0x3F00U) 416 #define QuadSPI_RBSR_RDBFL_SHIFT (8U) 417 #define QuadSPI_RBSR_RDBFL_WIDTH (6U) 418 #define QuadSPI_RBSR_RDBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDBFL_SHIFT)) & QuadSPI_RBSR_RDBFL_MASK) 419 420 #define QuadSPI_RBSR_RDCTR_MASK (0xFFFF0000U) 421 #define QuadSPI_RBSR_RDCTR_SHIFT (16U) 422 #define QuadSPI_RBSR_RDCTR_WIDTH (16U) 423 #define QuadSPI_RBSR_RDCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDCTR_SHIFT)) & QuadSPI_RBSR_RDCTR_MASK) 424 /*! @} */ 425 426 /*! @name RBCT - RX Buffer Control Register */ 427 /*! @{ */ 428 429 #define QuadSPI_RBCT_WMRK_MASK (0x1FU) 430 #define QuadSPI_RBCT_WMRK_SHIFT (0U) 431 #define QuadSPI_RBCT_WMRK_WIDTH (5U) 432 #define QuadSPI_RBCT_WMRK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_WMRK_SHIFT)) & QuadSPI_RBCT_WMRK_MASK) 433 434 #define QuadSPI_RBCT_RXBRD_MASK (0x100U) 435 #define QuadSPI_RBCT_RXBRD_SHIFT (8U) 436 #define QuadSPI_RBCT_RXBRD_WIDTH (1U) 437 #define QuadSPI_RBCT_RXBRD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_RXBRD_SHIFT)) & QuadSPI_RBCT_RXBRD_MASK) 438 /*! @} */ 439 440 /*! @name TBSR - TX Buffer Status Register */ 441 /*! @{ */ 442 443 #define QuadSPI_TBSR_TRBFL_MASK (0x3F00U) 444 #define QuadSPI_TBSR_TRBFL_SHIFT (8U) 445 #define QuadSPI_TBSR_TRBFL_WIDTH (6U) 446 #define QuadSPI_TBSR_TRBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRBFL_SHIFT)) & QuadSPI_TBSR_TRBFL_MASK) 447 448 #define QuadSPI_TBSR_TRCTR_MASK (0xFFFF0000U) 449 #define QuadSPI_TBSR_TRCTR_SHIFT (16U) 450 #define QuadSPI_TBSR_TRCTR_WIDTH (16U) 451 #define QuadSPI_TBSR_TRCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRCTR_SHIFT)) & QuadSPI_TBSR_TRCTR_MASK) 452 /*! @} */ 453 454 /*! @name TBDR - TX Buffer Data Register */ 455 /*! @{ */ 456 457 #define QuadSPI_TBDR_TXDATA_MASK (0xFFFFFFFFU) 458 #define QuadSPI_TBDR_TXDATA_SHIFT (0U) 459 #define QuadSPI_TBDR_TXDATA_WIDTH (32U) 460 #define QuadSPI_TBDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBDR_TXDATA_SHIFT)) & QuadSPI_TBDR_TXDATA_MASK) 461 /*! @} */ 462 463 /*! @name TBCT - Tx Buffer Control Register */ 464 /*! @{ */ 465 466 #define QuadSPI_TBCT_WMRK_MASK (0x1FU) 467 #define QuadSPI_TBCT_WMRK_SHIFT (0U) 468 #define QuadSPI_TBCT_WMRK_WIDTH (5U) 469 #define QuadSPI_TBCT_WMRK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBCT_WMRK_SHIFT)) & QuadSPI_TBCT_WMRK_MASK) 470 /*! @} */ 471 472 /*! @name SR - Status Register */ 473 /*! @{ */ 474 475 #define QuadSPI_SR_BUSY_MASK (0x1U) 476 #define QuadSPI_SR_BUSY_SHIFT (0U) 477 #define QuadSPI_SR_BUSY_WIDTH (1U) 478 #define QuadSPI_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_BUSY_SHIFT)) & QuadSPI_SR_BUSY_MASK) 479 480 #define QuadSPI_SR_IP_ACC_MASK (0x2U) 481 #define QuadSPI_SR_IP_ACC_SHIFT (1U) 482 #define QuadSPI_SR_IP_ACC_WIDTH (1U) 483 #define QuadSPI_SR_IP_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_IP_ACC_SHIFT)) & QuadSPI_SR_IP_ACC_MASK) 484 485 #define QuadSPI_SR_AHB_ACC_MASK (0x4U) 486 #define QuadSPI_SR_AHB_ACC_SHIFT (2U) 487 #define QuadSPI_SR_AHB_ACC_WIDTH (1U) 488 #define QuadSPI_SR_AHB_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB_ACC_SHIFT)) & QuadSPI_SR_AHB_ACC_MASK) 489 490 #define QuadSPI_SR_AHBTRN_MASK (0x40U) 491 #define QuadSPI_SR_AHBTRN_SHIFT (6U) 492 #define QuadSPI_SR_AHBTRN_WIDTH (1U) 493 #define QuadSPI_SR_AHBTRN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBTRN_SHIFT)) & QuadSPI_SR_AHBTRN_MASK) 494 495 #define QuadSPI_SR_AHB0NE_MASK (0x80U) 496 #define QuadSPI_SR_AHB0NE_SHIFT (7U) 497 #define QuadSPI_SR_AHB0NE_WIDTH (1U) 498 #define QuadSPI_SR_AHB0NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK) 499 500 #define QuadSPI_SR_AHB1NE_MASK (0x100U) 501 #define QuadSPI_SR_AHB1NE_SHIFT (8U) 502 #define QuadSPI_SR_AHB1NE_WIDTH (1U) 503 #define QuadSPI_SR_AHB1NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1NE_SHIFT)) & QuadSPI_SR_AHB1NE_MASK) 504 505 #define QuadSPI_SR_AHB2NE_MASK (0x200U) 506 #define QuadSPI_SR_AHB2NE_SHIFT (9U) 507 #define QuadSPI_SR_AHB2NE_WIDTH (1U) 508 #define QuadSPI_SR_AHB2NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2NE_SHIFT)) & QuadSPI_SR_AHB2NE_MASK) 509 510 #define QuadSPI_SR_AHB3NE_MASK (0x400U) 511 #define QuadSPI_SR_AHB3NE_SHIFT (10U) 512 #define QuadSPI_SR_AHB3NE_WIDTH (1U) 513 #define QuadSPI_SR_AHB3NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3NE_SHIFT)) & QuadSPI_SR_AHB3NE_MASK) 514 515 #define QuadSPI_SR_AHB0FUL_MASK (0x800U) 516 #define QuadSPI_SR_AHB0FUL_SHIFT (11U) 517 #define QuadSPI_SR_AHB0FUL_WIDTH (1U) 518 #define QuadSPI_SR_AHB0FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK) 519 520 #define QuadSPI_SR_AHB1FUL_MASK (0x1000U) 521 #define QuadSPI_SR_AHB1FUL_SHIFT (12U) 522 #define QuadSPI_SR_AHB1FUL_WIDTH (1U) 523 #define QuadSPI_SR_AHB1FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1FUL_SHIFT)) & QuadSPI_SR_AHB1FUL_MASK) 524 525 #define QuadSPI_SR_AHB2FUL_MASK (0x2000U) 526 #define QuadSPI_SR_AHB2FUL_SHIFT (13U) 527 #define QuadSPI_SR_AHB2FUL_WIDTH (1U) 528 #define QuadSPI_SR_AHB2FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2FUL_SHIFT)) & QuadSPI_SR_AHB2FUL_MASK) 529 530 #define QuadSPI_SR_AHB3FUL_MASK (0x4000U) 531 #define QuadSPI_SR_AHB3FUL_SHIFT (14U) 532 #define QuadSPI_SR_AHB3FUL_WIDTH (1U) 533 #define QuadSPI_SR_AHB3FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3FUL_SHIFT)) & QuadSPI_SR_AHB3FUL_MASK) 534 535 #define QuadSPI_SR_RXWE_MASK (0x10000U) 536 #define QuadSPI_SR_RXWE_SHIFT (16U) 537 #define QuadSPI_SR_RXWE_WIDTH (1U) 538 #define QuadSPI_SR_RXWE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK) 539 540 #define QuadSPI_SR_RXFULL_MASK (0x80000U) 541 #define QuadSPI_SR_RXFULL_SHIFT (19U) 542 #define QuadSPI_SR_RXFULL_WIDTH (1U) 543 #define QuadSPI_SR_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK) 544 545 #define QuadSPI_SR_RXDMA_MASK (0x800000U) 546 #define QuadSPI_SR_RXDMA_SHIFT (23U) 547 #define QuadSPI_SR_RXDMA_WIDTH (1U) 548 #define QuadSPI_SR_RXDMA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXDMA_SHIFT)) & QuadSPI_SR_RXDMA_MASK) 549 550 #define QuadSPI_SR_TXEDA_MASK (0x1000000U) 551 #define QuadSPI_SR_TXEDA_SHIFT (24U) 552 #define QuadSPI_SR_TXEDA_WIDTH (1U) 553 #define QuadSPI_SR_TXEDA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXEDA_SHIFT)) & QuadSPI_SR_TXEDA_MASK) 554 555 #define QuadSPI_SR_TXWA_MASK (0x2000000U) 556 #define QuadSPI_SR_TXWA_SHIFT (25U) 557 #define QuadSPI_SR_TXWA_WIDTH (1U) 558 #define QuadSPI_SR_TXWA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXWA_SHIFT)) & QuadSPI_SR_TXWA_MASK) 559 560 #define QuadSPI_SR_TXDMA_MASK (0x4000000U) 561 #define QuadSPI_SR_TXDMA_SHIFT (26U) 562 #define QuadSPI_SR_TXDMA_WIDTH (1U) 563 #define QuadSPI_SR_TXDMA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXDMA_SHIFT)) & QuadSPI_SR_TXDMA_MASK) 564 565 #define QuadSPI_SR_TXFULL_MASK (0x8000000U) 566 #define QuadSPI_SR_TXFULL_SHIFT (27U) 567 #define QuadSPI_SR_TXFULL_WIDTH (1U) 568 #define QuadSPI_SR_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK) 569 /*! @} */ 570 571 /*! @name FR - Flag Register */ 572 /*! @{ */ 573 574 #define QuadSPI_FR_TFF_MASK (0x1U) 575 #define QuadSPI_FR_TFF_SHIFT (0U) 576 #define QuadSPI_FR_TFF_WIDTH (1U) 577 #define QuadSPI_FR_TFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TFF_SHIFT)) & QuadSPI_FR_TFF_MASK) 578 579 #define QuadSPI_FR_IPIEF_MASK (0x40U) 580 #define QuadSPI_FR_IPIEF_SHIFT (6U) 581 #define QuadSPI_FR_IPIEF_WIDTH (1U) 582 #define QuadSPI_FR_IPIEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPIEF_SHIFT)) & QuadSPI_FR_IPIEF_MASK) 583 584 #define QuadSPI_FR_IPAEF_MASK (0x80U) 585 #define QuadSPI_FR_IPAEF_SHIFT (7U) 586 #define QuadSPI_FR_IPAEF_WIDTH (1U) 587 #define QuadSPI_FR_IPAEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPAEF_SHIFT)) & QuadSPI_FR_IPAEF_MASK) 588 589 #define QuadSPI_FR_ABOF_MASK (0x1000U) 590 #define QuadSPI_FR_ABOF_SHIFT (12U) 591 #define QuadSPI_FR_ABOF_WIDTH (1U) 592 #define QuadSPI_FR_ABOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABOF_SHIFT)) & QuadSPI_FR_ABOF_MASK) 593 594 #define QuadSPI_FR_AIBSEF_MASK (0x2000U) 595 #define QuadSPI_FR_AIBSEF_SHIFT (13U) 596 #define QuadSPI_FR_AIBSEF_WIDTH (1U) 597 #define QuadSPI_FR_AIBSEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AIBSEF_SHIFT)) & QuadSPI_FR_AIBSEF_MASK) 598 599 #define QuadSPI_FR_AITEF_MASK (0x4000U) 600 #define QuadSPI_FR_AITEF_SHIFT (14U) 601 #define QuadSPI_FR_AITEF_WIDTH (1U) 602 #define QuadSPI_FR_AITEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AITEF_SHIFT)) & QuadSPI_FR_AITEF_MASK) 603 604 #define QuadSPI_FR_ABSEF_MASK (0x8000U) 605 #define QuadSPI_FR_ABSEF_SHIFT (15U) 606 #define QuadSPI_FR_ABSEF_WIDTH (1U) 607 #define QuadSPI_FR_ABSEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK) 608 609 #define QuadSPI_FR_RBDF_MASK (0x10000U) 610 #define QuadSPI_FR_RBDF_SHIFT (16U) 611 #define QuadSPI_FR_RBDF_WIDTH (1U) 612 #define QuadSPI_FR_RBDF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBDF_SHIFT)) & QuadSPI_FR_RBDF_MASK) 613 614 #define QuadSPI_FR_RBOF_MASK (0x20000U) 615 #define QuadSPI_FR_RBOF_SHIFT (17U) 616 #define QuadSPI_FR_RBOF_WIDTH (1U) 617 #define QuadSPI_FR_RBOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBOF_SHIFT)) & QuadSPI_FR_RBOF_MASK) 618 619 #define QuadSPI_FR_ILLINE_MASK (0x800000U) 620 #define QuadSPI_FR_ILLINE_SHIFT (23U) 621 #define QuadSPI_FR_ILLINE_WIDTH (1U) 622 #define QuadSPI_FR_ILLINE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK) 623 624 #define QuadSPI_FR_TBUF_MASK (0x4000000U) 625 #define QuadSPI_FR_TBUF_SHIFT (26U) 626 #define QuadSPI_FR_TBUF_WIDTH (1U) 627 #define QuadSPI_FR_TBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBUF_SHIFT)) & QuadSPI_FR_TBUF_MASK) 628 629 #define QuadSPI_FR_TBFF_MASK (0x8000000U) 630 #define QuadSPI_FR_TBFF_SHIFT (27U) 631 #define QuadSPI_FR_TBFF_WIDTH (1U) 632 #define QuadSPI_FR_TBFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBFF_SHIFT)) & QuadSPI_FR_TBFF_MASK) 633 /*! @} */ 634 635 /*! @name RSER - Interrupt and DMA Request Select and Enable Register */ 636 /*! @{ */ 637 638 #define QuadSPI_RSER_TFIE_MASK (0x1U) 639 #define QuadSPI_RSER_TFIE_SHIFT (0U) 640 #define QuadSPI_RSER_TFIE_WIDTH (1U) 641 #define QuadSPI_RSER_TFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TFIE_SHIFT)) & QuadSPI_RSER_TFIE_MASK) 642 643 #define QuadSPI_RSER_IPIEIE_MASK (0x40U) 644 #define QuadSPI_RSER_IPIEIE_SHIFT (6U) 645 #define QuadSPI_RSER_IPIEIE_WIDTH (1U) 646 #define QuadSPI_RSER_IPIEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPIEIE_SHIFT)) & QuadSPI_RSER_IPIEIE_MASK) 647 648 #define QuadSPI_RSER_IPAEIE_MASK (0x80U) 649 #define QuadSPI_RSER_IPAEIE_SHIFT (7U) 650 #define QuadSPI_RSER_IPAEIE_WIDTH (1U) 651 #define QuadSPI_RSER_IPAEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPAEIE_SHIFT)) & QuadSPI_RSER_IPAEIE_MASK) 652 653 #define QuadSPI_RSER_ABOIE_MASK (0x1000U) 654 #define QuadSPI_RSER_ABOIE_SHIFT (12U) 655 #define QuadSPI_RSER_ABOIE_WIDTH (1U) 656 #define QuadSPI_RSER_ABOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABOIE_SHIFT)) & QuadSPI_RSER_ABOIE_MASK) 657 658 #define QuadSPI_RSER_AIBSIE_MASK (0x2000U) 659 #define QuadSPI_RSER_AIBSIE_SHIFT (13U) 660 #define QuadSPI_RSER_AIBSIE_WIDTH (1U) 661 #define QuadSPI_RSER_AIBSIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_AIBSIE_SHIFT)) & QuadSPI_RSER_AIBSIE_MASK) 662 663 #define QuadSPI_RSER_AITIE_MASK (0x4000U) 664 #define QuadSPI_RSER_AITIE_SHIFT (14U) 665 #define QuadSPI_RSER_AITIE_WIDTH (1U) 666 #define QuadSPI_RSER_AITIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_AITIE_SHIFT)) & QuadSPI_RSER_AITIE_MASK) 667 668 #define QuadSPI_RSER_ABSEIE_MASK (0x8000U) 669 #define QuadSPI_RSER_ABSEIE_SHIFT (15U) 670 #define QuadSPI_RSER_ABSEIE_WIDTH (1U) 671 #define QuadSPI_RSER_ABSEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABSEIE_SHIFT)) & QuadSPI_RSER_ABSEIE_MASK) 672 673 #define QuadSPI_RSER_RBDIE_MASK (0x10000U) 674 #define QuadSPI_RSER_RBDIE_SHIFT (16U) 675 #define QuadSPI_RSER_RBDIE_WIDTH (1U) 676 #define QuadSPI_RSER_RBDIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDIE_SHIFT)) & QuadSPI_RSER_RBDIE_MASK) 677 678 #define QuadSPI_RSER_RBOIE_MASK (0x20000U) 679 #define QuadSPI_RSER_RBOIE_SHIFT (17U) 680 #define QuadSPI_RSER_RBOIE_WIDTH (1U) 681 #define QuadSPI_RSER_RBOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBOIE_SHIFT)) & QuadSPI_RSER_RBOIE_MASK) 682 683 #define QuadSPI_RSER_RBDDE_MASK (0x200000U) 684 #define QuadSPI_RSER_RBDDE_SHIFT (21U) 685 #define QuadSPI_RSER_RBDDE_WIDTH (1U) 686 #define QuadSPI_RSER_RBDDE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDDE_SHIFT)) & QuadSPI_RSER_RBDDE_MASK) 687 688 #define QuadSPI_RSER_ILLINIE_MASK (0x800000U) 689 #define QuadSPI_RSER_ILLINIE_SHIFT (23U) 690 #define QuadSPI_RSER_ILLINIE_WIDTH (1U) 691 #define QuadSPI_RSER_ILLINIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ILLINIE_SHIFT)) & QuadSPI_RSER_ILLINIE_MASK) 692 693 #define QuadSPI_RSER_TBFDE_MASK (0x2000000U) 694 #define QuadSPI_RSER_TBFDE_SHIFT (25U) 695 #define QuadSPI_RSER_TBFDE_WIDTH (1U) 696 #define QuadSPI_RSER_TBFDE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFDE_SHIFT)) & QuadSPI_RSER_TBFDE_MASK) 697 698 #define QuadSPI_RSER_TBUIE_MASK (0x4000000U) 699 #define QuadSPI_RSER_TBUIE_SHIFT (26U) 700 #define QuadSPI_RSER_TBUIE_WIDTH (1U) 701 #define QuadSPI_RSER_TBUIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBUIE_SHIFT)) & QuadSPI_RSER_TBUIE_MASK) 702 703 #define QuadSPI_RSER_TBFIE_MASK (0x8000000U) 704 #define QuadSPI_RSER_TBFIE_SHIFT (27U) 705 #define QuadSPI_RSER_TBFIE_WIDTH (1U) 706 #define QuadSPI_RSER_TBFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFIE_SHIFT)) & QuadSPI_RSER_TBFIE_MASK) 707 /*! @} */ 708 709 /*! @name SPNDST - Sequence Suspend Status Register */ 710 /*! @{ */ 711 712 #define QuadSPI_SPNDST_SUSPND_MASK (0x1U) 713 #define QuadSPI_SPNDST_SUSPND_SHIFT (0U) 714 #define QuadSPI_SPNDST_SUSPND_WIDTH (1U) 715 #define QuadSPI_SPNDST_SUSPND(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SUSPND_SHIFT)) & QuadSPI_SPNDST_SUSPND_MASK) 716 717 #define QuadSPI_SPNDST_SPDBUF_MASK (0xC0U) 718 #define QuadSPI_SPNDST_SPDBUF_SHIFT (6U) 719 #define QuadSPI_SPNDST_SPDBUF_WIDTH (2U) 720 #define QuadSPI_SPNDST_SPDBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SPDBUF_SHIFT)) & QuadSPI_SPNDST_SPDBUF_MASK) 721 722 #define QuadSPI_SPNDST_DATLFT_MASK (0xFE00U) 723 #define QuadSPI_SPNDST_DATLFT_SHIFT (9U) 724 #define QuadSPI_SPNDST_DATLFT_WIDTH (7U) 725 #define QuadSPI_SPNDST_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_DATLFT_SHIFT)) & QuadSPI_SPNDST_DATLFT_MASK) 726 /*! @} */ 727 728 /*! @name SPTRCLR - Sequence Pointer Clear Register */ 729 /*! @{ */ 730 731 #define QuadSPI_SPTRCLR_BFPTRC_MASK (0x1U) 732 #define QuadSPI_SPTRCLR_BFPTRC_SHIFT (0U) 733 #define QuadSPI_SPTRCLR_BFPTRC_WIDTH (1U) 734 #define QuadSPI_SPTRCLR_BFPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_BFPTRC_SHIFT)) & QuadSPI_SPTRCLR_BFPTRC_MASK) 735 736 #define QuadSPI_SPTRCLR_IPPTRC_MASK (0x100U) 737 #define QuadSPI_SPTRCLR_IPPTRC_SHIFT (8U) 738 #define QuadSPI_SPTRCLR_IPPTRC_WIDTH (1U) 739 #define QuadSPI_SPTRCLR_IPPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_IPPTRC_SHIFT)) & QuadSPI_SPTRCLR_IPPTRC_MASK) 740 /*! @} */ 741 742 /*! @name SFA1AD - Serial Flash A1 Top Address */ 743 /*! @{ */ 744 745 #define QuadSPI_SFA1AD_TPADA1_MASK (0xFFFFFC00U) 746 #define QuadSPI_SFA1AD_TPADA1_SHIFT (10U) 747 #define QuadSPI_SFA1AD_TPADA1_WIDTH (22U) 748 #define QuadSPI_SFA1AD_TPADA1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA1AD_TPADA1_SHIFT)) & QuadSPI_SFA1AD_TPADA1_MASK) 749 /*! @} */ 750 751 /*! @name SFA2AD - Serial Flash A2 Top Address */ 752 /*! @{ */ 753 754 #define QuadSPI_SFA2AD_TPADA2_MASK (0xFFFFFC00U) 755 #define QuadSPI_SFA2AD_TPADA2_SHIFT (10U) 756 #define QuadSPI_SFA2AD_TPADA2_WIDTH (22U) 757 #define QuadSPI_SFA2AD_TPADA2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA2AD_TPADA2_SHIFT)) & QuadSPI_SFA2AD_TPADA2_MASK) 758 /*! @} */ 759 760 /*! @name SFB1AD - Serial Flash B1 Top Address */ 761 /*! @{ */ 762 763 #define QuadSPI_SFB1AD_TPADB1_MASK (0xFFFFFC00U) 764 #define QuadSPI_SFB1AD_TPADB1_SHIFT (10U) 765 #define QuadSPI_SFB1AD_TPADB1_WIDTH (22U) 766 #define QuadSPI_SFB1AD_TPADB1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB1AD_TPADB1_SHIFT)) & QuadSPI_SFB1AD_TPADB1_MASK) 767 /*! @} */ 768 769 /*! @name SFB2AD - Serial Flash B2 Top Address */ 770 /*! @{ */ 771 772 #define QuadSPI_SFB2AD_TPADB2_MASK (0xFFFFFC00U) 773 #define QuadSPI_SFB2AD_TPADB2_SHIFT (10U) 774 #define QuadSPI_SFB2AD_TPADB2_WIDTH (22U) 775 #define QuadSPI_SFB2AD_TPADB2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB2AD_TPADB2_SHIFT)) & QuadSPI_SFB2AD_TPADB2_MASK) 776 /*! @} */ 777 778 /*! @name RBDR - RX Buffer Data Register */ 779 /*! @{ */ 780 781 #define QuadSPI_RBDR_RXDATA_MASK (0xFFFFFFFFU) 782 #define QuadSPI_RBDR_RXDATA_SHIFT (0U) 783 #define QuadSPI_RBDR_RXDATA_WIDTH (32U) 784 #define QuadSPI_RBDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBDR_RXDATA_SHIFT)) & QuadSPI_RBDR_RXDATA_MASK) 785 /*! @} */ 786 787 /*! @name LUTKEY - LUT Key Register */ 788 /*! @{ */ 789 790 #define QuadSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) 791 #define QuadSPI_LUTKEY_KEY_SHIFT (0U) 792 #define QuadSPI_LUTKEY_KEY_WIDTH (32U) 793 #define QuadSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUTKEY_KEY_SHIFT)) & QuadSPI_LUTKEY_KEY_MASK) 794 /*! @} */ 795 796 /*! @name LCKCR - LUT Lock Configuration Register */ 797 /*! @{ */ 798 799 #define QuadSPI_LCKCR_LOCK_MASK (0x1U) 800 #define QuadSPI_LCKCR_LOCK_SHIFT (0U) 801 #define QuadSPI_LCKCR_LOCK_WIDTH (1U) 802 #define QuadSPI_LCKCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK) 803 804 #define QuadSPI_LCKCR_UNLOCK_MASK (0x2U) 805 #define QuadSPI_LCKCR_UNLOCK_SHIFT (1U) 806 #define QuadSPI_LCKCR_UNLOCK_WIDTH (1U) 807 #define QuadSPI_LCKCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_UNLOCK_SHIFT)) & QuadSPI_LCKCR_UNLOCK_MASK) 808 /*! @} */ 809 810 /*! @name LUT - Look-up Table register */ 811 /*! @{ */ 812 813 #define QuadSPI_LUT_OPRND0_MASK (0xFFU) 814 #define QuadSPI_LUT_OPRND0_SHIFT (0U) 815 #define QuadSPI_LUT_OPRND0_WIDTH (8U) 816 #define QuadSPI_LUT_OPRND0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND0_SHIFT)) & QuadSPI_LUT_OPRND0_MASK) 817 818 #define QuadSPI_LUT_PAD0_MASK (0x300U) 819 #define QuadSPI_LUT_PAD0_SHIFT (8U) 820 #define QuadSPI_LUT_PAD0_WIDTH (2U) 821 #define QuadSPI_LUT_PAD0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD0_SHIFT)) & QuadSPI_LUT_PAD0_MASK) 822 823 #define QuadSPI_LUT_INSTR0_MASK (0xFC00U) 824 #define QuadSPI_LUT_INSTR0_SHIFT (10U) 825 #define QuadSPI_LUT_INSTR0_WIDTH (6U) 826 #define QuadSPI_LUT_INSTR0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR0_SHIFT)) & QuadSPI_LUT_INSTR0_MASK) 827 828 #define QuadSPI_LUT_OPRND1_MASK (0xFF0000U) 829 #define QuadSPI_LUT_OPRND1_SHIFT (16U) 830 #define QuadSPI_LUT_OPRND1_WIDTH (8U) 831 #define QuadSPI_LUT_OPRND1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND1_SHIFT)) & QuadSPI_LUT_OPRND1_MASK) 832 833 #define QuadSPI_LUT_PAD1_MASK (0x3000000U) 834 #define QuadSPI_LUT_PAD1_SHIFT (24U) 835 #define QuadSPI_LUT_PAD1_WIDTH (2U) 836 #define QuadSPI_LUT_PAD1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD1_SHIFT)) & QuadSPI_LUT_PAD1_MASK) 837 838 #define QuadSPI_LUT_INSTR1_MASK (0xFC000000U) 839 #define QuadSPI_LUT_INSTR1_SHIFT (26U) 840 #define QuadSPI_LUT_INSTR1_WIDTH (6U) 841 #define QuadSPI_LUT_INSTR1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR1_SHIFT)) & QuadSPI_LUT_INSTR1_MASK) 842 /*! @} */ 843 844 /*! 845 * @} 846 */ /* end of group QuadSPI_Register_Masks */ 847 848 /*! 849 * @} 850 */ /* end of group QuadSPI_Peripheral_Access_Layer */ 851 852 #endif /* #if !defined(S32K148_QuadSPI_H_) */ 853
