1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K148_LPI2C.h 10 * @version 1.1 11 * @date 2022-02-02 12 * @brief Peripheral Access Layer for S32K148_LPI2C 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K148_LPI2C_H_) /* Check if memory map has not been already included */ 58 #define S32K148_LPI2C_H_ 59 60 #include "S32K148_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- LPI2C Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer 68 * @{ 69 */ 70 71 /** LPI2C - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ 74 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ 75 uint8_t RESERVED_0[8]; 76 __IO uint32_t MCR; /**< Master Control Register, offset: 0x10 */ 77 __IO uint32_t MSR; /**< Master Status Register, offset: 0x14 */ 78 __IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x18 */ 79 __IO uint32_t MDER; /**< Master DMA Enable Register, offset: 0x1C */ 80 __IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */ 81 __IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */ 82 __IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */ 83 __IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */ 84 uint8_t RESERVED_1[16]; 85 __IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */ 86 uint8_t RESERVED_2[4]; 87 __IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */ 88 uint8_t RESERVED_3[4]; 89 __IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */ 90 uint8_t RESERVED_4[4]; 91 __IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */ 92 __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ 93 __O uint32_t MTDR; /**< Master Transmit Data Register, offset: 0x60 */ 94 uint8_t RESERVED_5[12]; 95 __I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */ 96 uint8_t RESERVED_6[156]; 97 __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ 98 __IO uint32_t SSR; /**< Slave Status Register, offset: 0x114 */ 99 __IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */ 100 __IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */ 101 uint8_t RESERVED_7[4]; 102 __IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */ 103 __IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */ 104 uint8_t RESERVED_8[20]; 105 __IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */ 106 uint8_t RESERVED_9[12]; 107 __I uint32_t SASR; /**< Slave Address Status Register, offset: 0x150 */ 108 __IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */ 109 uint8_t RESERVED_10[8]; 110 __O uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */ 111 uint8_t RESERVED_11[12]; 112 __I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */ 113 } LPI2C_Type, *LPI2C_MemMapPtr; 114 115 /** Number of instances of the LPI2C module. */ 116 #define LPI2C_INSTANCE_COUNT (2u) 117 118 /* LPI2C - Peripheral instance base addresses */ 119 /** Peripheral LPI2C0 base address */ 120 #define IP_LPI2C0_BASE (0x40066000u) 121 /** Peripheral LPI2C0 base pointer */ 122 #define IP_LPI2C0 ((LPI2C_Type *)IP_LPI2C0_BASE) 123 /** Peripheral LPI2C1 base address */ 124 #define IP_LPI2C1_BASE (0x40067000u) 125 /** Peripheral LPI2C1 base pointer */ 126 #define IP_LPI2C1 ((LPI2C_Type *)IP_LPI2C1_BASE) 127 /** Array initializer of LPI2C peripheral base addresses */ 128 #define IP_LPI2C_BASE_ADDRS { IP_LPI2C0_BASE, IP_LPI2C1_BASE } 129 /** Array initializer of LPI2C peripheral base pointers */ 130 #define IP_LPI2C_BASE_PTRS { IP_LPI2C0, IP_LPI2C1 } 131 132 /* ---------------------------------------------------------------------------- 133 -- LPI2C Register Masks 134 ---------------------------------------------------------------------------- */ 135 136 /*! 137 * @addtogroup LPI2C_Register_Masks LPI2C Register Masks 138 * @{ 139 */ 140 141 /*! @name VERID - Version ID Register */ 142 /*! @{ */ 143 144 #define LPI2C_VERID_FEATURE_MASK (0xFFFFU) 145 #define LPI2C_VERID_FEATURE_SHIFT (0U) 146 #define LPI2C_VERID_FEATURE_WIDTH (16U) 147 #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) 148 149 #define LPI2C_VERID_MINOR_MASK (0xFF0000U) 150 #define LPI2C_VERID_MINOR_SHIFT (16U) 151 #define LPI2C_VERID_MINOR_WIDTH (8U) 152 #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) 153 154 #define LPI2C_VERID_MAJOR_MASK (0xFF000000U) 155 #define LPI2C_VERID_MAJOR_SHIFT (24U) 156 #define LPI2C_VERID_MAJOR_WIDTH (8U) 157 #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) 158 /*! @} */ 159 160 /*! @name PARAM - Parameter Register */ 161 /*! @{ */ 162 163 #define LPI2C_PARAM_MTXFIFO_MASK (0xFU) 164 #define LPI2C_PARAM_MTXFIFO_SHIFT (0U) 165 #define LPI2C_PARAM_MTXFIFO_WIDTH (4U) 166 #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) 167 168 #define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) 169 #define LPI2C_PARAM_MRXFIFO_SHIFT (8U) 170 #define LPI2C_PARAM_MRXFIFO_WIDTH (4U) 171 #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) 172 /*! @} */ 173 174 /*! @name MCR - Master Control Register */ 175 /*! @{ */ 176 177 #define LPI2C_MCR_MEN_MASK (0x1U) 178 #define LPI2C_MCR_MEN_SHIFT (0U) 179 #define LPI2C_MCR_MEN_WIDTH (1U) 180 #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) 181 182 #define LPI2C_MCR_RST_MASK (0x2U) 183 #define LPI2C_MCR_RST_SHIFT (1U) 184 #define LPI2C_MCR_RST_WIDTH (1U) 185 #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) 186 187 #define LPI2C_MCR_DOZEN_MASK (0x4U) 188 #define LPI2C_MCR_DOZEN_SHIFT (2U) 189 #define LPI2C_MCR_DOZEN_WIDTH (1U) 190 #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) 191 192 #define LPI2C_MCR_DBGEN_MASK (0x8U) 193 #define LPI2C_MCR_DBGEN_SHIFT (3U) 194 #define LPI2C_MCR_DBGEN_WIDTH (1U) 195 #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) 196 197 #define LPI2C_MCR_RTF_MASK (0x100U) 198 #define LPI2C_MCR_RTF_SHIFT (8U) 199 #define LPI2C_MCR_RTF_WIDTH (1U) 200 #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) 201 202 #define LPI2C_MCR_RRF_MASK (0x200U) 203 #define LPI2C_MCR_RRF_SHIFT (9U) 204 #define LPI2C_MCR_RRF_WIDTH (1U) 205 #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) 206 /*! @} */ 207 208 /*! @name MSR - Master Status Register */ 209 /*! @{ */ 210 211 #define LPI2C_MSR_TDF_MASK (0x1U) 212 #define LPI2C_MSR_TDF_SHIFT (0U) 213 #define LPI2C_MSR_TDF_WIDTH (1U) 214 #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) 215 216 #define LPI2C_MSR_RDF_MASK (0x2U) 217 #define LPI2C_MSR_RDF_SHIFT (1U) 218 #define LPI2C_MSR_RDF_WIDTH (1U) 219 #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) 220 221 #define LPI2C_MSR_EPF_MASK (0x100U) 222 #define LPI2C_MSR_EPF_SHIFT (8U) 223 #define LPI2C_MSR_EPF_WIDTH (1U) 224 #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) 225 226 #define LPI2C_MSR_SDF_MASK (0x200U) 227 #define LPI2C_MSR_SDF_SHIFT (9U) 228 #define LPI2C_MSR_SDF_WIDTH (1U) 229 #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) 230 231 #define LPI2C_MSR_NDF_MASK (0x400U) 232 #define LPI2C_MSR_NDF_SHIFT (10U) 233 #define LPI2C_MSR_NDF_WIDTH (1U) 234 #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) 235 236 #define LPI2C_MSR_ALF_MASK (0x800U) 237 #define LPI2C_MSR_ALF_SHIFT (11U) 238 #define LPI2C_MSR_ALF_WIDTH (1U) 239 #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) 240 241 #define LPI2C_MSR_FEF_MASK (0x1000U) 242 #define LPI2C_MSR_FEF_SHIFT (12U) 243 #define LPI2C_MSR_FEF_WIDTH (1U) 244 #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) 245 246 #define LPI2C_MSR_PLTF_MASK (0x2000U) 247 #define LPI2C_MSR_PLTF_SHIFT (13U) 248 #define LPI2C_MSR_PLTF_WIDTH (1U) 249 #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) 250 251 #define LPI2C_MSR_DMF_MASK (0x4000U) 252 #define LPI2C_MSR_DMF_SHIFT (14U) 253 #define LPI2C_MSR_DMF_WIDTH (1U) 254 #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) 255 256 #define LPI2C_MSR_MBF_MASK (0x1000000U) 257 #define LPI2C_MSR_MBF_SHIFT (24U) 258 #define LPI2C_MSR_MBF_WIDTH (1U) 259 #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) 260 261 #define LPI2C_MSR_BBF_MASK (0x2000000U) 262 #define LPI2C_MSR_BBF_SHIFT (25U) 263 #define LPI2C_MSR_BBF_WIDTH (1U) 264 #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) 265 /*! @} */ 266 267 /*! @name MIER - Master Interrupt Enable Register */ 268 /*! @{ */ 269 270 #define LPI2C_MIER_TDIE_MASK (0x1U) 271 #define LPI2C_MIER_TDIE_SHIFT (0U) 272 #define LPI2C_MIER_TDIE_WIDTH (1U) 273 #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) 274 275 #define LPI2C_MIER_RDIE_MASK (0x2U) 276 #define LPI2C_MIER_RDIE_SHIFT (1U) 277 #define LPI2C_MIER_RDIE_WIDTH (1U) 278 #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) 279 280 #define LPI2C_MIER_EPIE_MASK (0x100U) 281 #define LPI2C_MIER_EPIE_SHIFT (8U) 282 #define LPI2C_MIER_EPIE_WIDTH (1U) 283 #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) 284 285 #define LPI2C_MIER_SDIE_MASK (0x200U) 286 #define LPI2C_MIER_SDIE_SHIFT (9U) 287 #define LPI2C_MIER_SDIE_WIDTH (1U) 288 #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) 289 290 #define LPI2C_MIER_NDIE_MASK (0x400U) 291 #define LPI2C_MIER_NDIE_SHIFT (10U) 292 #define LPI2C_MIER_NDIE_WIDTH (1U) 293 #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) 294 295 #define LPI2C_MIER_ALIE_MASK (0x800U) 296 #define LPI2C_MIER_ALIE_SHIFT (11U) 297 #define LPI2C_MIER_ALIE_WIDTH (1U) 298 #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) 299 300 #define LPI2C_MIER_FEIE_MASK (0x1000U) 301 #define LPI2C_MIER_FEIE_SHIFT (12U) 302 #define LPI2C_MIER_FEIE_WIDTH (1U) 303 #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) 304 305 #define LPI2C_MIER_PLTIE_MASK (0x2000U) 306 #define LPI2C_MIER_PLTIE_SHIFT (13U) 307 #define LPI2C_MIER_PLTIE_WIDTH (1U) 308 #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) 309 310 #define LPI2C_MIER_DMIE_MASK (0x4000U) 311 #define LPI2C_MIER_DMIE_SHIFT (14U) 312 #define LPI2C_MIER_DMIE_WIDTH (1U) 313 #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) 314 /*! @} */ 315 316 /*! @name MDER - Master DMA Enable Register */ 317 /*! @{ */ 318 319 #define LPI2C_MDER_TDDE_MASK (0x1U) 320 #define LPI2C_MDER_TDDE_SHIFT (0U) 321 #define LPI2C_MDER_TDDE_WIDTH (1U) 322 #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) 323 324 #define LPI2C_MDER_RDDE_MASK (0x2U) 325 #define LPI2C_MDER_RDDE_SHIFT (1U) 326 #define LPI2C_MDER_RDDE_WIDTH (1U) 327 #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) 328 /*! @} */ 329 330 /*! @name MCFGR0 - Master Configuration Register 0 */ 331 /*! @{ */ 332 333 #define LPI2C_MCFGR0_HREN_MASK (0x1U) 334 #define LPI2C_MCFGR0_HREN_SHIFT (0U) 335 #define LPI2C_MCFGR0_HREN_WIDTH (1U) 336 #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) 337 338 #define LPI2C_MCFGR0_HRPOL_MASK (0x2U) 339 #define LPI2C_MCFGR0_HRPOL_SHIFT (1U) 340 #define LPI2C_MCFGR0_HRPOL_WIDTH (1U) 341 #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) 342 343 #define LPI2C_MCFGR0_HRSEL_MASK (0x4U) 344 #define LPI2C_MCFGR0_HRSEL_SHIFT (2U) 345 #define LPI2C_MCFGR0_HRSEL_WIDTH (1U) 346 #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) 347 348 #define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) 349 #define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) 350 #define LPI2C_MCFGR0_CIRFIFO_WIDTH (1U) 351 #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) 352 353 #define LPI2C_MCFGR0_RDMO_MASK (0x200U) 354 #define LPI2C_MCFGR0_RDMO_SHIFT (9U) 355 #define LPI2C_MCFGR0_RDMO_WIDTH (1U) 356 #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) 357 /*! @} */ 358 359 /*! @name MCFGR1 - Master Configuration Register 1 */ 360 /*! @{ */ 361 362 #define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) 363 #define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) 364 #define LPI2C_MCFGR1_PRESCALE_WIDTH (3U) 365 #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) 366 367 #define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) 368 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) 369 #define LPI2C_MCFGR1_AUTOSTOP_WIDTH (1U) 370 #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) 371 372 #define LPI2C_MCFGR1_IGNACK_MASK (0x200U) 373 #define LPI2C_MCFGR1_IGNACK_SHIFT (9U) 374 #define LPI2C_MCFGR1_IGNACK_WIDTH (1U) 375 #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) 376 377 #define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) 378 #define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) 379 #define LPI2C_MCFGR1_TIMECFG_WIDTH (1U) 380 #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) 381 382 #define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) 383 #define LPI2C_MCFGR1_MATCFG_SHIFT (16U) 384 #define LPI2C_MCFGR1_MATCFG_WIDTH (3U) 385 #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) 386 387 #define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) 388 #define LPI2C_MCFGR1_PINCFG_SHIFT (24U) 389 #define LPI2C_MCFGR1_PINCFG_WIDTH (3U) 390 #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) 391 /*! @} */ 392 393 /*! @name MCFGR2 - Master Configuration Register 2 */ 394 /*! @{ */ 395 396 #define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) 397 #define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) 398 #define LPI2C_MCFGR2_BUSIDLE_WIDTH (12U) 399 #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) 400 401 #define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) 402 #define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) 403 #define LPI2C_MCFGR2_FILTSCL_WIDTH (4U) 404 #define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) 405 406 #define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) 407 #define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) 408 #define LPI2C_MCFGR2_FILTSDA_WIDTH (4U) 409 #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) 410 /*! @} */ 411 412 /*! @name MCFGR3 - Master Configuration Register 3 */ 413 /*! @{ */ 414 415 #define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) 416 #define LPI2C_MCFGR3_PINLOW_SHIFT (8U) 417 #define LPI2C_MCFGR3_PINLOW_WIDTH (12U) 418 #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) 419 /*! @} */ 420 421 /*! @name MDMR - Master Data Match Register */ 422 /*! @{ */ 423 424 #define LPI2C_MDMR_MATCH0_MASK (0xFFU) 425 #define LPI2C_MDMR_MATCH0_SHIFT (0U) 426 #define LPI2C_MDMR_MATCH0_WIDTH (8U) 427 #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) 428 429 #define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) 430 #define LPI2C_MDMR_MATCH1_SHIFT (16U) 431 #define LPI2C_MDMR_MATCH1_WIDTH (8U) 432 #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) 433 /*! @} */ 434 435 /*! @name MCCR0 - Master Clock Configuration Register 0 */ 436 /*! @{ */ 437 438 #define LPI2C_MCCR0_CLKLO_MASK (0x3FU) 439 #define LPI2C_MCCR0_CLKLO_SHIFT (0U) 440 #define LPI2C_MCCR0_CLKLO_WIDTH (6U) 441 #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) 442 443 #define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) 444 #define LPI2C_MCCR0_CLKHI_SHIFT (8U) 445 #define LPI2C_MCCR0_CLKHI_WIDTH (6U) 446 #define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) 447 448 #define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) 449 #define LPI2C_MCCR0_SETHOLD_SHIFT (16U) 450 #define LPI2C_MCCR0_SETHOLD_WIDTH (6U) 451 #define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) 452 453 #define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) 454 #define LPI2C_MCCR0_DATAVD_SHIFT (24U) 455 #define LPI2C_MCCR0_DATAVD_WIDTH (6U) 456 #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) 457 /*! @} */ 458 459 /*! @name MCCR1 - Master Clock Configuration Register 1 */ 460 /*! @{ */ 461 462 #define LPI2C_MCCR1_CLKLO_MASK (0x3FU) 463 #define LPI2C_MCCR1_CLKLO_SHIFT (0U) 464 #define LPI2C_MCCR1_CLKLO_WIDTH (6U) 465 #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) 466 467 #define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) 468 #define LPI2C_MCCR1_CLKHI_SHIFT (8U) 469 #define LPI2C_MCCR1_CLKHI_WIDTH (6U) 470 #define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) 471 472 #define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) 473 #define LPI2C_MCCR1_SETHOLD_SHIFT (16U) 474 #define LPI2C_MCCR1_SETHOLD_WIDTH (6U) 475 #define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) 476 477 #define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) 478 #define LPI2C_MCCR1_DATAVD_SHIFT (24U) 479 #define LPI2C_MCCR1_DATAVD_WIDTH (6U) 480 #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) 481 /*! @} */ 482 483 /*! @name MFCR - Master FIFO Control Register */ 484 /*! @{ */ 485 486 #define LPI2C_MFCR_TXWATER_MASK (0x3U) 487 #define LPI2C_MFCR_TXWATER_SHIFT (0U) 488 #define LPI2C_MFCR_TXWATER_WIDTH (2U) 489 #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) 490 491 #define LPI2C_MFCR_RXWATER_MASK (0x30000U) 492 #define LPI2C_MFCR_RXWATER_SHIFT (16U) 493 #define LPI2C_MFCR_RXWATER_WIDTH (2U) 494 #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) 495 /*! @} */ 496 497 /*! @name MFSR - Master FIFO Status Register */ 498 /*! @{ */ 499 500 #define LPI2C_MFSR_TXCOUNT_MASK (0x7U) 501 #define LPI2C_MFSR_TXCOUNT_SHIFT (0U) 502 #define LPI2C_MFSR_TXCOUNT_WIDTH (3U) 503 #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) 504 505 #define LPI2C_MFSR_RXCOUNT_MASK (0x70000U) 506 #define LPI2C_MFSR_RXCOUNT_SHIFT (16U) 507 #define LPI2C_MFSR_RXCOUNT_WIDTH (3U) 508 #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) 509 /*! @} */ 510 511 /*! @name MTDR - Master Transmit Data Register */ 512 /*! @{ */ 513 514 #define LPI2C_MTDR_DATA_MASK (0xFFU) 515 #define LPI2C_MTDR_DATA_SHIFT (0U) 516 #define LPI2C_MTDR_DATA_WIDTH (8U) 517 #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) 518 519 #define LPI2C_MTDR_CMD_MASK (0x700U) 520 #define LPI2C_MTDR_CMD_SHIFT (8U) 521 #define LPI2C_MTDR_CMD_WIDTH (3U) 522 #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) 523 /*! @} */ 524 525 /*! @name MRDR - Master Receive Data Register */ 526 /*! @{ */ 527 528 #define LPI2C_MRDR_DATA_MASK (0xFFU) 529 #define LPI2C_MRDR_DATA_SHIFT (0U) 530 #define LPI2C_MRDR_DATA_WIDTH (8U) 531 #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) 532 533 #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) 534 #define LPI2C_MRDR_RXEMPTY_SHIFT (14U) 535 #define LPI2C_MRDR_RXEMPTY_WIDTH (1U) 536 #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) 537 /*! @} */ 538 539 /*! @name SCR - Slave Control Register */ 540 /*! @{ */ 541 542 #define LPI2C_SCR_SEN_MASK (0x1U) 543 #define LPI2C_SCR_SEN_SHIFT (0U) 544 #define LPI2C_SCR_SEN_WIDTH (1U) 545 #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) 546 547 #define LPI2C_SCR_RST_MASK (0x2U) 548 #define LPI2C_SCR_RST_SHIFT (1U) 549 #define LPI2C_SCR_RST_WIDTH (1U) 550 #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) 551 552 #define LPI2C_SCR_FILTEN_MASK (0x10U) 553 #define LPI2C_SCR_FILTEN_SHIFT (4U) 554 #define LPI2C_SCR_FILTEN_WIDTH (1U) 555 #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) 556 557 #define LPI2C_SCR_FILTDZ_MASK (0x20U) 558 #define LPI2C_SCR_FILTDZ_SHIFT (5U) 559 #define LPI2C_SCR_FILTDZ_WIDTH (1U) 560 #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) 561 562 #define LPI2C_SCR_RTF_MASK (0x100U) 563 #define LPI2C_SCR_RTF_SHIFT (8U) 564 #define LPI2C_SCR_RTF_WIDTH (1U) 565 #define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) 566 567 #define LPI2C_SCR_RRF_MASK (0x200U) 568 #define LPI2C_SCR_RRF_SHIFT (9U) 569 #define LPI2C_SCR_RRF_WIDTH (1U) 570 #define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) 571 /*! @} */ 572 573 /*! @name SSR - Slave Status Register */ 574 /*! @{ */ 575 576 #define LPI2C_SSR_TDF_MASK (0x1U) 577 #define LPI2C_SSR_TDF_SHIFT (0U) 578 #define LPI2C_SSR_TDF_WIDTH (1U) 579 #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) 580 581 #define LPI2C_SSR_RDF_MASK (0x2U) 582 #define LPI2C_SSR_RDF_SHIFT (1U) 583 #define LPI2C_SSR_RDF_WIDTH (1U) 584 #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) 585 586 #define LPI2C_SSR_AVF_MASK (0x4U) 587 #define LPI2C_SSR_AVF_SHIFT (2U) 588 #define LPI2C_SSR_AVF_WIDTH (1U) 589 #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) 590 591 #define LPI2C_SSR_TAF_MASK (0x8U) 592 #define LPI2C_SSR_TAF_SHIFT (3U) 593 #define LPI2C_SSR_TAF_WIDTH (1U) 594 #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) 595 596 #define LPI2C_SSR_RSF_MASK (0x100U) 597 #define LPI2C_SSR_RSF_SHIFT (8U) 598 #define LPI2C_SSR_RSF_WIDTH (1U) 599 #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) 600 601 #define LPI2C_SSR_SDF_MASK (0x200U) 602 #define LPI2C_SSR_SDF_SHIFT (9U) 603 #define LPI2C_SSR_SDF_WIDTH (1U) 604 #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) 605 606 #define LPI2C_SSR_BEF_MASK (0x400U) 607 #define LPI2C_SSR_BEF_SHIFT (10U) 608 #define LPI2C_SSR_BEF_WIDTH (1U) 609 #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) 610 611 #define LPI2C_SSR_FEF_MASK (0x800U) 612 #define LPI2C_SSR_FEF_SHIFT (11U) 613 #define LPI2C_SSR_FEF_WIDTH (1U) 614 #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) 615 616 #define LPI2C_SSR_AM0F_MASK (0x1000U) 617 #define LPI2C_SSR_AM0F_SHIFT (12U) 618 #define LPI2C_SSR_AM0F_WIDTH (1U) 619 #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) 620 621 #define LPI2C_SSR_AM1F_MASK (0x2000U) 622 #define LPI2C_SSR_AM1F_SHIFT (13U) 623 #define LPI2C_SSR_AM1F_WIDTH (1U) 624 #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) 625 626 #define LPI2C_SSR_GCF_MASK (0x4000U) 627 #define LPI2C_SSR_GCF_SHIFT (14U) 628 #define LPI2C_SSR_GCF_WIDTH (1U) 629 #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) 630 631 #define LPI2C_SSR_SARF_MASK (0x8000U) 632 #define LPI2C_SSR_SARF_SHIFT (15U) 633 #define LPI2C_SSR_SARF_WIDTH (1U) 634 #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) 635 636 #define LPI2C_SSR_SBF_MASK (0x1000000U) 637 #define LPI2C_SSR_SBF_SHIFT (24U) 638 #define LPI2C_SSR_SBF_WIDTH (1U) 639 #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) 640 641 #define LPI2C_SSR_BBF_MASK (0x2000000U) 642 #define LPI2C_SSR_BBF_SHIFT (25U) 643 #define LPI2C_SSR_BBF_WIDTH (1U) 644 #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) 645 /*! @} */ 646 647 /*! @name SIER - Slave Interrupt Enable Register */ 648 /*! @{ */ 649 650 #define LPI2C_SIER_TDIE_MASK (0x1U) 651 #define LPI2C_SIER_TDIE_SHIFT (0U) 652 #define LPI2C_SIER_TDIE_WIDTH (1U) 653 #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) 654 655 #define LPI2C_SIER_RDIE_MASK (0x2U) 656 #define LPI2C_SIER_RDIE_SHIFT (1U) 657 #define LPI2C_SIER_RDIE_WIDTH (1U) 658 #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) 659 660 #define LPI2C_SIER_AVIE_MASK (0x4U) 661 #define LPI2C_SIER_AVIE_SHIFT (2U) 662 #define LPI2C_SIER_AVIE_WIDTH (1U) 663 #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) 664 665 #define LPI2C_SIER_TAIE_MASK (0x8U) 666 #define LPI2C_SIER_TAIE_SHIFT (3U) 667 #define LPI2C_SIER_TAIE_WIDTH (1U) 668 #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) 669 670 #define LPI2C_SIER_RSIE_MASK (0x100U) 671 #define LPI2C_SIER_RSIE_SHIFT (8U) 672 #define LPI2C_SIER_RSIE_WIDTH (1U) 673 #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) 674 675 #define LPI2C_SIER_SDIE_MASK (0x200U) 676 #define LPI2C_SIER_SDIE_SHIFT (9U) 677 #define LPI2C_SIER_SDIE_WIDTH (1U) 678 #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) 679 680 #define LPI2C_SIER_BEIE_MASK (0x400U) 681 #define LPI2C_SIER_BEIE_SHIFT (10U) 682 #define LPI2C_SIER_BEIE_WIDTH (1U) 683 #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) 684 685 #define LPI2C_SIER_FEIE_MASK (0x800U) 686 #define LPI2C_SIER_FEIE_SHIFT (11U) 687 #define LPI2C_SIER_FEIE_WIDTH (1U) 688 #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) 689 690 #define LPI2C_SIER_AM0IE_MASK (0x1000U) 691 #define LPI2C_SIER_AM0IE_SHIFT (12U) 692 #define LPI2C_SIER_AM0IE_WIDTH (1U) 693 #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) 694 695 #define LPI2C_SIER_AM1F_MASK (0x2000U) 696 #define LPI2C_SIER_AM1F_SHIFT (13U) 697 #define LPI2C_SIER_AM1F_WIDTH (1U) 698 #define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK) 699 700 #define LPI2C_SIER_GCIE_MASK (0x4000U) 701 #define LPI2C_SIER_GCIE_SHIFT (14U) 702 #define LPI2C_SIER_GCIE_WIDTH (1U) 703 #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) 704 705 #define LPI2C_SIER_SARIE_MASK (0x8000U) 706 #define LPI2C_SIER_SARIE_SHIFT (15U) 707 #define LPI2C_SIER_SARIE_WIDTH (1U) 708 #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) 709 /*! @} */ 710 711 /*! @name SDER - Slave DMA Enable Register */ 712 /*! @{ */ 713 714 #define LPI2C_SDER_TDDE_MASK (0x1U) 715 #define LPI2C_SDER_TDDE_SHIFT (0U) 716 #define LPI2C_SDER_TDDE_WIDTH (1U) 717 #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) 718 719 #define LPI2C_SDER_RDDE_MASK (0x2U) 720 #define LPI2C_SDER_RDDE_SHIFT (1U) 721 #define LPI2C_SDER_RDDE_WIDTH (1U) 722 #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) 723 724 #define LPI2C_SDER_AVDE_MASK (0x4U) 725 #define LPI2C_SDER_AVDE_SHIFT (2U) 726 #define LPI2C_SDER_AVDE_WIDTH (1U) 727 #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) 728 /*! @} */ 729 730 /*! @name SCFGR1 - Slave Configuration Register 1 */ 731 /*! @{ */ 732 733 #define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) 734 #define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) 735 #define LPI2C_SCFGR1_ADRSTALL_WIDTH (1U) 736 #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) 737 738 #define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) 739 #define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) 740 #define LPI2C_SCFGR1_RXSTALL_WIDTH (1U) 741 #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) 742 743 #define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) 744 #define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) 745 #define LPI2C_SCFGR1_TXDSTALL_WIDTH (1U) 746 #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) 747 748 #define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) 749 #define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) 750 #define LPI2C_SCFGR1_ACKSTALL_WIDTH (1U) 751 #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) 752 753 #define LPI2C_SCFGR1_GCEN_MASK (0x100U) 754 #define LPI2C_SCFGR1_GCEN_SHIFT (8U) 755 #define LPI2C_SCFGR1_GCEN_WIDTH (1U) 756 #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) 757 758 #define LPI2C_SCFGR1_SAEN_MASK (0x200U) 759 #define LPI2C_SCFGR1_SAEN_SHIFT (9U) 760 #define LPI2C_SCFGR1_SAEN_WIDTH (1U) 761 #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) 762 763 #define LPI2C_SCFGR1_TXCFG_MASK (0x400U) 764 #define LPI2C_SCFGR1_TXCFG_SHIFT (10U) 765 #define LPI2C_SCFGR1_TXCFG_WIDTH (1U) 766 #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) 767 768 #define LPI2C_SCFGR1_RXCFG_MASK (0x800U) 769 #define LPI2C_SCFGR1_RXCFG_SHIFT (11U) 770 #define LPI2C_SCFGR1_RXCFG_WIDTH (1U) 771 #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) 772 773 #define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) 774 #define LPI2C_SCFGR1_IGNACK_SHIFT (12U) 775 #define LPI2C_SCFGR1_IGNACK_WIDTH (1U) 776 #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) 777 778 #define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) 779 #define LPI2C_SCFGR1_HSMEN_SHIFT (13U) 780 #define LPI2C_SCFGR1_HSMEN_WIDTH (1U) 781 #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) 782 783 #define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) 784 #define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) 785 #define LPI2C_SCFGR1_ADDRCFG_WIDTH (3U) 786 #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) 787 /*! @} */ 788 789 /*! @name SCFGR2 - Slave Configuration Register 2 */ 790 /*! @{ */ 791 792 #define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) 793 #define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) 794 #define LPI2C_SCFGR2_CLKHOLD_WIDTH (4U) 795 #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) 796 797 #define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) 798 #define LPI2C_SCFGR2_DATAVD_SHIFT (8U) 799 #define LPI2C_SCFGR2_DATAVD_WIDTH (6U) 800 #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) 801 802 #define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) 803 #define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) 804 #define LPI2C_SCFGR2_FILTSCL_WIDTH (4U) 805 #define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) 806 807 #define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) 808 #define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) 809 #define LPI2C_SCFGR2_FILTSDA_WIDTH (4U) 810 #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) 811 /*! @} */ 812 813 /*! @name SAMR - Slave Address Match Register */ 814 /*! @{ */ 815 816 #define LPI2C_SAMR_ADDR0_MASK (0x7FEU) 817 #define LPI2C_SAMR_ADDR0_SHIFT (1U) 818 #define LPI2C_SAMR_ADDR0_WIDTH (10U) 819 #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) 820 821 #define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) 822 #define LPI2C_SAMR_ADDR1_SHIFT (17U) 823 #define LPI2C_SAMR_ADDR1_WIDTH (10U) 824 #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) 825 /*! @} */ 826 827 /*! @name SASR - Slave Address Status Register */ 828 /*! @{ */ 829 830 #define LPI2C_SASR_RADDR_MASK (0x7FFU) 831 #define LPI2C_SASR_RADDR_SHIFT (0U) 832 #define LPI2C_SASR_RADDR_WIDTH (11U) 833 #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) 834 835 #define LPI2C_SASR_ANV_MASK (0x4000U) 836 #define LPI2C_SASR_ANV_SHIFT (14U) 837 #define LPI2C_SASR_ANV_WIDTH (1U) 838 #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) 839 /*! @} */ 840 841 /*! @name STAR - Slave Transmit ACK Register */ 842 /*! @{ */ 843 844 #define LPI2C_STAR_TXNACK_MASK (0x1U) 845 #define LPI2C_STAR_TXNACK_SHIFT (0U) 846 #define LPI2C_STAR_TXNACK_WIDTH (1U) 847 #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) 848 /*! @} */ 849 850 /*! @name STDR - Slave Transmit Data Register */ 851 /*! @{ */ 852 853 #define LPI2C_STDR_DATA_MASK (0xFFU) 854 #define LPI2C_STDR_DATA_SHIFT (0U) 855 #define LPI2C_STDR_DATA_WIDTH (8U) 856 #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) 857 /*! @} */ 858 859 /*! @name SRDR - Slave Receive Data Register */ 860 /*! @{ */ 861 862 #define LPI2C_SRDR_DATA_MASK (0xFFU) 863 #define LPI2C_SRDR_DATA_SHIFT (0U) 864 #define LPI2C_SRDR_DATA_WIDTH (8U) 865 #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) 866 867 #define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) 868 #define LPI2C_SRDR_RXEMPTY_SHIFT (14U) 869 #define LPI2C_SRDR_RXEMPTY_WIDTH (1U) 870 #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) 871 872 #define LPI2C_SRDR_SOF_MASK (0x8000U) 873 #define LPI2C_SRDR_SOF_SHIFT (15U) 874 #define LPI2C_SRDR_SOF_WIDTH (1U) 875 #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) 876 /*! @} */ 877 878 /*! 879 * @} 880 */ /* end of group LPI2C_Register_Masks */ 881 882 /*! 883 * @} 884 */ /* end of group LPI2C_Peripheral_Access_Layer */ 885 886 #endif /* #if !defined(S32K148_LPI2C_H_) */ 887
