1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K148_ENET.h 10 * @version 1.1 11 * @date 2022-02-02 12 * @brief Peripheral Access Layer for S32K148_ENET 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K148_ENET_H_) /* Check if memory map has not been already included */ 58 #define S32K148_ENET_H_ 59 60 #include "S32K148_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- ENET Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer 68 * @{ 69 */ 70 71 /** ENET - Size of Registers Arrays */ 72 #define ENET_TC_COUNT 4u 73 74 /** ENET - Register Layout Typedef */ 75 typedef struct { 76 uint8_t RESERVED_0[4]; 77 __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ 78 __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ 79 uint8_t RESERVED_1[4]; 80 __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */ 81 __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */ 82 uint8_t RESERVED_2[12]; 83 __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ 84 uint8_t RESERVED_3[24]; 85 __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */ 86 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ 87 uint8_t RESERVED_4[28]; 88 __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */ 89 uint8_t RESERVED_5[28]; 90 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ 91 uint8_t RESERVED_6[60]; 92 __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */ 93 uint8_t RESERVED_7[28]; 94 __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */ 95 __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */ 96 __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */ 97 uint8_t RESERVED_8[40]; 98 __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */ 99 __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */ 100 __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */ 101 __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */ 102 uint8_t RESERVED_9[28]; 103 __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */ 104 uint8_t RESERVED_10[56]; 105 __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */ 106 __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */ 107 __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */ 108 uint8_t RESERVED_11[4]; 109 __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ 110 __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ 111 __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */ 112 __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */ 113 __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */ 114 __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */ 115 __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */ 116 __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */ 117 __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */ 118 uint8_t RESERVED_12[12]; 119 __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */ 120 __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */ 121 uint8_t RESERVED_13[56]; 122 uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */ 123 __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ 124 __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ 125 __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ 126 __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */ 127 __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */ 128 __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */ 129 __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */ 130 __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */ 131 __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */ 132 __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */ 133 __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */ 134 __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */ 135 __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */ 136 __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */ 137 __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ 138 __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ 139 __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ 140 uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */ 141 __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ 142 __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ 143 __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ 144 __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */ 145 __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */ 146 __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */ 147 __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */ 148 __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */ 149 __I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */ 150 __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */ 151 __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */ 152 uint8_t RESERVED_14[12]; 153 __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */ 154 __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */ 155 __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */ 156 __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */ 157 __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */ 158 __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ 159 __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ 160 __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ 161 uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */ 162 __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ 163 __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ 164 __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ 165 __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */ 166 __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */ 167 __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */ 168 __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */ 169 __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */ 170 __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */ 171 __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */ 172 __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */ 173 __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */ 174 __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ 175 __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ 176 __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ 177 uint8_t RESERVED_15[284]; 178 __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ 179 __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ 180 __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ 181 __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ 182 __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ 183 __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ 184 __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ 185 uint8_t RESERVED_16[488]; 186 __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ 187 struct { /* offset: 0x608, array step: 0x8 */ 188 __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ 189 __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ 190 } TC[ENET_TC_COUNT]; 191 } ENET_Type, *ENET_MemMapPtr; 192 193 /** Number of instances of the ENET module. */ 194 #define ENET_INSTANCE_COUNT (1u) 195 196 /* ENET - Peripheral instance base addresses */ 197 /** Peripheral ENET base address */ 198 #define IP_ENET_BASE (0x40079000u) 199 /** Peripheral ENET base pointer */ 200 #define IP_ENET ((ENET_Type *)IP_ENET_BASE) 201 /** Array initializer of ENET peripheral base addresses */ 202 #define IP_ENET_BASE_ADDRS { IP_ENET_BASE } 203 /** Array initializer of ENET peripheral base pointers */ 204 #define IP_ENET_BASE_PTRS { IP_ENET } 205 206 /* ---------------------------------------------------------------------------- 207 -- ENET Register Masks 208 ---------------------------------------------------------------------------- */ 209 210 /*! 211 * @addtogroup ENET_Register_Masks ENET Register Masks 212 * @{ 213 */ 214 215 /*! @name EIR - Interrupt Event Register */ 216 /*! @{ */ 217 218 #define ENET_EIR_TS_TIMER_MASK (0x8000U) 219 #define ENET_EIR_TS_TIMER_SHIFT (15U) 220 #define ENET_EIR_TS_TIMER_WIDTH (1U) 221 #define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) 222 223 #define ENET_EIR_TS_AVAIL_MASK (0x10000U) 224 #define ENET_EIR_TS_AVAIL_SHIFT (16U) 225 #define ENET_EIR_TS_AVAIL_WIDTH (1U) 226 #define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK) 227 228 #define ENET_EIR_WAKEUP_MASK (0x20000U) 229 #define ENET_EIR_WAKEUP_SHIFT (17U) 230 #define ENET_EIR_WAKEUP_WIDTH (1U) 231 #define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK) 232 233 #define ENET_EIR_PLR_MASK (0x40000U) 234 #define ENET_EIR_PLR_SHIFT (18U) 235 #define ENET_EIR_PLR_WIDTH (1U) 236 #define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK) 237 238 #define ENET_EIR_UN_MASK (0x80000U) 239 #define ENET_EIR_UN_SHIFT (19U) 240 #define ENET_EIR_UN_WIDTH (1U) 241 #define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK) 242 243 #define ENET_EIR_RL_MASK (0x100000U) 244 #define ENET_EIR_RL_SHIFT (20U) 245 #define ENET_EIR_RL_WIDTH (1U) 246 #define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK) 247 248 #define ENET_EIR_LC_MASK (0x200000U) 249 #define ENET_EIR_LC_SHIFT (21U) 250 #define ENET_EIR_LC_WIDTH (1U) 251 #define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK) 252 253 #define ENET_EIR_EBERR_MASK (0x400000U) 254 #define ENET_EIR_EBERR_SHIFT (22U) 255 #define ENET_EIR_EBERR_WIDTH (1U) 256 #define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK) 257 258 #define ENET_EIR_MII_MASK (0x800000U) 259 #define ENET_EIR_MII_SHIFT (23U) 260 #define ENET_EIR_MII_WIDTH (1U) 261 #define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK) 262 263 #define ENET_EIR_RXB_MASK (0x1000000U) 264 #define ENET_EIR_RXB_SHIFT (24U) 265 #define ENET_EIR_RXB_WIDTH (1U) 266 #define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK) 267 268 #define ENET_EIR_RXF_MASK (0x2000000U) 269 #define ENET_EIR_RXF_SHIFT (25U) 270 #define ENET_EIR_RXF_WIDTH (1U) 271 #define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK) 272 273 #define ENET_EIR_TXB_MASK (0x4000000U) 274 #define ENET_EIR_TXB_SHIFT (26U) 275 #define ENET_EIR_TXB_WIDTH (1U) 276 #define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK) 277 278 #define ENET_EIR_TXF_MASK (0x8000000U) 279 #define ENET_EIR_TXF_SHIFT (27U) 280 #define ENET_EIR_TXF_WIDTH (1U) 281 #define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK) 282 283 #define ENET_EIR_GRA_MASK (0x10000000U) 284 #define ENET_EIR_GRA_SHIFT (28U) 285 #define ENET_EIR_GRA_WIDTH (1U) 286 #define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK) 287 288 #define ENET_EIR_BABT_MASK (0x20000000U) 289 #define ENET_EIR_BABT_SHIFT (29U) 290 #define ENET_EIR_BABT_WIDTH (1U) 291 #define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK) 292 293 #define ENET_EIR_BABR_MASK (0x40000000U) 294 #define ENET_EIR_BABR_SHIFT (30U) 295 #define ENET_EIR_BABR_WIDTH (1U) 296 #define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) 297 /*! @} */ 298 299 /*! @name EIMR - Interrupt Mask Register */ 300 /*! @{ */ 301 302 #define ENET_EIMR_TS_TIMER_MASK (0x8000U) 303 #define ENET_EIMR_TS_TIMER_SHIFT (15U) 304 #define ENET_EIMR_TS_TIMER_WIDTH (1U) 305 #define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) 306 307 #define ENET_EIMR_TS_AVAIL_MASK (0x10000U) 308 #define ENET_EIMR_TS_AVAIL_SHIFT (16U) 309 #define ENET_EIMR_TS_AVAIL_WIDTH (1U) 310 #define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) 311 312 #define ENET_EIMR_WAKEUP_MASK (0x20000U) 313 #define ENET_EIMR_WAKEUP_SHIFT (17U) 314 #define ENET_EIMR_WAKEUP_WIDTH (1U) 315 #define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) 316 317 #define ENET_EIMR_PLR_MASK (0x40000U) 318 #define ENET_EIMR_PLR_SHIFT (18U) 319 #define ENET_EIMR_PLR_WIDTH (1U) 320 #define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) 321 322 #define ENET_EIMR_UN_MASK (0x80000U) 323 #define ENET_EIMR_UN_SHIFT (19U) 324 #define ENET_EIMR_UN_WIDTH (1U) 325 #define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) 326 327 #define ENET_EIMR_RL_MASK (0x100000U) 328 #define ENET_EIMR_RL_SHIFT (20U) 329 #define ENET_EIMR_RL_WIDTH (1U) 330 #define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) 331 332 #define ENET_EIMR_LC_MASK (0x200000U) 333 #define ENET_EIMR_LC_SHIFT (21U) 334 #define ENET_EIMR_LC_WIDTH (1U) 335 #define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) 336 337 #define ENET_EIMR_EBERR_MASK (0x400000U) 338 #define ENET_EIMR_EBERR_SHIFT (22U) 339 #define ENET_EIMR_EBERR_WIDTH (1U) 340 #define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) 341 342 #define ENET_EIMR_MII_MASK (0x800000U) 343 #define ENET_EIMR_MII_SHIFT (23U) 344 #define ENET_EIMR_MII_WIDTH (1U) 345 #define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) 346 347 #define ENET_EIMR_RXB_MASK (0x1000000U) 348 #define ENET_EIMR_RXB_SHIFT (24U) 349 #define ENET_EIMR_RXB_WIDTH (1U) 350 #define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) 351 352 #define ENET_EIMR_RXF_MASK (0x2000000U) 353 #define ENET_EIMR_RXF_SHIFT (25U) 354 #define ENET_EIMR_RXF_WIDTH (1U) 355 #define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) 356 357 #define ENET_EIMR_TXB_MASK (0x4000000U) 358 #define ENET_EIMR_TXB_SHIFT (26U) 359 #define ENET_EIMR_TXB_WIDTH (1U) 360 #define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) 361 362 #define ENET_EIMR_TXF_MASK (0x8000000U) 363 #define ENET_EIMR_TXF_SHIFT (27U) 364 #define ENET_EIMR_TXF_WIDTH (1U) 365 #define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) 366 367 #define ENET_EIMR_GRA_MASK (0x10000000U) 368 #define ENET_EIMR_GRA_SHIFT (28U) 369 #define ENET_EIMR_GRA_WIDTH (1U) 370 #define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) 371 372 #define ENET_EIMR_BABT_MASK (0x20000000U) 373 #define ENET_EIMR_BABT_SHIFT (29U) 374 #define ENET_EIMR_BABT_WIDTH (1U) 375 #define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) 376 377 #define ENET_EIMR_BABR_MASK (0x40000000U) 378 #define ENET_EIMR_BABR_SHIFT (30U) 379 #define ENET_EIMR_BABR_WIDTH (1U) 380 #define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) 381 /*! @} */ 382 383 /*! @name RDAR - Receive Descriptor Active Register */ 384 /*! @{ */ 385 386 #define ENET_RDAR_RDAR_MASK (0x1000000U) 387 #define ENET_RDAR_RDAR_SHIFT (24U) 388 #define ENET_RDAR_RDAR_WIDTH (1U) 389 #define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) 390 /*! @} */ 391 392 /*! @name TDAR - Transmit Descriptor Active Register */ 393 /*! @{ */ 394 395 #define ENET_TDAR_TDAR_MASK (0x1000000U) 396 #define ENET_TDAR_TDAR_SHIFT (24U) 397 #define ENET_TDAR_TDAR_WIDTH (1U) 398 #define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) 399 /*! @} */ 400 401 /*! @name ECR - Ethernet Control Register */ 402 /*! @{ */ 403 404 #define ENET_ECR_RESET_MASK (0x1U) 405 #define ENET_ECR_RESET_SHIFT (0U) 406 #define ENET_ECR_RESET_WIDTH (1U) 407 #define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) 408 409 #define ENET_ECR_ETHEREN_MASK (0x2U) 410 #define ENET_ECR_ETHEREN_SHIFT (1U) 411 #define ENET_ECR_ETHEREN_WIDTH (1U) 412 #define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) 413 414 #define ENET_ECR_MAGICEN_MASK (0x4U) 415 #define ENET_ECR_MAGICEN_SHIFT (2U) 416 #define ENET_ECR_MAGICEN_WIDTH (1U) 417 #define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) 418 419 #define ENET_ECR_SLEEP_MASK (0x8U) 420 #define ENET_ECR_SLEEP_SHIFT (3U) 421 #define ENET_ECR_SLEEP_WIDTH (1U) 422 #define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) 423 424 #define ENET_ECR_EN1588_MASK (0x10U) 425 #define ENET_ECR_EN1588_SHIFT (4U) 426 #define ENET_ECR_EN1588_WIDTH (1U) 427 #define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) 428 429 #define ENET_ECR_DBGEN_MASK (0x40U) 430 #define ENET_ECR_DBGEN_SHIFT (6U) 431 #define ENET_ECR_DBGEN_WIDTH (1U) 432 #define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) 433 434 #define ENET_ECR_DBSWP_MASK (0x100U) 435 #define ENET_ECR_DBSWP_SHIFT (8U) 436 #define ENET_ECR_DBSWP_WIDTH (1U) 437 #define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) 438 /*! @} */ 439 440 /*! @name MMFR - MII Management Frame Register */ 441 /*! @{ */ 442 443 #define ENET_MMFR_DATA_MASK (0xFFFFU) 444 #define ENET_MMFR_DATA_SHIFT (0U) 445 #define ENET_MMFR_DATA_WIDTH (16U) 446 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) 447 448 #define ENET_MMFR_TA_MASK (0x30000U) 449 #define ENET_MMFR_TA_SHIFT (16U) 450 #define ENET_MMFR_TA_WIDTH (2U) 451 #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) 452 453 #define ENET_MMFR_RA_MASK (0x7C0000U) 454 #define ENET_MMFR_RA_SHIFT (18U) 455 #define ENET_MMFR_RA_WIDTH (5U) 456 #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) 457 458 #define ENET_MMFR_PA_MASK (0xF800000U) 459 #define ENET_MMFR_PA_SHIFT (23U) 460 #define ENET_MMFR_PA_WIDTH (5U) 461 #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) 462 463 #define ENET_MMFR_OP_MASK (0x30000000U) 464 #define ENET_MMFR_OP_SHIFT (28U) 465 #define ENET_MMFR_OP_WIDTH (2U) 466 #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) 467 468 #define ENET_MMFR_ST_MASK (0xC0000000U) 469 #define ENET_MMFR_ST_SHIFT (30U) 470 #define ENET_MMFR_ST_WIDTH (2U) 471 #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) 472 /*! @} */ 473 474 /*! @name MSCR - MII Speed Control Register */ 475 /*! @{ */ 476 477 #define ENET_MSCR_MII_SPEED_MASK (0x7EU) 478 #define ENET_MSCR_MII_SPEED_SHIFT (1U) 479 #define ENET_MSCR_MII_SPEED_WIDTH (6U) 480 #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) 481 482 #define ENET_MSCR_DIS_PRE_MASK (0x80U) 483 #define ENET_MSCR_DIS_PRE_SHIFT (7U) 484 #define ENET_MSCR_DIS_PRE_WIDTH (1U) 485 #define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) 486 487 #define ENET_MSCR_HOLDTIME_MASK (0x700U) 488 #define ENET_MSCR_HOLDTIME_SHIFT (8U) 489 #define ENET_MSCR_HOLDTIME_WIDTH (3U) 490 #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) 491 /*! @} */ 492 493 /*! @name MIBC - MIB Control Register */ 494 /*! @{ */ 495 496 #define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) 497 #define ENET_MIBC_MIB_CLEAR_SHIFT (29U) 498 #define ENET_MIBC_MIB_CLEAR_WIDTH (1U) 499 #define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) 500 501 #define ENET_MIBC_MIB_IDLE_MASK (0x40000000U) 502 #define ENET_MIBC_MIB_IDLE_SHIFT (30U) 503 #define ENET_MIBC_MIB_IDLE_WIDTH (1U) 504 #define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) 505 506 #define ENET_MIBC_MIB_DIS_MASK (0x80000000U) 507 #define ENET_MIBC_MIB_DIS_SHIFT (31U) 508 #define ENET_MIBC_MIB_DIS_WIDTH (1U) 509 #define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) 510 /*! @} */ 511 512 /*! @name RCR - Receive Control Register */ 513 /*! @{ */ 514 515 #define ENET_RCR_LOOP_MASK (0x1U) 516 #define ENET_RCR_LOOP_SHIFT (0U) 517 #define ENET_RCR_LOOP_WIDTH (1U) 518 #define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) 519 520 #define ENET_RCR_DRT_MASK (0x2U) 521 #define ENET_RCR_DRT_SHIFT (1U) 522 #define ENET_RCR_DRT_WIDTH (1U) 523 #define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) 524 525 #define ENET_RCR_MII_MODE_MASK (0x4U) 526 #define ENET_RCR_MII_MODE_SHIFT (2U) 527 #define ENET_RCR_MII_MODE_WIDTH (1U) 528 #define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) 529 530 #define ENET_RCR_PROM_MASK (0x8U) 531 #define ENET_RCR_PROM_SHIFT (3U) 532 #define ENET_RCR_PROM_WIDTH (1U) 533 #define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) 534 535 #define ENET_RCR_BC_REJ_MASK (0x10U) 536 #define ENET_RCR_BC_REJ_SHIFT (4U) 537 #define ENET_RCR_BC_REJ_WIDTH (1U) 538 #define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) 539 540 #define ENET_RCR_FCE_MASK (0x20U) 541 #define ENET_RCR_FCE_SHIFT (5U) 542 #define ENET_RCR_FCE_WIDTH (1U) 543 #define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) 544 545 #define ENET_RCR_RMII_MODE_MASK (0x100U) 546 #define ENET_RCR_RMII_MODE_SHIFT (8U) 547 #define ENET_RCR_RMII_MODE_WIDTH (1U) 548 #define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) 549 550 #define ENET_RCR_RMII_10T_MASK (0x200U) 551 #define ENET_RCR_RMII_10T_SHIFT (9U) 552 #define ENET_RCR_RMII_10T_WIDTH (1U) 553 #define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) 554 555 #define ENET_RCR_PADEN_MASK (0x1000U) 556 #define ENET_RCR_PADEN_SHIFT (12U) 557 #define ENET_RCR_PADEN_WIDTH (1U) 558 #define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) 559 560 #define ENET_RCR_PAUFWD_MASK (0x2000U) 561 #define ENET_RCR_PAUFWD_SHIFT (13U) 562 #define ENET_RCR_PAUFWD_WIDTH (1U) 563 #define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) 564 565 #define ENET_RCR_CRCFWD_MASK (0x4000U) 566 #define ENET_RCR_CRCFWD_SHIFT (14U) 567 #define ENET_RCR_CRCFWD_WIDTH (1U) 568 #define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) 569 570 #define ENET_RCR_CFEN_MASK (0x8000U) 571 #define ENET_RCR_CFEN_SHIFT (15U) 572 #define ENET_RCR_CFEN_WIDTH (1U) 573 #define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) 574 575 #define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) 576 #define ENET_RCR_MAX_FL_SHIFT (16U) 577 #define ENET_RCR_MAX_FL_WIDTH (14U) 578 #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) 579 580 #define ENET_RCR_NLC_MASK (0x40000000U) 581 #define ENET_RCR_NLC_SHIFT (30U) 582 #define ENET_RCR_NLC_WIDTH (1U) 583 #define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) 584 585 #define ENET_RCR_GRS_MASK (0x80000000U) 586 #define ENET_RCR_GRS_SHIFT (31U) 587 #define ENET_RCR_GRS_WIDTH (1U) 588 #define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) 589 /*! @} */ 590 591 /*! @name TCR - Transmit Control Register */ 592 /*! @{ */ 593 594 #define ENET_TCR_GTS_MASK (0x1U) 595 #define ENET_TCR_GTS_SHIFT (0U) 596 #define ENET_TCR_GTS_WIDTH (1U) 597 #define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) 598 599 #define ENET_TCR_FDEN_MASK (0x4U) 600 #define ENET_TCR_FDEN_SHIFT (2U) 601 #define ENET_TCR_FDEN_WIDTH (1U) 602 #define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) 603 604 #define ENET_TCR_TFC_PAUSE_MASK (0x8U) 605 #define ENET_TCR_TFC_PAUSE_SHIFT (3U) 606 #define ENET_TCR_TFC_PAUSE_WIDTH (1U) 607 #define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) 608 609 #define ENET_TCR_RFC_PAUSE_MASK (0x10U) 610 #define ENET_TCR_RFC_PAUSE_SHIFT (4U) 611 #define ENET_TCR_RFC_PAUSE_WIDTH (1U) 612 #define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) 613 614 #define ENET_TCR_ADDSEL_MASK (0xE0U) 615 #define ENET_TCR_ADDSEL_SHIFT (5U) 616 #define ENET_TCR_ADDSEL_WIDTH (3U) 617 #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) 618 619 #define ENET_TCR_ADDINS_MASK (0x100U) 620 #define ENET_TCR_ADDINS_SHIFT (8U) 621 #define ENET_TCR_ADDINS_WIDTH (1U) 622 #define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) 623 624 #define ENET_TCR_CRCFWD_MASK (0x200U) 625 #define ENET_TCR_CRCFWD_SHIFT (9U) 626 #define ENET_TCR_CRCFWD_WIDTH (1U) 627 #define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) 628 /*! @} */ 629 630 /*! @name PALR - Physical Address Lower Register */ 631 /*! @{ */ 632 633 #define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) 634 #define ENET_PALR_PADDR1_SHIFT (0U) 635 #define ENET_PALR_PADDR1_WIDTH (32U) 636 #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) 637 /*! @} */ 638 639 /*! @name PAUR - Physical Address Upper Register */ 640 /*! @{ */ 641 642 #define ENET_PAUR_TYPE_MASK (0xFFFFU) 643 #define ENET_PAUR_TYPE_SHIFT (0U) 644 #define ENET_PAUR_TYPE_WIDTH (16U) 645 #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) 646 647 #define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) 648 #define ENET_PAUR_PADDR2_SHIFT (16U) 649 #define ENET_PAUR_PADDR2_WIDTH (16U) 650 #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) 651 /*! @} */ 652 653 /*! @name OPD - Opcode/Pause Duration Register */ 654 /*! @{ */ 655 656 #define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) 657 #define ENET_OPD_PAUSE_DUR_SHIFT (0U) 658 #define ENET_OPD_PAUSE_DUR_WIDTH (16U) 659 #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) 660 661 #define ENET_OPD_OPCODE_MASK (0xFFFF0000U) 662 #define ENET_OPD_OPCODE_SHIFT (16U) 663 #define ENET_OPD_OPCODE_WIDTH (16U) 664 #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) 665 /*! @} */ 666 667 /*! @name IAUR - Descriptor Individual Upper Address Register */ 668 /*! @{ */ 669 670 #define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) 671 #define ENET_IAUR_IADDR1_SHIFT (0U) 672 #define ENET_IAUR_IADDR1_WIDTH (32U) 673 #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) 674 /*! @} */ 675 676 /*! @name IALR - Descriptor Individual Lower Address Register */ 677 /*! @{ */ 678 679 #define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) 680 #define ENET_IALR_IADDR2_SHIFT (0U) 681 #define ENET_IALR_IADDR2_WIDTH (32U) 682 #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) 683 /*! @} */ 684 685 /*! @name GAUR - Descriptor Group Upper Address Register */ 686 /*! @{ */ 687 688 #define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) 689 #define ENET_GAUR_GADDR1_SHIFT (0U) 690 #define ENET_GAUR_GADDR1_WIDTH (32U) 691 #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) 692 /*! @} */ 693 694 /*! @name GALR - Descriptor Group Lower Address Register */ 695 /*! @{ */ 696 697 #define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) 698 #define ENET_GALR_GADDR2_SHIFT (0U) 699 #define ENET_GALR_GADDR2_WIDTH (32U) 700 #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) 701 /*! @} */ 702 703 /*! @name TFWR - Transmit FIFO Watermark Register */ 704 /*! @{ */ 705 706 #define ENET_TFWR_TFWR_MASK (0x3FU) 707 #define ENET_TFWR_TFWR_SHIFT (0U) 708 #define ENET_TFWR_TFWR_WIDTH (6U) 709 #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) 710 711 #define ENET_TFWR_STRFWD_MASK (0x100U) 712 #define ENET_TFWR_STRFWD_SHIFT (8U) 713 #define ENET_TFWR_STRFWD_WIDTH (1U) 714 #define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) 715 /*! @} */ 716 717 /*! @name RDSR - Receive Descriptor Ring Start Register */ 718 /*! @{ */ 719 720 #define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) 721 #define ENET_RDSR_R_DES_START_SHIFT (3U) 722 #define ENET_RDSR_R_DES_START_WIDTH (29U) 723 #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) 724 /*! @} */ 725 726 /*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */ 727 /*! @{ */ 728 729 #define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) 730 #define ENET_TDSR_X_DES_START_SHIFT (3U) 731 #define ENET_TDSR_X_DES_START_WIDTH (29U) 732 #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) 733 /*! @} */ 734 735 /*! @name MRBR - Maximum Receive Buffer Size Register */ 736 /*! @{ */ 737 738 #define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) 739 #define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) 740 #define ENET_MRBR_R_BUF_SIZE_WIDTH (10U) 741 #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) 742 /*! @} */ 743 744 /*! @name RSFL - Receive FIFO Section Full Threshold */ 745 /*! @{ */ 746 747 #define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU) 748 #define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) 749 #define ENET_RSFL_RX_SECTION_FULL_WIDTH (8U) 750 #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) 751 /*! @} */ 752 753 /*! @name RSEM - Receive FIFO Section Empty Threshold */ 754 /*! @{ */ 755 756 #define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU) 757 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) 758 #define ENET_RSEM_RX_SECTION_EMPTY_WIDTH (8U) 759 #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) 760 761 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) 762 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) 763 #define ENET_RSEM_STAT_SECTION_EMPTY_WIDTH (5U) 764 #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) 765 /*! @} */ 766 767 /*! @name RAEM - Receive FIFO Almost Empty Threshold */ 768 /*! @{ */ 769 770 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU) 771 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) 772 #define ENET_RAEM_RX_ALMOST_EMPTY_WIDTH (8U) 773 #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) 774 /*! @} */ 775 776 /*! @name RAFL - Receive FIFO Almost Full Threshold */ 777 /*! @{ */ 778 779 #define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU) 780 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) 781 #define ENET_RAFL_RX_ALMOST_FULL_WIDTH (8U) 782 #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) 783 /*! @} */ 784 785 /*! @name TSEM - Transmit FIFO Section Empty Threshold */ 786 /*! @{ */ 787 788 #define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU) 789 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) 790 #define ENET_TSEM_TX_SECTION_EMPTY_WIDTH (8U) 791 #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) 792 /*! @} */ 793 794 /*! @name TAEM - Transmit FIFO Almost Empty Threshold */ 795 /*! @{ */ 796 797 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU) 798 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) 799 #define ENET_TAEM_TX_ALMOST_EMPTY_WIDTH (8U) 800 #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) 801 /*! @} */ 802 803 /*! @name TAFL - Transmit FIFO Almost Full Threshold */ 804 /*! @{ */ 805 806 #define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU) 807 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) 808 #define ENET_TAFL_TX_ALMOST_FULL_WIDTH (8U) 809 #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) 810 /*! @} */ 811 812 /*! @name TIPG - Transmit Inter-Packet Gap */ 813 /*! @{ */ 814 815 #define ENET_TIPG_IPG_MASK (0x1FU) 816 #define ENET_TIPG_IPG_SHIFT (0U) 817 #define ENET_TIPG_IPG_WIDTH (5U) 818 #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) 819 /*! @} */ 820 821 /*! @name FTRL - Frame Truncation Length */ 822 /*! @{ */ 823 824 #define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) 825 #define ENET_FTRL_TRUNC_FL_SHIFT (0U) 826 #define ENET_FTRL_TRUNC_FL_WIDTH (14U) 827 #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) 828 /*! @} */ 829 830 /*! @name TACC - Transmit Accelerator Function Configuration */ 831 /*! @{ */ 832 833 #define ENET_TACC_SHIFT16_MASK (0x1U) 834 #define ENET_TACC_SHIFT16_SHIFT (0U) 835 #define ENET_TACC_SHIFT16_WIDTH (1U) 836 #define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) 837 838 #define ENET_TACC_IPCHK_MASK (0x8U) 839 #define ENET_TACC_IPCHK_SHIFT (3U) 840 #define ENET_TACC_IPCHK_WIDTH (1U) 841 #define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) 842 843 #define ENET_TACC_PROCHK_MASK (0x10U) 844 #define ENET_TACC_PROCHK_SHIFT (4U) 845 #define ENET_TACC_PROCHK_WIDTH (1U) 846 #define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) 847 /*! @} */ 848 849 /*! @name RACC - Receive Accelerator Function Configuration */ 850 /*! @{ */ 851 852 #define ENET_RACC_PADREM_MASK (0x1U) 853 #define ENET_RACC_PADREM_SHIFT (0U) 854 #define ENET_RACC_PADREM_WIDTH (1U) 855 #define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) 856 857 #define ENET_RACC_IPDIS_MASK (0x2U) 858 #define ENET_RACC_IPDIS_SHIFT (1U) 859 #define ENET_RACC_IPDIS_WIDTH (1U) 860 #define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) 861 862 #define ENET_RACC_PRODIS_MASK (0x4U) 863 #define ENET_RACC_PRODIS_SHIFT (2U) 864 #define ENET_RACC_PRODIS_WIDTH (1U) 865 #define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) 866 867 #define ENET_RACC_LINEDIS_MASK (0x40U) 868 #define ENET_RACC_LINEDIS_SHIFT (6U) 869 #define ENET_RACC_LINEDIS_WIDTH (1U) 870 #define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) 871 872 #define ENET_RACC_SHIFT16_MASK (0x80U) 873 #define ENET_RACC_SHIFT16_SHIFT (7U) 874 #define ENET_RACC_SHIFT16_WIDTH (1U) 875 #define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) 876 /*! @} */ 877 878 /*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ 879 /*! @{ */ 880 881 #define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) 882 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) 883 #define ENET_RMON_T_PACKETS_TXPKTS_WIDTH (16U) 884 #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) 885 /*! @} */ 886 887 /*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ 888 /*! @{ */ 889 890 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) 891 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) 892 #define ENET_RMON_T_BC_PKT_TXPKTS_WIDTH (16U) 893 #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) 894 /*! @} */ 895 896 /*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ 897 /*! @{ */ 898 899 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) 900 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) 901 #define ENET_RMON_T_MC_PKT_TXPKTS_WIDTH (16U) 902 #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) 903 /*! @} */ 904 905 /*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ 906 /*! @{ */ 907 908 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) 909 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) 910 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_WIDTH (16U) 911 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) 912 /*! @} */ 913 914 /*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ 915 /*! @{ */ 916 917 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) 918 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) 919 #define ENET_RMON_T_UNDERSIZE_TXPKTS_WIDTH (16U) 920 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) 921 /*! @} */ 922 923 /*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ 924 /*! @{ */ 925 926 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) 927 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) 928 #define ENET_RMON_T_OVERSIZE_TXPKTS_WIDTH (16U) 929 #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) 930 /*! @} */ 931 932 /*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ 933 /*! @{ */ 934 935 #define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) 936 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) 937 #define ENET_RMON_T_FRAG_TXPKTS_WIDTH (16U) 938 #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) 939 /*! @} */ 940 941 /*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ 942 /*! @{ */ 943 944 #define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) 945 #define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) 946 #define ENET_RMON_T_JAB_TXPKTS_WIDTH (16U) 947 #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) 948 /*! @} */ 949 950 /*! @name RMON_T_COL - Tx Collision Count Statistic Register */ 951 /*! @{ */ 952 953 #define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) 954 #define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) 955 #define ENET_RMON_T_COL_TXPKTS_WIDTH (16U) 956 #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) 957 /*! @} */ 958 959 /*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ 960 /*! @{ */ 961 962 #define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) 963 #define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) 964 #define ENET_RMON_T_P64_TXPKTS_WIDTH (16U) 965 #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) 966 /*! @} */ 967 968 /*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ 969 /*! @{ */ 970 971 #define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) 972 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) 973 #define ENET_RMON_T_P65TO127_TXPKTS_WIDTH (16U) 974 #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) 975 /*! @} */ 976 977 /*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ 978 /*! @{ */ 979 980 #define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) 981 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) 982 #define ENET_RMON_T_P128TO255_TXPKTS_WIDTH (16U) 983 #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) 984 /*! @} */ 985 986 /*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ 987 /*! @{ */ 988 989 #define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) 990 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) 991 #define ENET_RMON_T_P256TO511_TXPKTS_WIDTH (16U) 992 #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) 993 /*! @} */ 994 995 /*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ 996 /*! @{ */ 997 998 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) 999 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) 1000 #define ENET_RMON_T_P512TO1023_TXPKTS_WIDTH (16U) 1001 #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) 1002 /*! @} */ 1003 1004 /*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ 1005 /*! @{ */ 1006 1007 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) 1008 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) 1009 #define ENET_RMON_T_P1024TO2047_TXPKTS_WIDTH (16U) 1010 #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) 1011 /*! @} */ 1012 1013 /*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ 1014 /*! @{ */ 1015 1016 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) 1017 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) 1018 #define ENET_RMON_T_P_GTE2048_TXPKTS_WIDTH (16U) 1019 #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) 1020 /*! @} */ 1021 1022 /*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ 1023 /*! @{ */ 1024 1025 #define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) 1026 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) 1027 #define ENET_RMON_T_OCTETS_TXOCTS_WIDTH (32U) 1028 #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) 1029 /*! @} */ 1030 1031 /*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ 1032 /*! @{ */ 1033 1034 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) 1035 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) 1036 #define ENET_IEEE_T_FRAME_OK_COUNT_WIDTH (16U) 1037 #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) 1038 /*! @} */ 1039 1040 /*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ 1041 /*! @{ */ 1042 1043 #define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) 1044 #define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) 1045 #define ENET_IEEE_T_1COL_COUNT_WIDTH (16U) 1046 #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) 1047 /*! @} */ 1048 1049 /*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ 1050 /*! @{ */ 1051 1052 #define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) 1053 #define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) 1054 #define ENET_IEEE_T_MCOL_COUNT_WIDTH (16U) 1055 #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) 1056 /*! @} */ 1057 1058 /*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ 1059 /*! @{ */ 1060 1061 #define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) 1062 #define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) 1063 #define ENET_IEEE_T_DEF_COUNT_WIDTH (16U) 1064 #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) 1065 /*! @} */ 1066 1067 /*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ 1068 /*! @{ */ 1069 1070 #define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) 1071 #define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) 1072 #define ENET_IEEE_T_LCOL_COUNT_WIDTH (16U) 1073 #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) 1074 /*! @} */ 1075 1076 /*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ 1077 /*! @{ */ 1078 1079 #define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) 1080 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) 1081 #define ENET_IEEE_T_EXCOL_COUNT_WIDTH (16U) 1082 #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) 1083 /*! @} */ 1084 1085 /*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ 1086 /*! @{ */ 1087 1088 #define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) 1089 #define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) 1090 #define ENET_IEEE_T_MACERR_COUNT_WIDTH (16U) 1091 #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) 1092 /*! @} */ 1093 1094 /*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ 1095 /*! @{ */ 1096 1097 #define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) 1098 #define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) 1099 #define ENET_IEEE_T_CSERR_COUNT_WIDTH (16U) 1100 #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) 1101 /*! @} */ 1102 1103 /*! @name IEEE_T_SQE - Reserved Statistic Register */ 1104 /*! @{ */ 1105 1106 #define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU) 1107 #define ENET_IEEE_T_SQE_COUNT_SHIFT (0U) 1108 #define ENET_IEEE_T_SQE_COUNT_WIDTH (16U) 1109 #define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK) 1110 /*! @} */ 1111 1112 /*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ 1113 /*! @{ */ 1114 1115 #define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) 1116 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) 1117 #define ENET_IEEE_T_FDXFC_COUNT_WIDTH (16U) 1118 #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) 1119 /*! @} */ 1120 1121 /*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ 1122 /*! @{ */ 1123 1124 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) 1125 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) 1126 #define ENET_IEEE_T_OCTETS_OK_COUNT_WIDTH (32U) 1127 #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) 1128 /*! @} */ 1129 1130 /*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ 1131 /*! @{ */ 1132 1133 #define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) 1134 #define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) 1135 #define ENET_RMON_R_PACKETS_COUNT_WIDTH (16U) 1136 #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) 1137 /*! @} */ 1138 1139 /*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ 1140 /*! @{ */ 1141 1142 #define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) 1143 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) 1144 #define ENET_RMON_R_BC_PKT_COUNT_WIDTH (16U) 1145 #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) 1146 /*! @} */ 1147 1148 /*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ 1149 /*! @{ */ 1150 1151 #define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) 1152 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) 1153 #define ENET_RMON_R_MC_PKT_COUNT_WIDTH (16U) 1154 #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) 1155 /*! @} */ 1156 1157 /*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ 1158 /*! @{ */ 1159 1160 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) 1161 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) 1162 #define ENET_RMON_R_CRC_ALIGN_COUNT_WIDTH (16U) 1163 #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) 1164 /*! @} */ 1165 1166 /*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ 1167 /*! @{ */ 1168 1169 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) 1170 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) 1171 #define ENET_RMON_R_UNDERSIZE_COUNT_WIDTH (16U) 1172 #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) 1173 /*! @} */ 1174 1175 /*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ 1176 /*! @{ */ 1177 1178 #define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) 1179 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) 1180 #define ENET_RMON_R_OVERSIZE_COUNT_WIDTH (16U) 1181 #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) 1182 /*! @} */ 1183 1184 /*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ 1185 /*! @{ */ 1186 1187 #define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) 1188 #define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) 1189 #define ENET_RMON_R_FRAG_COUNT_WIDTH (16U) 1190 #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) 1191 /*! @} */ 1192 1193 /*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ 1194 /*! @{ */ 1195 1196 #define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) 1197 #define ENET_RMON_R_JAB_COUNT_SHIFT (0U) 1198 #define ENET_RMON_R_JAB_COUNT_WIDTH (16U) 1199 #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) 1200 /*! @} */ 1201 1202 /*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ 1203 /*! @{ */ 1204 1205 #define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) 1206 #define ENET_RMON_R_P64_COUNT_SHIFT (0U) 1207 #define ENET_RMON_R_P64_COUNT_WIDTH (16U) 1208 #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) 1209 /*! @} */ 1210 1211 /*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ 1212 /*! @{ */ 1213 1214 #define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) 1215 #define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) 1216 #define ENET_RMON_R_P65TO127_COUNT_WIDTH (16U) 1217 #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) 1218 /*! @} */ 1219 1220 /*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ 1221 /*! @{ */ 1222 1223 #define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) 1224 #define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) 1225 #define ENET_RMON_R_P128TO255_COUNT_WIDTH (16U) 1226 #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) 1227 /*! @} */ 1228 1229 /*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ 1230 /*! @{ */ 1231 1232 #define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) 1233 #define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) 1234 #define ENET_RMON_R_P256TO511_COUNT_WIDTH (16U) 1235 #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) 1236 /*! @} */ 1237 1238 /*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ 1239 /*! @{ */ 1240 1241 #define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) 1242 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) 1243 #define ENET_RMON_R_P512TO1023_COUNT_WIDTH (16U) 1244 #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) 1245 /*! @} */ 1246 1247 /*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ 1248 /*! @{ */ 1249 1250 #define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) 1251 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) 1252 #define ENET_RMON_R_P1024TO2047_COUNT_WIDTH (16U) 1253 #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) 1254 /*! @} */ 1255 1256 /*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ 1257 /*! @{ */ 1258 1259 #define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) 1260 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) 1261 #define ENET_RMON_R_P_GTE2048_COUNT_WIDTH (16U) 1262 #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) 1263 /*! @} */ 1264 1265 /*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ 1266 /*! @{ */ 1267 1268 #define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) 1269 #define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) 1270 #define ENET_RMON_R_OCTETS_COUNT_WIDTH (32U) 1271 #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) 1272 /*! @} */ 1273 1274 /*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ 1275 /*! @{ */ 1276 1277 #define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) 1278 #define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) 1279 #define ENET_IEEE_R_DROP_COUNT_WIDTH (16U) 1280 #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) 1281 /*! @} */ 1282 1283 /*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ 1284 /*! @{ */ 1285 1286 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) 1287 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) 1288 #define ENET_IEEE_R_FRAME_OK_COUNT_WIDTH (16U) 1289 #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) 1290 /*! @} */ 1291 1292 /*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ 1293 /*! @{ */ 1294 1295 #define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) 1296 #define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) 1297 #define ENET_IEEE_R_CRC_COUNT_WIDTH (16U) 1298 #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) 1299 /*! @} */ 1300 1301 /*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ 1302 /*! @{ */ 1303 1304 #define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) 1305 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) 1306 #define ENET_IEEE_R_ALIGN_COUNT_WIDTH (16U) 1307 #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) 1308 /*! @} */ 1309 1310 /*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ 1311 /*! @{ */ 1312 1313 #define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) 1314 #define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) 1315 #define ENET_IEEE_R_MACERR_COUNT_WIDTH (16U) 1316 #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) 1317 /*! @} */ 1318 1319 /*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ 1320 /*! @{ */ 1321 1322 #define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) 1323 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) 1324 #define ENET_IEEE_R_FDXFC_COUNT_WIDTH (16U) 1325 #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) 1326 /*! @} */ 1327 1328 /*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ 1329 /*! @{ */ 1330 1331 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) 1332 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) 1333 #define ENET_IEEE_R_OCTETS_OK_COUNT_WIDTH (32U) 1334 #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) 1335 /*! @} */ 1336 1337 /*! @name ATCR - Adjustable Timer Control Register */ 1338 /*! @{ */ 1339 1340 #define ENET_ATCR_EN_MASK (0x1U) 1341 #define ENET_ATCR_EN_SHIFT (0U) 1342 #define ENET_ATCR_EN_WIDTH (1U) 1343 #define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) 1344 1345 #define ENET_ATCR_OFFEN_MASK (0x4U) 1346 #define ENET_ATCR_OFFEN_SHIFT (2U) 1347 #define ENET_ATCR_OFFEN_WIDTH (1U) 1348 #define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) 1349 1350 #define ENET_ATCR_OFFRST_MASK (0x8U) 1351 #define ENET_ATCR_OFFRST_SHIFT (3U) 1352 #define ENET_ATCR_OFFRST_WIDTH (1U) 1353 #define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) 1354 1355 #define ENET_ATCR_PEREN_MASK (0x10U) 1356 #define ENET_ATCR_PEREN_SHIFT (4U) 1357 #define ENET_ATCR_PEREN_WIDTH (1U) 1358 #define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) 1359 1360 #define ENET_ATCR_PINPER_MASK (0x80U) 1361 #define ENET_ATCR_PINPER_SHIFT (7U) 1362 #define ENET_ATCR_PINPER_WIDTH (1U) 1363 #define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) 1364 1365 #define ENET_ATCR_RESTART_MASK (0x200U) 1366 #define ENET_ATCR_RESTART_SHIFT (9U) 1367 #define ENET_ATCR_RESTART_WIDTH (1U) 1368 #define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) 1369 1370 #define ENET_ATCR_CAPTURE_MASK (0x800U) 1371 #define ENET_ATCR_CAPTURE_SHIFT (11U) 1372 #define ENET_ATCR_CAPTURE_WIDTH (1U) 1373 #define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) 1374 1375 #define ENET_ATCR_SLAVE_MASK (0x2000U) 1376 #define ENET_ATCR_SLAVE_SHIFT (13U) 1377 #define ENET_ATCR_SLAVE_WIDTH (1U) 1378 #define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) 1379 /*! @} */ 1380 1381 /*! @name ATVR - Timer Value Register */ 1382 /*! @{ */ 1383 1384 #define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) 1385 #define ENET_ATVR_ATIME_SHIFT (0U) 1386 #define ENET_ATVR_ATIME_WIDTH (32U) 1387 #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) 1388 /*! @} */ 1389 1390 /*! @name ATOFF - Timer Offset Register */ 1391 /*! @{ */ 1392 1393 #define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) 1394 #define ENET_ATOFF_OFFSET_SHIFT (0U) 1395 #define ENET_ATOFF_OFFSET_WIDTH (32U) 1396 #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) 1397 /*! @} */ 1398 1399 /*! @name ATPER - Timer Period Register */ 1400 /*! @{ */ 1401 1402 #define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) 1403 #define ENET_ATPER_PERIOD_SHIFT (0U) 1404 #define ENET_ATPER_PERIOD_WIDTH (32U) 1405 #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) 1406 /*! @} */ 1407 1408 /*! @name ATCOR - Timer Correction Register */ 1409 /*! @{ */ 1410 1411 #define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) 1412 #define ENET_ATCOR_COR_SHIFT (0U) 1413 #define ENET_ATCOR_COR_WIDTH (31U) 1414 #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) 1415 /*! @} */ 1416 1417 /*! @name ATINC - Time-Stamping Clock Period Register */ 1418 /*! @{ */ 1419 1420 #define ENET_ATINC_INC_MASK (0x7FU) 1421 #define ENET_ATINC_INC_SHIFT (0U) 1422 #define ENET_ATINC_INC_WIDTH (7U) 1423 #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) 1424 1425 #define ENET_ATINC_INC_CORR_MASK (0x7F00U) 1426 #define ENET_ATINC_INC_CORR_SHIFT (8U) 1427 #define ENET_ATINC_INC_CORR_WIDTH (7U) 1428 #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) 1429 /*! @} */ 1430 1431 /*! @name ATSTMP - Timestamp of Last Transmitted Frame */ 1432 /*! @{ */ 1433 1434 #define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) 1435 #define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) 1436 #define ENET_ATSTMP_TIMESTAMP_WIDTH (32U) 1437 #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) 1438 /*! @} */ 1439 1440 /*! @name TGSR - Timer Global Status Register */ 1441 /*! @{ */ 1442 1443 #define ENET_TGSR_TF0_MASK (0x1U) 1444 #define ENET_TGSR_TF0_SHIFT (0U) 1445 #define ENET_TGSR_TF0_WIDTH (1U) 1446 #define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) 1447 1448 #define ENET_TGSR_TF1_MASK (0x2U) 1449 #define ENET_TGSR_TF1_SHIFT (1U) 1450 #define ENET_TGSR_TF1_WIDTH (1U) 1451 #define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) 1452 1453 #define ENET_TGSR_TF2_MASK (0x4U) 1454 #define ENET_TGSR_TF2_SHIFT (2U) 1455 #define ENET_TGSR_TF2_WIDTH (1U) 1456 #define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) 1457 1458 #define ENET_TGSR_TF3_MASK (0x8U) 1459 #define ENET_TGSR_TF3_SHIFT (3U) 1460 #define ENET_TGSR_TF3_WIDTH (1U) 1461 #define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) 1462 /*! @} */ 1463 1464 /*! @name TCSR - Timer Control Status Register */ 1465 /*! @{ */ 1466 1467 #define ENET_TCSR_TDRE_MASK (0x1U) 1468 #define ENET_TCSR_TDRE_SHIFT (0U) 1469 #define ENET_TCSR_TDRE_WIDTH (1U) 1470 #define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) 1471 1472 #define ENET_TCSR_TMODE_MASK (0x3CU) 1473 #define ENET_TCSR_TMODE_SHIFT (2U) 1474 #define ENET_TCSR_TMODE_WIDTH (4U) 1475 #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) 1476 1477 #define ENET_TCSR_TIE_MASK (0x40U) 1478 #define ENET_TCSR_TIE_SHIFT (6U) 1479 #define ENET_TCSR_TIE_WIDTH (1U) 1480 #define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) 1481 1482 #define ENET_TCSR_TF_MASK (0x80U) 1483 #define ENET_TCSR_TF_SHIFT (7U) 1484 #define ENET_TCSR_TF_WIDTH (1U) 1485 #define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) 1486 /*! @} */ 1487 1488 /*! @name TCCR - Timer Compare Capture Register */ 1489 /*! @{ */ 1490 1491 #define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) 1492 #define ENET_TCCR_TCC_SHIFT (0U) 1493 #define ENET_TCCR_TCC_WIDTH (32U) 1494 #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) 1495 /*! @} */ 1496 1497 /*! 1498 * @} 1499 */ /* end of group ENET_Register_Masks */ 1500 1501 /*! 1502 * @} 1503 */ /* end of group ENET_Peripheral_Access_Layer */ 1504 1505 #endif /* #if !defined(S32K148_ENET_H_) */ 1506
