1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K146_SCG.h 10 * @version 1.1 11 * @date 2022-01-31 12 * @brief Peripheral Access Layer for S32K146_SCG 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K146_SCG_H_) /* Check if memory map has not been already included */ 58 #define S32K146_SCG_H_ 59 60 #include "S32K146_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SCG Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SCG - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ 74 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ 75 uint8_t RESERVED_0[8]; 76 __I uint32_t CSR; /**< Clock Status Register, offset: 0x10 */ 77 __IO uint32_t RCCR; /**< Run Clock Control Register, offset: 0x14 */ 78 __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ 79 __IO uint32_t HCCR; /**< HSRUN Clock Control Register, offset: 0x1C */ 80 __IO uint32_t CLKOUTCNFG; /**< SCG CLKOUT Configuration Register, offset: 0x20 */ 81 uint8_t RESERVED_1[220]; 82 __IO uint32_t SOSCCSR; /**< System OSC Control Status Register, offset: 0x100 */ 83 __IO uint32_t SOSCDIV; /**< System OSC Divide Register, offset: 0x104 */ 84 __IO uint32_t SOSCCFG; /**< System Oscillator Configuration Register, offset: 0x108 */ 85 uint8_t RESERVED_2[244]; 86 __IO uint32_t SIRCCSR; /**< Slow IRC Control Status Register, offset: 0x200 */ 87 __IO uint32_t SIRCDIV; /**< Slow IRC Divide Register, offset: 0x204 */ 88 __IO uint32_t SIRCCFG; /**< Slow IRC Configuration Register, offset: 0x208 */ 89 uint8_t RESERVED_3[244]; 90 __IO uint32_t FIRCCSR; /**< Fast IRC Control Status Register, offset: 0x300 */ 91 __IO uint32_t FIRCDIV; /**< Fast IRC Divide Register, offset: 0x304 */ 92 __IO uint32_t FIRCCFG; /**< Fast IRC Configuration Register, offset: 0x308 */ 93 uint8_t RESERVED_4[756]; 94 __IO uint32_t SPLLCSR; /**< System PLL Control Status Register, offset: 0x600 */ 95 __IO uint32_t SPLLDIV; /**< System PLL Divide Register, offset: 0x604 */ 96 __IO uint32_t SPLLCFG; /**< System PLL Configuration Register, offset: 0x608 */ 97 } SCG_Type, *SCG_MemMapPtr; 98 99 /** Number of instances of the SCG module. */ 100 #define SCG_INSTANCE_COUNT (1u) 101 102 /* SCG - Peripheral instance base addresses */ 103 /** Peripheral SCG base address */ 104 #define IP_SCG_BASE (0x40064000u) 105 /** Peripheral SCG base pointer */ 106 #define IP_SCG ((SCG_Type *)IP_SCG_BASE) 107 /** Array initializer of SCG peripheral base addresses */ 108 #define IP_SCG_BASE_ADDRS { IP_SCG_BASE } 109 /** Array initializer of SCG peripheral base pointers */ 110 #define IP_SCG_BASE_PTRS { IP_SCG } 111 112 /* ---------------------------------------------------------------------------- 113 -- SCG Register Masks 114 ---------------------------------------------------------------------------- */ 115 116 /*! 117 * @addtogroup SCG_Register_Masks SCG Register Masks 118 * @{ 119 */ 120 121 /*! @name VERID - Version ID Register */ 122 /*! @{ */ 123 124 #define SCG_VERID_VERSION_MASK (0xFFFFFFFFU) 125 #define SCG_VERID_VERSION_SHIFT (0U) 126 #define SCG_VERID_VERSION_WIDTH (32U) 127 #define SCG_VERID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SCG_VERID_VERSION_SHIFT)) & SCG_VERID_VERSION_MASK) 128 /*! @} */ 129 130 /*! @name PARAM - Parameter Register */ 131 /*! @{ */ 132 133 #define SCG_PARAM_CLKPRES_MASK (0xFFU) 134 #define SCG_PARAM_CLKPRES_SHIFT (0U) 135 #define SCG_PARAM_CLKPRES_WIDTH (8U) 136 #define SCG_PARAM_CLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_CLKPRES_SHIFT)) & SCG_PARAM_CLKPRES_MASK) 137 138 #define SCG_PARAM_DIVPRES_MASK (0xF8000000U) 139 #define SCG_PARAM_DIVPRES_SHIFT (27U) 140 #define SCG_PARAM_DIVPRES_WIDTH (5U) 141 #define SCG_PARAM_DIVPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_DIVPRES_SHIFT)) & SCG_PARAM_DIVPRES_MASK) 142 /*! @} */ 143 144 /*! @name CSR - Clock Status Register */ 145 /*! @{ */ 146 147 #define SCG_CSR_DIVSLOW_MASK (0xFU) 148 #define SCG_CSR_DIVSLOW_SHIFT (0U) 149 #define SCG_CSR_DIVSLOW_WIDTH (4U) 150 #define SCG_CSR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK) 151 152 #define SCG_CSR_DIVBUS_MASK (0xF0U) 153 #define SCG_CSR_DIVBUS_SHIFT (4U) 154 #define SCG_CSR_DIVBUS_WIDTH (4U) 155 #define SCG_CSR_DIVBUS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVBUS_SHIFT)) & SCG_CSR_DIVBUS_MASK) 156 157 #define SCG_CSR_DIVCORE_MASK (0xF0000U) 158 #define SCG_CSR_DIVCORE_SHIFT (16U) 159 #define SCG_CSR_DIVCORE_WIDTH (4U) 160 #define SCG_CSR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVCORE_SHIFT)) & SCG_CSR_DIVCORE_MASK) 161 162 #define SCG_CSR_SCS_MASK (0xF000000U) 163 #define SCG_CSR_SCS_SHIFT (24U) 164 #define SCG_CSR_SCS_WIDTH (4U) 165 #define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK) 166 /*! @} */ 167 168 /*! @name RCCR - Run Clock Control Register */ 169 /*! @{ */ 170 171 #define SCG_RCCR_DIVSLOW_MASK (0xFU) 172 #define SCG_RCCR_DIVSLOW_SHIFT (0U) 173 #define SCG_RCCR_DIVSLOW_WIDTH (4U) 174 #define SCG_RCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVSLOW_SHIFT)) & SCG_RCCR_DIVSLOW_MASK) 175 176 #define SCG_RCCR_DIVBUS_MASK (0xF0U) 177 #define SCG_RCCR_DIVBUS_SHIFT (4U) 178 #define SCG_RCCR_DIVBUS_WIDTH (4U) 179 #define SCG_RCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVBUS_SHIFT)) & SCG_RCCR_DIVBUS_MASK) 180 181 #define SCG_RCCR_DIVCORE_MASK (0xF0000U) 182 #define SCG_RCCR_DIVCORE_SHIFT (16U) 183 #define SCG_RCCR_DIVCORE_WIDTH (4U) 184 #define SCG_RCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVCORE_SHIFT)) & SCG_RCCR_DIVCORE_MASK) 185 186 #define SCG_RCCR_SCS_MASK (0xF000000U) 187 #define SCG_RCCR_SCS_SHIFT (24U) 188 #define SCG_RCCR_SCS_WIDTH (4U) 189 #define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK) 190 /*! @} */ 191 192 /*! @name VCCR - VLPR Clock Control Register */ 193 /*! @{ */ 194 195 #define SCG_VCCR_DIVSLOW_MASK (0xFU) 196 #define SCG_VCCR_DIVSLOW_SHIFT (0U) 197 #define SCG_VCCR_DIVSLOW_WIDTH (4U) 198 #define SCG_VCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVSLOW_SHIFT)) & SCG_VCCR_DIVSLOW_MASK) 199 200 #define SCG_VCCR_DIVBUS_MASK (0xF0U) 201 #define SCG_VCCR_DIVBUS_SHIFT (4U) 202 #define SCG_VCCR_DIVBUS_WIDTH (4U) 203 #define SCG_VCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVBUS_SHIFT)) & SCG_VCCR_DIVBUS_MASK) 204 205 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) 206 #define SCG_VCCR_DIVCORE_SHIFT (16U) 207 #define SCG_VCCR_DIVCORE_WIDTH (4U) 208 #define SCG_VCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK) 209 210 #define SCG_VCCR_SCS_MASK (0xF000000U) 211 #define SCG_VCCR_SCS_SHIFT (24U) 212 #define SCG_VCCR_SCS_WIDTH (4U) 213 #define SCG_VCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_SCS_SHIFT)) & SCG_VCCR_SCS_MASK) 214 /*! @} */ 215 216 /*! @name HCCR - HSRUN Clock Control Register */ 217 /*! @{ */ 218 219 #define SCG_HCCR_DIVSLOW_MASK (0xFU) 220 #define SCG_HCCR_DIVSLOW_SHIFT (0U) 221 #define SCG_HCCR_DIVSLOW_WIDTH (4U) 222 #define SCG_HCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVSLOW_SHIFT)) & SCG_HCCR_DIVSLOW_MASK) 223 224 #define SCG_HCCR_DIVBUS_MASK (0xF0U) 225 #define SCG_HCCR_DIVBUS_SHIFT (4U) 226 #define SCG_HCCR_DIVBUS_WIDTH (4U) 227 #define SCG_HCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVBUS_SHIFT)) & SCG_HCCR_DIVBUS_MASK) 228 229 #define SCG_HCCR_DIVCORE_MASK (0xF0000U) 230 #define SCG_HCCR_DIVCORE_SHIFT (16U) 231 #define SCG_HCCR_DIVCORE_WIDTH (4U) 232 #define SCG_HCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVCORE_SHIFT)) & SCG_HCCR_DIVCORE_MASK) 233 234 #define SCG_HCCR_SCS_MASK (0xF000000U) 235 #define SCG_HCCR_SCS_SHIFT (24U) 236 #define SCG_HCCR_SCS_WIDTH (4U) 237 #define SCG_HCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_SCS_SHIFT)) & SCG_HCCR_SCS_MASK) 238 /*! @} */ 239 240 /*! @name CLKOUTCNFG - SCG CLKOUT Configuration Register */ 241 /*! @{ */ 242 243 #define SCG_CLKOUTCNFG_CLKOUTSEL_MASK (0xF000000U) 244 #define SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT (24U) 245 #define SCG_CLKOUTCNFG_CLKOUTSEL_WIDTH (4U) 246 #define SCG_CLKOUTCNFG_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT)) & SCG_CLKOUTCNFG_CLKOUTSEL_MASK) 247 /*! @} */ 248 249 /*! @name SOSCCSR - System OSC Control Status Register */ 250 /*! @{ */ 251 252 #define SCG_SOSCCSR_SOSCEN_MASK (0x1U) 253 #define SCG_SOSCCSR_SOSCEN_SHIFT (0U) 254 #define SCG_SOSCCSR_SOSCEN_WIDTH (1U) 255 #define SCG_SOSCCSR_SOSCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK) 256 257 #define SCG_SOSCCSR_SOSCCM_MASK (0x10000U) 258 #define SCG_SOSCCSR_SOSCCM_SHIFT (16U) 259 #define SCG_SOSCCSR_SOSCCM_WIDTH (1U) 260 #define SCG_SOSCCSR_SOSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCM_SHIFT)) & SCG_SOSCCSR_SOSCCM_MASK) 261 262 #define SCG_SOSCCSR_SOSCCMRE_MASK (0x20000U) 263 #define SCG_SOSCCSR_SOSCCMRE_SHIFT (17U) 264 #define SCG_SOSCCSR_SOSCCMRE_WIDTH (1U) 265 #define SCG_SOSCCSR_SOSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCMRE_SHIFT)) & SCG_SOSCCSR_SOSCCMRE_MASK) 266 267 #define SCG_SOSCCSR_LK_MASK (0x800000U) 268 #define SCG_SOSCCSR_LK_SHIFT (23U) 269 #define SCG_SOSCCSR_LK_WIDTH (1U) 270 #define SCG_SOSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_LK_SHIFT)) & SCG_SOSCCSR_LK_MASK) 271 272 #define SCG_SOSCCSR_SOSCVLD_MASK (0x1000000U) 273 #define SCG_SOSCCSR_SOSCVLD_SHIFT (24U) 274 #define SCG_SOSCCSR_SOSCVLD_WIDTH (1U) 275 #define SCG_SOSCCSR_SOSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK) 276 277 #define SCG_SOSCCSR_SOSCSEL_MASK (0x2000000U) 278 #define SCG_SOSCCSR_SOSCSEL_SHIFT (25U) 279 #define SCG_SOSCCSR_SOSCSEL_WIDTH (1U) 280 #define SCG_SOSCCSR_SOSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSEL_SHIFT)) & SCG_SOSCCSR_SOSCSEL_MASK) 281 282 #define SCG_SOSCCSR_SOSCERR_MASK (0x4000000U) 283 #define SCG_SOSCCSR_SOSCERR_SHIFT (26U) 284 #define SCG_SOSCCSR_SOSCERR_WIDTH (1U) 285 #define SCG_SOSCCSR_SOSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERR_SHIFT)) & SCG_SOSCCSR_SOSCERR_MASK) 286 /*! @} */ 287 288 /*! @name SOSCDIV - System OSC Divide Register */ 289 /*! @{ */ 290 291 #define SCG_SOSCDIV_SOSCDIV1_MASK (0x7U) 292 #define SCG_SOSCDIV_SOSCDIV1_SHIFT (0U) 293 #define SCG_SOSCDIV_SOSCDIV1_WIDTH (3U) 294 #define SCG_SOSCDIV_SOSCDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV1_SHIFT)) & SCG_SOSCDIV_SOSCDIV1_MASK) 295 296 #define SCG_SOSCDIV_SOSCDIV2_MASK (0x700U) 297 #define SCG_SOSCDIV_SOSCDIV2_SHIFT (8U) 298 #define SCG_SOSCDIV_SOSCDIV2_WIDTH (3U) 299 #define SCG_SOSCDIV_SOSCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV2_SHIFT)) & SCG_SOSCDIV_SOSCDIV2_MASK) 300 /*! @} */ 301 302 /*! @name SOSCCFG - System Oscillator Configuration Register */ 303 /*! @{ */ 304 305 #define SCG_SOSCCFG_EREFS_MASK (0x4U) 306 #define SCG_SOSCCFG_EREFS_SHIFT (2U) 307 #define SCG_SOSCCFG_EREFS_WIDTH (1U) 308 #define SCG_SOSCCFG_EREFS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_EREFS_SHIFT)) & SCG_SOSCCFG_EREFS_MASK) 309 310 #define SCG_SOSCCFG_HGO_MASK (0x8U) 311 #define SCG_SOSCCFG_HGO_SHIFT (3U) 312 #define SCG_SOSCCFG_HGO_WIDTH (1U) 313 #define SCG_SOSCCFG_HGO(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_HGO_SHIFT)) & SCG_SOSCCFG_HGO_MASK) 314 315 #define SCG_SOSCCFG_RANGE_MASK (0x30U) 316 #define SCG_SOSCCFG_RANGE_SHIFT (4U) 317 #define SCG_SOSCCFG_RANGE_WIDTH (2U) 318 #define SCG_SOSCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_RANGE_SHIFT)) & SCG_SOSCCFG_RANGE_MASK) 319 /*! @} */ 320 321 /*! @name SIRCCSR - Slow IRC Control Status Register */ 322 /*! @{ */ 323 324 #define SCG_SIRCCSR_SIRCEN_MASK (0x1U) 325 #define SCG_SIRCCSR_SIRCEN_SHIFT (0U) 326 #define SCG_SIRCCSR_SIRCEN_WIDTH (1U) 327 #define SCG_SIRCCSR_SIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCEN_SHIFT)) & SCG_SIRCCSR_SIRCEN_MASK) 328 329 #define SCG_SIRCCSR_SIRCSTEN_MASK (0x2U) 330 #define SCG_SIRCCSR_SIRCSTEN_SHIFT (1U) 331 #define SCG_SIRCCSR_SIRCSTEN_WIDTH (1U) 332 #define SCG_SIRCCSR_SIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSTEN_SHIFT)) & SCG_SIRCCSR_SIRCSTEN_MASK) 333 334 #define SCG_SIRCCSR_SIRCLPEN_MASK (0x4U) 335 #define SCG_SIRCCSR_SIRCLPEN_SHIFT (2U) 336 #define SCG_SIRCCSR_SIRCLPEN_WIDTH (1U) 337 #define SCG_SIRCCSR_SIRCLPEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCLPEN_SHIFT)) & SCG_SIRCCSR_SIRCLPEN_MASK) 338 339 #define SCG_SIRCCSR_LK_MASK (0x800000U) 340 #define SCG_SIRCCSR_LK_SHIFT (23U) 341 #define SCG_SIRCCSR_LK_WIDTH (1U) 342 #define SCG_SIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LK_SHIFT)) & SCG_SIRCCSR_LK_MASK) 343 344 #define SCG_SIRCCSR_SIRCVLD_MASK (0x1000000U) 345 #define SCG_SIRCCSR_SIRCVLD_SHIFT (24U) 346 #define SCG_SIRCCSR_SIRCVLD_WIDTH (1U) 347 #define SCG_SIRCCSR_SIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK) 348 349 #define SCG_SIRCCSR_SIRCSEL_MASK (0x2000000U) 350 #define SCG_SIRCCSR_SIRCSEL_SHIFT (25U) 351 #define SCG_SIRCCSR_SIRCSEL_WIDTH (1U) 352 #define SCG_SIRCCSR_SIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSEL_SHIFT)) & SCG_SIRCCSR_SIRCSEL_MASK) 353 /*! @} */ 354 355 /*! @name SIRCDIV - Slow IRC Divide Register */ 356 /*! @{ */ 357 358 #define SCG_SIRCDIV_SIRCDIV1_MASK (0x7U) 359 #define SCG_SIRCDIV_SIRCDIV1_SHIFT (0U) 360 #define SCG_SIRCDIV_SIRCDIV1_WIDTH (3U) 361 #define SCG_SIRCDIV_SIRCDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV1_SHIFT)) & SCG_SIRCDIV_SIRCDIV1_MASK) 362 363 #define SCG_SIRCDIV_SIRCDIV2_MASK (0x700U) 364 #define SCG_SIRCDIV_SIRCDIV2_SHIFT (8U) 365 #define SCG_SIRCDIV_SIRCDIV2_WIDTH (3U) 366 #define SCG_SIRCDIV_SIRCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV2_SHIFT)) & SCG_SIRCDIV_SIRCDIV2_MASK) 367 /*! @} */ 368 369 /*! @name SIRCCFG - Slow IRC Configuration Register */ 370 /*! @{ */ 371 372 #define SCG_SIRCCFG_RANGE_MASK (0x1U) 373 #define SCG_SIRCCFG_RANGE_SHIFT (0U) 374 #define SCG_SIRCCFG_RANGE_WIDTH (1U) 375 #define SCG_SIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCFG_RANGE_SHIFT)) & SCG_SIRCCFG_RANGE_MASK) 376 /*! @} */ 377 378 /*! @name FIRCCSR - Fast IRC Control Status Register */ 379 /*! @{ */ 380 381 #define SCG_FIRCCSR_FIRCEN_MASK (0x1U) 382 #define SCG_FIRCCSR_FIRCEN_SHIFT (0U) 383 #define SCG_FIRCCSR_FIRCEN_WIDTH (1U) 384 #define SCG_FIRCCSR_FIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK) 385 386 #define SCG_FIRCCSR_FIRCREGOFF_MASK (0x8U) 387 #define SCG_FIRCCSR_FIRCREGOFF_SHIFT (3U) 388 #define SCG_FIRCCSR_FIRCREGOFF_WIDTH (1U) 389 #define SCG_FIRCCSR_FIRCREGOFF(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCREGOFF_SHIFT)) & SCG_FIRCCSR_FIRCREGOFF_MASK) 390 391 #define SCG_FIRCCSR_LK_MASK (0x800000U) 392 #define SCG_FIRCCSR_LK_SHIFT (23U) 393 #define SCG_FIRCCSR_LK_WIDTH (1U) 394 #define SCG_FIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_LK_SHIFT)) & SCG_FIRCCSR_LK_MASK) 395 396 #define SCG_FIRCCSR_FIRCVLD_MASK (0x1000000U) 397 #define SCG_FIRCCSR_FIRCVLD_SHIFT (24U) 398 #define SCG_FIRCCSR_FIRCVLD_WIDTH (1U) 399 #define SCG_FIRCCSR_FIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCVLD_SHIFT)) & SCG_FIRCCSR_FIRCVLD_MASK) 400 401 #define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U) 402 #define SCG_FIRCCSR_FIRCSEL_SHIFT (25U) 403 #define SCG_FIRCCSR_FIRCSEL_WIDTH (1U) 404 #define SCG_FIRCCSR_FIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK) 405 /*! @} */ 406 407 /*! @name FIRCDIV - Fast IRC Divide Register */ 408 /*! @{ */ 409 410 #define SCG_FIRCDIV_FIRCDIV1_MASK (0x7U) 411 #define SCG_FIRCDIV_FIRCDIV1_SHIFT (0U) 412 #define SCG_FIRCDIV_FIRCDIV1_WIDTH (3U) 413 #define SCG_FIRCDIV_FIRCDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV1_SHIFT)) & SCG_FIRCDIV_FIRCDIV1_MASK) 414 415 #define SCG_FIRCDIV_FIRCDIV2_MASK (0x700U) 416 #define SCG_FIRCDIV_FIRCDIV2_SHIFT (8U) 417 #define SCG_FIRCDIV_FIRCDIV2_WIDTH (3U) 418 #define SCG_FIRCDIV_FIRCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV2_SHIFT)) & SCG_FIRCDIV_FIRCDIV2_MASK) 419 /*! @} */ 420 421 /*! @name FIRCCFG - Fast IRC Configuration Register */ 422 /*! @{ */ 423 424 #define SCG_FIRCCFG_RANGE_MASK (0x3U) 425 #define SCG_FIRCCFG_RANGE_SHIFT (0U) 426 #define SCG_FIRCCFG_RANGE_WIDTH (2U) 427 #define SCG_FIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_RANGE_SHIFT)) & SCG_FIRCCFG_RANGE_MASK) 428 /*! @} */ 429 430 /*! @name SPLLCSR - System PLL Control Status Register */ 431 /*! @{ */ 432 433 #define SCG_SPLLCSR_SPLLEN_MASK (0x1U) 434 #define SCG_SPLLCSR_SPLLEN_SHIFT (0U) 435 #define SCG_SPLLCSR_SPLLEN_WIDTH (1U) 436 #define SCG_SPLLCSR_SPLLEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLEN_SHIFT)) & SCG_SPLLCSR_SPLLEN_MASK) 437 438 #define SCG_SPLLCSR_SPLLCM_MASK (0x10000U) 439 #define SCG_SPLLCSR_SPLLCM_SHIFT (16U) 440 #define SCG_SPLLCSR_SPLLCM_WIDTH (1U) 441 #define SCG_SPLLCSR_SPLLCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCM_SHIFT)) & SCG_SPLLCSR_SPLLCM_MASK) 442 443 #define SCG_SPLLCSR_SPLLCMRE_MASK (0x20000U) 444 #define SCG_SPLLCSR_SPLLCMRE_SHIFT (17U) 445 #define SCG_SPLLCSR_SPLLCMRE_WIDTH (1U) 446 #define SCG_SPLLCSR_SPLLCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCMRE_SHIFT)) & SCG_SPLLCSR_SPLLCMRE_MASK) 447 448 #define SCG_SPLLCSR_LK_MASK (0x800000U) 449 #define SCG_SPLLCSR_LK_SHIFT (23U) 450 #define SCG_SPLLCSR_LK_WIDTH (1U) 451 #define SCG_SPLLCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_LK_SHIFT)) & SCG_SPLLCSR_LK_MASK) 452 453 #define SCG_SPLLCSR_SPLLVLD_MASK (0x1000000U) 454 #define SCG_SPLLCSR_SPLLVLD_SHIFT (24U) 455 #define SCG_SPLLCSR_SPLLVLD_WIDTH (1U) 456 #define SCG_SPLLCSR_SPLLVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLVLD_SHIFT)) & SCG_SPLLCSR_SPLLVLD_MASK) 457 458 #define SCG_SPLLCSR_SPLLSEL_MASK (0x2000000U) 459 #define SCG_SPLLCSR_SPLLSEL_SHIFT (25U) 460 #define SCG_SPLLCSR_SPLLSEL_WIDTH (1U) 461 #define SCG_SPLLCSR_SPLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLSEL_SHIFT)) & SCG_SPLLCSR_SPLLSEL_MASK) 462 463 #define SCG_SPLLCSR_SPLLERR_MASK (0x4000000U) 464 #define SCG_SPLLCSR_SPLLERR_SHIFT (26U) 465 #define SCG_SPLLCSR_SPLLERR_WIDTH (1U) 466 #define SCG_SPLLCSR_SPLLERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLERR_SHIFT)) & SCG_SPLLCSR_SPLLERR_MASK) 467 /*! @} */ 468 469 /*! @name SPLLDIV - System PLL Divide Register */ 470 /*! @{ */ 471 472 #define SCG_SPLLDIV_SPLLDIV1_MASK (0x7U) 473 #define SCG_SPLLDIV_SPLLDIV1_SHIFT (0U) 474 #define SCG_SPLLDIV_SPLLDIV1_WIDTH (3U) 475 #define SCG_SPLLDIV_SPLLDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDIV_SPLLDIV1_SHIFT)) & SCG_SPLLDIV_SPLLDIV1_MASK) 476 477 #define SCG_SPLLDIV_SPLLDIV2_MASK (0x700U) 478 #define SCG_SPLLDIV_SPLLDIV2_SHIFT (8U) 479 #define SCG_SPLLDIV_SPLLDIV2_WIDTH (3U) 480 #define SCG_SPLLDIV_SPLLDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDIV_SPLLDIV2_SHIFT)) & SCG_SPLLDIV_SPLLDIV2_MASK) 481 /*! @} */ 482 483 /*! @name SPLLCFG - System PLL Configuration Register */ 484 /*! @{ */ 485 486 #define SCG_SPLLCFG_PREDIV_MASK (0x700U) 487 #define SCG_SPLLCFG_PREDIV_SHIFT (8U) 488 #define SCG_SPLLCFG_PREDIV_WIDTH (3U) 489 #define SCG_SPLLCFG_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCFG_PREDIV_SHIFT)) & SCG_SPLLCFG_PREDIV_MASK) 490 491 #define SCG_SPLLCFG_MULT_MASK (0x1F0000U) 492 #define SCG_SPLLCFG_MULT_SHIFT (16U) 493 #define SCG_SPLLCFG_MULT_WIDTH (5U) 494 #define SCG_SPLLCFG_MULT(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCFG_MULT_SHIFT)) & SCG_SPLLCFG_MULT_MASK) 495 /*! @} */ 496 497 /*! 498 * @} 499 */ /* end of group SCG_Register_Masks */ 500 501 /*! 502 * @} 503 */ /* end of group SCG_Peripheral_Access_Layer */ 504 505 #endif /* #if !defined(S32K146_SCG_H_) */ 506
