1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K146_LPUART.h 10 * @version 1.1 11 * @date 2022-01-31 12 * @brief Peripheral Access Layer for S32K146_LPUART 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K146_LPUART_H_) /* Check if memory map has not been already included */ 58 #define S32K146_LPUART_H_ 59 60 #include "S32K146_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- LPUART Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer 68 * @{ 69 */ 70 71 /** LPUART - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ 74 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ 75 __IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */ 76 __IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */ 77 __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x10 */ 78 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */ 79 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */ 80 __IO uint32_t DATA; /**< LPUART Data Register, offset: 0x1C */ 81 __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x20 */ 82 __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x24 */ 83 __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */ 84 __IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x2C */ 85 } LPUART_Type, *LPUART_MemMapPtr; 86 87 /** Number of instances of the LPUART module. */ 88 #define LPUART_INSTANCE_COUNT (3u) 89 90 /* LPUART - Peripheral instance base addresses */ 91 /** Peripheral LPUART0 base address */ 92 #define IP_LPUART0_BASE (0x4006A000u) 93 /** Peripheral LPUART0 base pointer */ 94 #define IP_LPUART0 ((LPUART_Type *)IP_LPUART0_BASE) 95 /** Peripheral LPUART1 base address */ 96 #define IP_LPUART1_BASE (0x4006B000u) 97 /** Peripheral LPUART1 base pointer */ 98 #define IP_LPUART1 ((LPUART_Type *)IP_LPUART1_BASE) 99 /** Peripheral LPUART2 base address */ 100 #define IP_LPUART2_BASE (0x4006C000u) 101 /** Peripheral LPUART2 base pointer */ 102 #define IP_LPUART2 ((LPUART_Type *)IP_LPUART2_BASE) 103 /** Array initializer of LPUART peripheral base addresses */ 104 #define IP_LPUART_BASE_ADDRS { IP_LPUART0_BASE, IP_LPUART1_BASE, IP_LPUART2_BASE } 105 /** Array initializer of LPUART peripheral base pointers */ 106 #define IP_LPUART_BASE_PTRS { IP_LPUART0, IP_LPUART1, IP_LPUART2 } 107 108 /* ---------------------------------------------------------------------------- 109 -- LPUART Register Masks 110 ---------------------------------------------------------------------------- */ 111 112 /*! 113 * @addtogroup LPUART_Register_Masks LPUART Register Masks 114 * @{ 115 */ 116 117 /*! @name VERID - Version ID Register */ 118 /*! @{ */ 119 120 #define LPUART_VERID_FEATURE_MASK (0xFFFFU) 121 #define LPUART_VERID_FEATURE_SHIFT (0U) 122 #define LPUART_VERID_FEATURE_WIDTH (16U) 123 #define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) 124 125 #define LPUART_VERID_MINOR_MASK (0xFF0000U) 126 #define LPUART_VERID_MINOR_SHIFT (16U) 127 #define LPUART_VERID_MINOR_WIDTH (8U) 128 #define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) 129 130 #define LPUART_VERID_MAJOR_MASK (0xFF000000U) 131 #define LPUART_VERID_MAJOR_SHIFT (24U) 132 #define LPUART_VERID_MAJOR_WIDTH (8U) 133 #define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) 134 /*! @} */ 135 136 /*! @name PARAM - Parameter Register */ 137 /*! @{ */ 138 139 #define LPUART_PARAM_TXFIFO_MASK (0xFFU) 140 #define LPUART_PARAM_TXFIFO_SHIFT (0U) 141 #define LPUART_PARAM_TXFIFO_WIDTH (8U) 142 #define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) 143 144 #define LPUART_PARAM_RXFIFO_MASK (0xFF00U) 145 #define LPUART_PARAM_RXFIFO_SHIFT (8U) 146 #define LPUART_PARAM_RXFIFO_WIDTH (8U) 147 #define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) 148 /*! @} */ 149 150 /*! @name GLOBAL - LPUART Global Register */ 151 /*! @{ */ 152 153 #define LPUART_GLOBAL_RST_MASK (0x2U) 154 #define LPUART_GLOBAL_RST_SHIFT (1U) 155 #define LPUART_GLOBAL_RST_WIDTH (1U) 156 #define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) 157 /*! @} */ 158 159 /*! @name PINCFG - LPUART Pin Configuration Register */ 160 /*! @{ */ 161 162 #define LPUART_PINCFG_TRGSEL_MASK (0x3U) 163 #define LPUART_PINCFG_TRGSEL_SHIFT (0U) 164 #define LPUART_PINCFG_TRGSEL_WIDTH (2U) 165 #define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) 166 /*! @} */ 167 168 /*! @name BAUD - LPUART Baud Rate Register */ 169 /*! @{ */ 170 171 #define LPUART_BAUD_SBR_MASK (0x1FFFU) 172 #define LPUART_BAUD_SBR_SHIFT (0U) 173 #define LPUART_BAUD_SBR_WIDTH (13U) 174 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) 175 176 #define LPUART_BAUD_SBNS_MASK (0x2000U) 177 #define LPUART_BAUD_SBNS_SHIFT (13U) 178 #define LPUART_BAUD_SBNS_WIDTH (1U) 179 #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) 180 181 #define LPUART_BAUD_RXEDGIE_MASK (0x4000U) 182 #define LPUART_BAUD_RXEDGIE_SHIFT (14U) 183 #define LPUART_BAUD_RXEDGIE_WIDTH (1U) 184 #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) 185 186 #define LPUART_BAUD_LBKDIE_MASK (0x8000U) 187 #define LPUART_BAUD_LBKDIE_SHIFT (15U) 188 #define LPUART_BAUD_LBKDIE_WIDTH (1U) 189 #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) 190 191 #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) 192 #define LPUART_BAUD_RESYNCDIS_SHIFT (16U) 193 #define LPUART_BAUD_RESYNCDIS_WIDTH (1U) 194 #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) 195 196 #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) 197 #define LPUART_BAUD_BOTHEDGE_SHIFT (17U) 198 #define LPUART_BAUD_BOTHEDGE_WIDTH (1U) 199 #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) 200 201 #define LPUART_BAUD_MATCFG_MASK (0xC0000U) 202 #define LPUART_BAUD_MATCFG_SHIFT (18U) 203 #define LPUART_BAUD_MATCFG_WIDTH (2U) 204 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) 205 206 #define LPUART_BAUD_RIDMAE_MASK (0x100000U) 207 #define LPUART_BAUD_RIDMAE_SHIFT (20U) 208 #define LPUART_BAUD_RIDMAE_WIDTH (1U) 209 #define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) 210 211 #define LPUART_BAUD_RDMAE_MASK (0x200000U) 212 #define LPUART_BAUD_RDMAE_SHIFT (21U) 213 #define LPUART_BAUD_RDMAE_WIDTH (1U) 214 #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) 215 216 #define LPUART_BAUD_TDMAE_MASK (0x800000U) 217 #define LPUART_BAUD_TDMAE_SHIFT (23U) 218 #define LPUART_BAUD_TDMAE_WIDTH (1U) 219 #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) 220 221 #define LPUART_BAUD_OSR_MASK (0x1F000000U) 222 #define LPUART_BAUD_OSR_SHIFT (24U) 223 #define LPUART_BAUD_OSR_WIDTH (5U) 224 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) 225 226 #define LPUART_BAUD_M10_MASK (0x20000000U) 227 #define LPUART_BAUD_M10_SHIFT (29U) 228 #define LPUART_BAUD_M10_WIDTH (1U) 229 #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) 230 231 #define LPUART_BAUD_MAEN2_MASK (0x40000000U) 232 #define LPUART_BAUD_MAEN2_SHIFT (30U) 233 #define LPUART_BAUD_MAEN2_WIDTH (1U) 234 #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) 235 236 #define LPUART_BAUD_MAEN1_MASK (0x80000000U) 237 #define LPUART_BAUD_MAEN1_SHIFT (31U) 238 #define LPUART_BAUD_MAEN1_WIDTH (1U) 239 #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) 240 /*! @} */ 241 242 /*! @name STAT - LPUART Status Register */ 243 /*! @{ */ 244 245 #define LPUART_STAT_MA2F_MASK (0x4000U) 246 #define LPUART_STAT_MA2F_SHIFT (14U) 247 #define LPUART_STAT_MA2F_WIDTH (1U) 248 #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) 249 250 #define LPUART_STAT_MA1F_MASK (0x8000U) 251 #define LPUART_STAT_MA1F_SHIFT (15U) 252 #define LPUART_STAT_MA1F_WIDTH (1U) 253 #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) 254 255 #define LPUART_STAT_PF_MASK (0x10000U) 256 #define LPUART_STAT_PF_SHIFT (16U) 257 #define LPUART_STAT_PF_WIDTH (1U) 258 #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) 259 260 #define LPUART_STAT_FE_MASK (0x20000U) 261 #define LPUART_STAT_FE_SHIFT (17U) 262 #define LPUART_STAT_FE_WIDTH (1U) 263 #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) 264 265 #define LPUART_STAT_NF_MASK (0x40000U) 266 #define LPUART_STAT_NF_SHIFT (18U) 267 #define LPUART_STAT_NF_WIDTH (1U) 268 #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) 269 270 #define LPUART_STAT_OR_MASK (0x80000U) 271 #define LPUART_STAT_OR_SHIFT (19U) 272 #define LPUART_STAT_OR_WIDTH (1U) 273 #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) 274 275 #define LPUART_STAT_IDLE_MASK (0x100000U) 276 #define LPUART_STAT_IDLE_SHIFT (20U) 277 #define LPUART_STAT_IDLE_WIDTH (1U) 278 #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) 279 280 #define LPUART_STAT_RDRF_MASK (0x200000U) 281 #define LPUART_STAT_RDRF_SHIFT (21U) 282 #define LPUART_STAT_RDRF_WIDTH (1U) 283 #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) 284 285 #define LPUART_STAT_TC_MASK (0x400000U) 286 #define LPUART_STAT_TC_SHIFT (22U) 287 #define LPUART_STAT_TC_WIDTH (1U) 288 #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) 289 290 #define LPUART_STAT_TDRE_MASK (0x800000U) 291 #define LPUART_STAT_TDRE_SHIFT (23U) 292 #define LPUART_STAT_TDRE_WIDTH (1U) 293 #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) 294 295 #define LPUART_STAT_RAF_MASK (0x1000000U) 296 #define LPUART_STAT_RAF_SHIFT (24U) 297 #define LPUART_STAT_RAF_WIDTH (1U) 298 #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) 299 300 #define LPUART_STAT_LBKDE_MASK (0x2000000U) 301 #define LPUART_STAT_LBKDE_SHIFT (25U) 302 #define LPUART_STAT_LBKDE_WIDTH (1U) 303 #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) 304 305 #define LPUART_STAT_BRK13_MASK (0x4000000U) 306 #define LPUART_STAT_BRK13_SHIFT (26U) 307 #define LPUART_STAT_BRK13_WIDTH (1U) 308 #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) 309 310 #define LPUART_STAT_RWUID_MASK (0x8000000U) 311 #define LPUART_STAT_RWUID_SHIFT (27U) 312 #define LPUART_STAT_RWUID_WIDTH (1U) 313 #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) 314 315 #define LPUART_STAT_RXINV_MASK (0x10000000U) 316 #define LPUART_STAT_RXINV_SHIFT (28U) 317 #define LPUART_STAT_RXINV_WIDTH (1U) 318 #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) 319 320 #define LPUART_STAT_MSBF_MASK (0x20000000U) 321 #define LPUART_STAT_MSBF_SHIFT (29U) 322 #define LPUART_STAT_MSBF_WIDTH (1U) 323 #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) 324 325 #define LPUART_STAT_RXEDGIF_MASK (0x40000000U) 326 #define LPUART_STAT_RXEDGIF_SHIFT (30U) 327 #define LPUART_STAT_RXEDGIF_WIDTH (1U) 328 #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) 329 330 #define LPUART_STAT_LBKDIF_MASK (0x80000000U) 331 #define LPUART_STAT_LBKDIF_SHIFT (31U) 332 #define LPUART_STAT_LBKDIF_WIDTH (1U) 333 #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) 334 /*! @} */ 335 336 /*! @name CTRL - LPUART Control Register */ 337 /*! @{ */ 338 339 #define LPUART_CTRL_PT_MASK (0x1U) 340 #define LPUART_CTRL_PT_SHIFT (0U) 341 #define LPUART_CTRL_PT_WIDTH (1U) 342 #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) 343 344 #define LPUART_CTRL_PE_MASK (0x2U) 345 #define LPUART_CTRL_PE_SHIFT (1U) 346 #define LPUART_CTRL_PE_WIDTH (1U) 347 #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) 348 349 #define LPUART_CTRL_ILT_MASK (0x4U) 350 #define LPUART_CTRL_ILT_SHIFT (2U) 351 #define LPUART_CTRL_ILT_WIDTH (1U) 352 #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) 353 354 #define LPUART_CTRL_WAKE_MASK (0x8U) 355 #define LPUART_CTRL_WAKE_SHIFT (3U) 356 #define LPUART_CTRL_WAKE_WIDTH (1U) 357 #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) 358 359 #define LPUART_CTRL_M_MASK (0x10U) 360 #define LPUART_CTRL_M_SHIFT (4U) 361 #define LPUART_CTRL_M_WIDTH (1U) 362 #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) 363 364 #define LPUART_CTRL_RSRC_MASK (0x20U) 365 #define LPUART_CTRL_RSRC_SHIFT (5U) 366 #define LPUART_CTRL_RSRC_WIDTH (1U) 367 #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) 368 369 #define LPUART_CTRL_DOZEEN_MASK (0x40U) 370 #define LPUART_CTRL_DOZEEN_SHIFT (6U) 371 #define LPUART_CTRL_DOZEEN_WIDTH (1U) 372 #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) 373 374 #define LPUART_CTRL_LOOPS_MASK (0x80U) 375 #define LPUART_CTRL_LOOPS_SHIFT (7U) 376 #define LPUART_CTRL_LOOPS_WIDTH (1U) 377 #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) 378 379 #define LPUART_CTRL_IDLECFG_MASK (0x700U) 380 #define LPUART_CTRL_IDLECFG_SHIFT (8U) 381 #define LPUART_CTRL_IDLECFG_WIDTH (3U) 382 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) 383 384 #define LPUART_CTRL_M7_MASK (0x800U) 385 #define LPUART_CTRL_M7_SHIFT (11U) 386 #define LPUART_CTRL_M7_WIDTH (1U) 387 #define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) 388 389 #define LPUART_CTRL_MA2IE_MASK (0x4000U) 390 #define LPUART_CTRL_MA2IE_SHIFT (14U) 391 #define LPUART_CTRL_MA2IE_WIDTH (1U) 392 #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) 393 394 #define LPUART_CTRL_MA1IE_MASK (0x8000U) 395 #define LPUART_CTRL_MA1IE_SHIFT (15U) 396 #define LPUART_CTRL_MA1IE_WIDTH (1U) 397 #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) 398 399 #define LPUART_CTRL_SBK_MASK (0x10000U) 400 #define LPUART_CTRL_SBK_SHIFT (16U) 401 #define LPUART_CTRL_SBK_WIDTH (1U) 402 #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) 403 404 #define LPUART_CTRL_RWU_MASK (0x20000U) 405 #define LPUART_CTRL_RWU_SHIFT (17U) 406 #define LPUART_CTRL_RWU_WIDTH (1U) 407 #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) 408 409 #define LPUART_CTRL_RE_MASK (0x40000U) 410 #define LPUART_CTRL_RE_SHIFT (18U) 411 #define LPUART_CTRL_RE_WIDTH (1U) 412 #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) 413 414 #define LPUART_CTRL_TE_MASK (0x80000U) 415 #define LPUART_CTRL_TE_SHIFT (19U) 416 #define LPUART_CTRL_TE_WIDTH (1U) 417 #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) 418 419 #define LPUART_CTRL_ILIE_MASK (0x100000U) 420 #define LPUART_CTRL_ILIE_SHIFT (20U) 421 #define LPUART_CTRL_ILIE_WIDTH (1U) 422 #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) 423 424 #define LPUART_CTRL_RIE_MASK (0x200000U) 425 #define LPUART_CTRL_RIE_SHIFT (21U) 426 #define LPUART_CTRL_RIE_WIDTH (1U) 427 #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) 428 429 #define LPUART_CTRL_TCIE_MASK (0x400000U) 430 #define LPUART_CTRL_TCIE_SHIFT (22U) 431 #define LPUART_CTRL_TCIE_WIDTH (1U) 432 #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) 433 434 #define LPUART_CTRL_TIE_MASK (0x800000U) 435 #define LPUART_CTRL_TIE_SHIFT (23U) 436 #define LPUART_CTRL_TIE_WIDTH (1U) 437 #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) 438 439 #define LPUART_CTRL_PEIE_MASK (0x1000000U) 440 #define LPUART_CTRL_PEIE_SHIFT (24U) 441 #define LPUART_CTRL_PEIE_WIDTH (1U) 442 #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) 443 444 #define LPUART_CTRL_FEIE_MASK (0x2000000U) 445 #define LPUART_CTRL_FEIE_SHIFT (25U) 446 #define LPUART_CTRL_FEIE_WIDTH (1U) 447 #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) 448 449 #define LPUART_CTRL_NEIE_MASK (0x4000000U) 450 #define LPUART_CTRL_NEIE_SHIFT (26U) 451 #define LPUART_CTRL_NEIE_WIDTH (1U) 452 #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) 453 454 #define LPUART_CTRL_ORIE_MASK (0x8000000U) 455 #define LPUART_CTRL_ORIE_SHIFT (27U) 456 #define LPUART_CTRL_ORIE_WIDTH (1U) 457 #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) 458 459 #define LPUART_CTRL_TXINV_MASK (0x10000000U) 460 #define LPUART_CTRL_TXINV_SHIFT (28U) 461 #define LPUART_CTRL_TXINV_WIDTH (1U) 462 #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) 463 464 #define LPUART_CTRL_TXDIR_MASK (0x20000000U) 465 #define LPUART_CTRL_TXDIR_SHIFT (29U) 466 #define LPUART_CTRL_TXDIR_WIDTH (1U) 467 #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) 468 469 #define LPUART_CTRL_R9T8_MASK (0x40000000U) 470 #define LPUART_CTRL_R9T8_SHIFT (30U) 471 #define LPUART_CTRL_R9T8_WIDTH (1U) 472 #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) 473 474 #define LPUART_CTRL_R8T9_MASK (0x80000000U) 475 #define LPUART_CTRL_R8T9_SHIFT (31U) 476 #define LPUART_CTRL_R8T9_WIDTH (1U) 477 #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) 478 /*! @} */ 479 480 /*! @name DATA - LPUART Data Register */ 481 /*! @{ */ 482 483 #define LPUART_DATA_R0T0_MASK (0x1U) 484 #define LPUART_DATA_R0T0_SHIFT (0U) 485 #define LPUART_DATA_R0T0_WIDTH (1U) 486 #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) 487 488 #define LPUART_DATA_R1T1_MASK (0x2U) 489 #define LPUART_DATA_R1T1_SHIFT (1U) 490 #define LPUART_DATA_R1T1_WIDTH (1U) 491 #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) 492 493 #define LPUART_DATA_R2T2_MASK (0x4U) 494 #define LPUART_DATA_R2T2_SHIFT (2U) 495 #define LPUART_DATA_R2T2_WIDTH (1U) 496 #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) 497 498 #define LPUART_DATA_R3T3_MASK (0x8U) 499 #define LPUART_DATA_R3T3_SHIFT (3U) 500 #define LPUART_DATA_R3T3_WIDTH (1U) 501 #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) 502 503 #define LPUART_DATA_R4T4_MASK (0x10U) 504 #define LPUART_DATA_R4T4_SHIFT (4U) 505 #define LPUART_DATA_R4T4_WIDTH (1U) 506 #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) 507 508 #define LPUART_DATA_R5T5_MASK (0x20U) 509 #define LPUART_DATA_R5T5_SHIFT (5U) 510 #define LPUART_DATA_R5T5_WIDTH (1U) 511 #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) 512 513 #define LPUART_DATA_R6T6_MASK (0x40U) 514 #define LPUART_DATA_R6T6_SHIFT (6U) 515 #define LPUART_DATA_R6T6_WIDTH (1U) 516 #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) 517 518 #define LPUART_DATA_R7T7_MASK (0x80U) 519 #define LPUART_DATA_R7T7_SHIFT (7U) 520 #define LPUART_DATA_R7T7_WIDTH (1U) 521 #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) 522 523 #define LPUART_DATA_R8T8_MASK (0x100U) 524 #define LPUART_DATA_R8T8_SHIFT (8U) 525 #define LPUART_DATA_R8T8_WIDTH (1U) 526 #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) 527 528 #define LPUART_DATA_R9T9_MASK (0x200U) 529 #define LPUART_DATA_R9T9_SHIFT (9U) 530 #define LPUART_DATA_R9T9_WIDTH (1U) 531 #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) 532 533 #define LPUART_DATA_IDLINE_MASK (0x800U) 534 #define LPUART_DATA_IDLINE_SHIFT (11U) 535 #define LPUART_DATA_IDLINE_WIDTH (1U) 536 #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) 537 538 #define LPUART_DATA_RXEMPT_MASK (0x1000U) 539 #define LPUART_DATA_RXEMPT_SHIFT (12U) 540 #define LPUART_DATA_RXEMPT_WIDTH (1U) 541 #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) 542 543 #define LPUART_DATA_FRETSC_MASK (0x2000U) 544 #define LPUART_DATA_FRETSC_SHIFT (13U) 545 #define LPUART_DATA_FRETSC_WIDTH (1U) 546 #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) 547 548 #define LPUART_DATA_PARITYE_MASK (0x4000U) 549 #define LPUART_DATA_PARITYE_SHIFT (14U) 550 #define LPUART_DATA_PARITYE_WIDTH (1U) 551 #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) 552 553 #define LPUART_DATA_NOISY_MASK (0x8000U) 554 #define LPUART_DATA_NOISY_SHIFT (15U) 555 #define LPUART_DATA_NOISY_WIDTH (1U) 556 #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) 557 /*! @} */ 558 559 /*! @name MATCH - LPUART Match Address Register */ 560 /*! @{ */ 561 562 #define LPUART_MATCH_MA1_MASK (0x3FFU) 563 #define LPUART_MATCH_MA1_SHIFT (0U) 564 #define LPUART_MATCH_MA1_WIDTH (10U) 565 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) 566 567 #define LPUART_MATCH_MA2_MASK (0x3FF0000U) 568 #define LPUART_MATCH_MA2_SHIFT (16U) 569 #define LPUART_MATCH_MA2_WIDTH (10U) 570 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) 571 /*! @} */ 572 573 /*! @name MODIR - LPUART Modem IrDA Register */ 574 /*! @{ */ 575 576 #define LPUART_MODIR_TXCTSE_MASK (0x1U) 577 #define LPUART_MODIR_TXCTSE_SHIFT (0U) 578 #define LPUART_MODIR_TXCTSE_WIDTH (1U) 579 #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) 580 581 #define LPUART_MODIR_TXRTSE_MASK (0x2U) 582 #define LPUART_MODIR_TXRTSE_SHIFT (1U) 583 #define LPUART_MODIR_TXRTSE_WIDTH (1U) 584 #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) 585 586 #define LPUART_MODIR_TXRTSPOL_MASK (0x4U) 587 #define LPUART_MODIR_TXRTSPOL_SHIFT (2U) 588 #define LPUART_MODIR_TXRTSPOL_WIDTH (1U) 589 #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) 590 591 #define LPUART_MODIR_RXRTSE_MASK (0x8U) 592 #define LPUART_MODIR_RXRTSE_SHIFT (3U) 593 #define LPUART_MODIR_RXRTSE_WIDTH (1U) 594 #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) 595 596 #define LPUART_MODIR_TXCTSC_MASK (0x10U) 597 #define LPUART_MODIR_TXCTSC_SHIFT (4U) 598 #define LPUART_MODIR_TXCTSC_WIDTH (1U) 599 #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) 600 601 #define LPUART_MODIR_TXCTSSRC_MASK (0x20U) 602 #define LPUART_MODIR_TXCTSSRC_SHIFT (5U) 603 #define LPUART_MODIR_TXCTSSRC_WIDTH (1U) 604 #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) 605 606 #define LPUART_MODIR_RTSWATER_MASK (0x300U) 607 #define LPUART_MODIR_RTSWATER_SHIFT (8U) 608 #define LPUART_MODIR_RTSWATER_WIDTH (2U) 609 #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) 610 611 #define LPUART_MODIR_TNP_MASK (0x30000U) 612 #define LPUART_MODIR_TNP_SHIFT (16U) 613 #define LPUART_MODIR_TNP_WIDTH (2U) 614 #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) 615 616 #define LPUART_MODIR_IREN_MASK (0x40000U) 617 #define LPUART_MODIR_IREN_SHIFT (18U) 618 #define LPUART_MODIR_IREN_WIDTH (1U) 619 #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) 620 /*! @} */ 621 622 /*! @name FIFO - LPUART FIFO Register */ 623 /*! @{ */ 624 625 #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) 626 #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) 627 #define LPUART_FIFO_RXFIFOSIZE_WIDTH (3U) 628 #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) 629 630 #define LPUART_FIFO_RXFE_MASK (0x8U) 631 #define LPUART_FIFO_RXFE_SHIFT (3U) 632 #define LPUART_FIFO_RXFE_WIDTH (1U) 633 #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) 634 635 #define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) 636 #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) 637 #define LPUART_FIFO_TXFIFOSIZE_WIDTH (3U) 638 #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) 639 640 #define LPUART_FIFO_TXFE_MASK (0x80U) 641 #define LPUART_FIFO_TXFE_SHIFT (7U) 642 #define LPUART_FIFO_TXFE_WIDTH (1U) 643 #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) 644 645 #define LPUART_FIFO_RXUFE_MASK (0x100U) 646 #define LPUART_FIFO_RXUFE_SHIFT (8U) 647 #define LPUART_FIFO_RXUFE_WIDTH (1U) 648 #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) 649 650 #define LPUART_FIFO_TXOFE_MASK (0x200U) 651 #define LPUART_FIFO_TXOFE_SHIFT (9U) 652 #define LPUART_FIFO_TXOFE_WIDTH (1U) 653 #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) 654 655 #define LPUART_FIFO_RXIDEN_MASK (0x1C00U) 656 #define LPUART_FIFO_RXIDEN_SHIFT (10U) 657 #define LPUART_FIFO_RXIDEN_WIDTH (3U) 658 #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) 659 660 #define LPUART_FIFO_RXFLUSH_MASK (0x4000U) 661 #define LPUART_FIFO_RXFLUSH_SHIFT (14U) 662 #define LPUART_FIFO_RXFLUSH_WIDTH (1U) 663 #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) 664 665 #define LPUART_FIFO_TXFLUSH_MASK (0x8000U) 666 #define LPUART_FIFO_TXFLUSH_SHIFT (15U) 667 #define LPUART_FIFO_TXFLUSH_WIDTH (1U) 668 #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) 669 670 #define LPUART_FIFO_RXUF_MASK (0x10000U) 671 #define LPUART_FIFO_RXUF_SHIFT (16U) 672 #define LPUART_FIFO_RXUF_WIDTH (1U) 673 #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) 674 675 #define LPUART_FIFO_TXOF_MASK (0x20000U) 676 #define LPUART_FIFO_TXOF_SHIFT (17U) 677 #define LPUART_FIFO_TXOF_WIDTH (1U) 678 #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) 679 680 #define LPUART_FIFO_RXEMPT_MASK (0x400000U) 681 #define LPUART_FIFO_RXEMPT_SHIFT (22U) 682 #define LPUART_FIFO_RXEMPT_WIDTH (1U) 683 #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) 684 685 #define LPUART_FIFO_TXEMPT_MASK (0x800000U) 686 #define LPUART_FIFO_TXEMPT_SHIFT (23U) 687 #define LPUART_FIFO_TXEMPT_WIDTH (1U) 688 #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) 689 /*! @} */ 690 691 /*! @name WATER - LPUART Watermark Register */ 692 /*! @{ */ 693 694 #define LPUART_WATER_TXWATER_MASK (0x3U) 695 #define LPUART_WATER_TXWATER_SHIFT (0U) 696 #define LPUART_WATER_TXWATER_WIDTH (2U) 697 #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) 698 699 #define LPUART_WATER_TXCOUNT_MASK (0x700U) 700 #define LPUART_WATER_TXCOUNT_SHIFT (8U) 701 #define LPUART_WATER_TXCOUNT_WIDTH (3U) 702 #define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) 703 704 #define LPUART_WATER_RXWATER_MASK (0x30000U) 705 #define LPUART_WATER_RXWATER_SHIFT (16U) 706 #define LPUART_WATER_RXWATER_WIDTH (2U) 707 #define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) 708 709 #define LPUART_WATER_RXCOUNT_MASK (0x7000000U) 710 #define LPUART_WATER_RXCOUNT_SHIFT (24U) 711 #define LPUART_WATER_RXCOUNT_WIDTH (3U) 712 #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) 713 /*! @} */ 714 715 /*! 716 * @} 717 */ /* end of group LPUART_Register_Masks */ 718 719 /*! 720 * @} 721 */ /* end of group LPUART_Peripheral_Access_Layer */ 722 723 #endif /* #if !defined(S32K146_LPUART_H_) */ 724
