1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K146_LPSPI.h 10 * @version 1.1 11 * @date 2022-01-31 12 * @brief Peripheral Access Layer for S32K146_LPSPI 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K146_LPSPI_H_) /* Check if memory map has not been already included */ 58 #define S32K146_LPSPI_H_ 59 60 #include "S32K146_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- LPSPI Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer 68 * @{ 69 */ 70 71 /** LPSPI - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ 74 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ 75 uint8_t RESERVED_0[8]; 76 __IO uint32_t CR; /**< Control Register, offset: 0x10 */ 77 __IO uint32_t SR; /**< Status Register, offset: 0x14 */ 78 __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x18 */ 79 __IO uint32_t DER; /**< DMA Enable Register, offset: 0x1C */ 80 __IO uint32_t CFGR0; /**< Configuration Register 0, offset: 0x20 */ 81 __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ 82 uint8_t RESERVED_1[8]; 83 __IO uint32_t DMR0; /**< Data Match Register 0, offset: 0x30 */ 84 __IO uint32_t DMR1; /**< Data Match Register 1, offset: 0x34 */ 85 uint8_t RESERVED_2[8]; 86 __IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ 87 uint8_t RESERVED_3[20]; 88 __IO uint32_t FCR; /**< The FIFO Control register contains the RXWATER and TXWATER control fields., offset: 0x58 */ 89 __I uint32_t FSR; /**< FIFO Status Register, offset: 0x5C */ 90 __IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */ 91 __O uint32_t TDR; /**< Transmit Data Register, offset: 0x64 */ 92 uint8_t RESERVED_4[8]; 93 __I uint32_t RSR; /**< Receive Status Register, offset: 0x70 */ 94 __I uint32_t RDR; /**< Receive Data Register, offset: 0x74 */ 95 } LPSPI_Type, *LPSPI_MemMapPtr; 96 97 /** Number of instances of the LPSPI module. */ 98 #define LPSPI_INSTANCE_COUNT (3u) 99 100 /* LPSPI - Peripheral instance base addresses */ 101 /** Peripheral LPSPI0 base address */ 102 #define IP_LPSPI0_BASE (0x4002C000u) 103 /** Peripheral LPSPI0 base pointer */ 104 #define IP_LPSPI0 ((LPSPI_Type *)IP_LPSPI0_BASE) 105 /** Peripheral LPSPI1 base address */ 106 #define IP_LPSPI1_BASE (0x4002D000u) 107 /** Peripheral LPSPI1 base pointer */ 108 #define IP_LPSPI1 ((LPSPI_Type *)IP_LPSPI1_BASE) 109 /** Peripheral LPSPI2 base address */ 110 #define IP_LPSPI2_BASE (0x4002E000u) 111 /** Peripheral LPSPI2 base pointer */ 112 #define IP_LPSPI2 ((LPSPI_Type *)IP_LPSPI2_BASE) 113 /** Array initializer of LPSPI peripheral base addresses */ 114 #define IP_LPSPI_BASE_ADDRS { IP_LPSPI0_BASE, IP_LPSPI1_BASE, IP_LPSPI2_BASE } 115 /** Array initializer of LPSPI peripheral base pointers */ 116 #define IP_LPSPI_BASE_PTRS { IP_LPSPI0, IP_LPSPI1, IP_LPSPI2 } 117 118 /* ---------------------------------------------------------------------------- 119 -- LPSPI Register Masks 120 ---------------------------------------------------------------------------- */ 121 122 /*! 123 * @addtogroup LPSPI_Register_Masks LPSPI Register Masks 124 * @{ 125 */ 126 127 /*! @name VERID - Version ID Register */ 128 /*! @{ */ 129 130 #define LPSPI_VERID_FEATURE_MASK (0xFFFFU) 131 #define LPSPI_VERID_FEATURE_SHIFT (0U) 132 #define LPSPI_VERID_FEATURE_WIDTH (16U) 133 #define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) 134 135 #define LPSPI_VERID_MINOR_MASK (0xFF0000U) 136 #define LPSPI_VERID_MINOR_SHIFT (16U) 137 #define LPSPI_VERID_MINOR_WIDTH (8U) 138 #define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) 139 140 #define LPSPI_VERID_MAJOR_MASK (0xFF000000U) 141 #define LPSPI_VERID_MAJOR_SHIFT (24U) 142 #define LPSPI_VERID_MAJOR_WIDTH (8U) 143 #define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) 144 /*! @} */ 145 146 /*! @name PARAM - Parameter Register */ 147 /*! @{ */ 148 149 #define LPSPI_PARAM_TXFIFO_MASK (0xFFU) 150 #define LPSPI_PARAM_TXFIFO_SHIFT (0U) 151 #define LPSPI_PARAM_TXFIFO_WIDTH (8U) 152 #define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) 153 154 #define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) 155 #define LPSPI_PARAM_RXFIFO_SHIFT (8U) 156 #define LPSPI_PARAM_RXFIFO_WIDTH (8U) 157 #define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) 158 /*! @} */ 159 160 /*! @name CR - Control Register */ 161 /*! @{ */ 162 163 #define LPSPI_CR_MEN_MASK (0x1U) 164 #define LPSPI_CR_MEN_SHIFT (0U) 165 #define LPSPI_CR_MEN_WIDTH (1U) 166 #define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) 167 168 #define LPSPI_CR_RST_MASK (0x2U) 169 #define LPSPI_CR_RST_SHIFT (1U) 170 #define LPSPI_CR_RST_WIDTH (1U) 171 #define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) 172 173 #define LPSPI_CR_DOZEN_MASK (0x4U) 174 #define LPSPI_CR_DOZEN_SHIFT (2U) 175 #define LPSPI_CR_DOZEN_WIDTH (1U) 176 #define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK) 177 178 #define LPSPI_CR_DBGEN_MASK (0x8U) 179 #define LPSPI_CR_DBGEN_SHIFT (3U) 180 #define LPSPI_CR_DBGEN_WIDTH (1U) 181 #define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) 182 183 #define LPSPI_CR_RTF_MASK (0x100U) 184 #define LPSPI_CR_RTF_SHIFT (8U) 185 #define LPSPI_CR_RTF_WIDTH (1U) 186 #define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) 187 188 #define LPSPI_CR_RRF_MASK (0x200U) 189 #define LPSPI_CR_RRF_SHIFT (9U) 190 #define LPSPI_CR_RRF_WIDTH (1U) 191 #define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) 192 /*! @} */ 193 194 /*! @name SR - Status Register */ 195 /*! @{ */ 196 197 #define LPSPI_SR_TDF_MASK (0x1U) 198 #define LPSPI_SR_TDF_SHIFT (0U) 199 #define LPSPI_SR_TDF_WIDTH (1U) 200 #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) 201 202 #define LPSPI_SR_RDF_MASK (0x2U) 203 #define LPSPI_SR_RDF_SHIFT (1U) 204 #define LPSPI_SR_RDF_WIDTH (1U) 205 #define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) 206 207 #define LPSPI_SR_WCF_MASK (0x100U) 208 #define LPSPI_SR_WCF_SHIFT (8U) 209 #define LPSPI_SR_WCF_WIDTH (1U) 210 #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) 211 212 #define LPSPI_SR_FCF_MASK (0x200U) 213 #define LPSPI_SR_FCF_SHIFT (9U) 214 #define LPSPI_SR_FCF_WIDTH (1U) 215 #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) 216 217 #define LPSPI_SR_TCF_MASK (0x400U) 218 #define LPSPI_SR_TCF_SHIFT (10U) 219 #define LPSPI_SR_TCF_WIDTH (1U) 220 #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) 221 222 #define LPSPI_SR_TEF_MASK (0x800U) 223 #define LPSPI_SR_TEF_SHIFT (11U) 224 #define LPSPI_SR_TEF_WIDTH (1U) 225 #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) 226 227 #define LPSPI_SR_REF_MASK (0x1000U) 228 #define LPSPI_SR_REF_SHIFT (12U) 229 #define LPSPI_SR_REF_WIDTH (1U) 230 #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) 231 232 #define LPSPI_SR_DMF_MASK (0x2000U) 233 #define LPSPI_SR_DMF_SHIFT (13U) 234 #define LPSPI_SR_DMF_WIDTH (1U) 235 #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) 236 237 #define LPSPI_SR_MBF_MASK (0x1000000U) 238 #define LPSPI_SR_MBF_SHIFT (24U) 239 #define LPSPI_SR_MBF_WIDTH (1U) 240 #define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) 241 /*! @} */ 242 243 /*! @name IER - Interrupt Enable Register */ 244 /*! @{ */ 245 246 #define LPSPI_IER_TDIE_MASK (0x1U) 247 #define LPSPI_IER_TDIE_SHIFT (0U) 248 #define LPSPI_IER_TDIE_WIDTH (1U) 249 #define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) 250 251 #define LPSPI_IER_RDIE_MASK (0x2U) 252 #define LPSPI_IER_RDIE_SHIFT (1U) 253 #define LPSPI_IER_RDIE_WIDTH (1U) 254 #define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) 255 256 #define LPSPI_IER_WCIE_MASK (0x100U) 257 #define LPSPI_IER_WCIE_SHIFT (8U) 258 #define LPSPI_IER_WCIE_WIDTH (1U) 259 #define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) 260 261 #define LPSPI_IER_FCIE_MASK (0x200U) 262 #define LPSPI_IER_FCIE_SHIFT (9U) 263 #define LPSPI_IER_FCIE_WIDTH (1U) 264 #define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) 265 266 #define LPSPI_IER_TCIE_MASK (0x400U) 267 #define LPSPI_IER_TCIE_SHIFT (10U) 268 #define LPSPI_IER_TCIE_WIDTH (1U) 269 #define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) 270 271 #define LPSPI_IER_TEIE_MASK (0x800U) 272 #define LPSPI_IER_TEIE_SHIFT (11U) 273 #define LPSPI_IER_TEIE_WIDTH (1U) 274 #define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) 275 276 #define LPSPI_IER_REIE_MASK (0x1000U) 277 #define LPSPI_IER_REIE_SHIFT (12U) 278 #define LPSPI_IER_REIE_WIDTH (1U) 279 #define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) 280 281 #define LPSPI_IER_DMIE_MASK (0x2000U) 282 #define LPSPI_IER_DMIE_SHIFT (13U) 283 #define LPSPI_IER_DMIE_WIDTH (1U) 284 #define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) 285 /*! @} */ 286 287 /*! @name DER - DMA Enable Register */ 288 /*! @{ */ 289 290 #define LPSPI_DER_TDDE_MASK (0x1U) 291 #define LPSPI_DER_TDDE_SHIFT (0U) 292 #define LPSPI_DER_TDDE_WIDTH (1U) 293 #define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) 294 295 #define LPSPI_DER_RDDE_MASK (0x2U) 296 #define LPSPI_DER_RDDE_SHIFT (1U) 297 #define LPSPI_DER_RDDE_WIDTH (1U) 298 #define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) 299 /*! @} */ 300 301 /*! @name CFGR0 - Configuration Register 0 */ 302 /*! @{ */ 303 304 #define LPSPI_CFGR0_HREN_MASK (0x1U) 305 #define LPSPI_CFGR0_HREN_SHIFT (0U) 306 #define LPSPI_CFGR0_HREN_WIDTH (1U) 307 #define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) 308 309 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) 310 #define LPSPI_CFGR0_HRPOL_SHIFT (1U) 311 #define LPSPI_CFGR0_HRPOL_WIDTH (1U) 312 #define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) 313 314 #define LPSPI_CFGR0_HRSEL_MASK (0x4U) 315 #define LPSPI_CFGR0_HRSEL_SHIFT (2U) 316 #define LPSPI_CFGR0_HRSEL_WIDTH (1U) 317 #define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) 318 319 #define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) 320 #define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) 321 #define LPSPI_CFGR0_CIRFIFO_WIDTH (1U) 322 #define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) 323 324 #define LPSPI_CFGR0_RDMO_MASK (0x200U) 325 #define LPSPI_CFGR0_RDMO_SHIFT (9U) 326 #define LPSPI_CFGR0_RDMO_WIDTH (1U) 327 #define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) 328 /*! @} */ 329 330 /*! @name CFGR1 - Configuration Register 1 */ 331 /*! @{ */ 332 333 #define LPSPI_CFGR1_MASTER_MASK (0x1U) 334 #define LPSPI_CFGR1_MASTER_SHIFT (0U) 335 #define LPSPI_CFGR1_MASTER_WIDTH (1U) 336 #define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) 337 338 #define LPSPI_CFGR1_SAMPLE_MASK (0x2U) 339 #define LPSPI_CFGR1_SAMPLE_SHIFT (1U) 340 #define LPSPI_CFGR1_SAMPLE_WIDTH (1U) 341 #define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) 342 343 #define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) 344 #define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) 345 #define LPSPI_CFGR1_AUTOPCS_WIDTH (1U) 346 #define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) 347 348 #define LPSPI_CFGR1_NOSTALL_MASK (0x8U) 349 #define LPSPI_CFGR1_NOSTALL_SHIFT (3U) 350 #define LPSPI_CFGR1_NOSTALL_WIDTH (1U) 351 #define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) 352 353 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) 354 #define LPSPI_CFGR1_PCSPOL_SHIFT (8U) 355 #define LPSPI_CFGR1_PCSPOL_WIDTH (4U) 356 #define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) 357 358 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) 359 #define LPSPI_CFGR1_MATCFG_SHIFT (16U) 360 #define LPSPI_CFGR1_MATCFG_WIDTH (3U) 361 #define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) 362 363 #define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) 364 #define LPSPI_CFGR1_PINCFG_SHIFT (24U) 365 #define LPSPI_CFGR1_PINCFG_WIDTH (2U) 366 #define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) 367 368 #define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) 369 #define LPSPI_CFGR1_OUTCFG_SHIFT (26U) 370 #define LPSPI_CFGR1_OUTCFG_WIDTH (1U) 371 #define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) 372 373 #define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) 374 #define LPSPI_CFGR1_PCSCFG_SHIFT (27U) 375 #define LPSPI_CFGR1_PCSCFG_WIDTH (1U) 376 #define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) 377 /*! @} */ 378 379 /*! @name DMR0 - Data Match Register 0 */ 380 /*! @{ */ 381 382 #define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) 383 #define LPSPI_DMR0_MATCH0_SHIFT (0U) 384 #define LPSPI_DMR0_MATCH0_WIDTH (32U) 385 #define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) 386 /*! @} */ 387 388 /*! @name DMR1 - Data Match Register 1 */ 389 /*! @{ */ 390 391 #define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) 392 #define LPSPI_DMR1_MATCH1_SHIFT (0U) 393 #define LPSPI_DMR1_MATCH1_WIDTH (32U) 394 #define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) 395 /*! @} */ 396 397 /*! @name CCR - Clock Configuration Register */ 398 /*! @{ */ 399 400 #define LPSPI_CCR_SCKDIV_MASK (0xFFU) 401 #define LPSPI_CCR_SCKDIV_SHIFT (0U) 402 #define LPSPI_CCR_SCKDIV_WIDTH (8U) 403 #define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) 404 405 #define LPSPI_CCR_DBT_MASK (0xFF00U) 406 #define LPSPI_CCR_DBT_SHIFT (8U) 407 #define LPSPI_CCR_DBT_WIDTH (8U) 408 #define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) 409 410 #define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) 411 #define LPSPI_CCR_PCSSCK_SHIFT (16U) 412 #define LPSPI_CCR_PCSSCK_WIDTH (8U) 413 #define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) 414 415 #define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) 416 #define LPSPI_CCR_SCKPCS_SHIFT (24U) 417 #define LPSPI_CCR_SCKPCS_WIDTH (8U) 418 #define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) 419 /*! @} */ 420 421 /*! @name FCR - The FIFO Control register contains the RXWATER and TXWATER control fields. */ 422 /*! @{ */ 423 424 #define LPSPI_FCR_TXWATER_MASK (0x3U) 425 #define LPSPI_FCR_TXWATER_SHIFT (0U) 426 #define LPSPI_FCR_TXWATER_WIDTH (2U) 427 #define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) 428 429 #define LPSPI_FCR_RXWATER_MASK (0x30000U) 430 #define LPSPI_FCR_RXWATER_SHIFT (16U) 431 #define LPSPI_FCR_RXWATER_WIDTH (2U) 432 #define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) 433 /*! @} */ 434 435 /*! @name FSR - FIFO Status Register */ 436 /*! @{ */ 437 438 #define LPSPI_FSR_TXCOUNT_MASK (0x7U) 439 #define LPSPI_FSR_TXCOUNT_SHIFT (0U) 440 #define LPSPI_FSR_TXCOUNT_WIDTH (3U) 441 #define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) 442 443 #define LPSPI_FSR_RXCOUNT_MASK (0x70000U) 444 #define LPSPI_FSR_RXCOUNT_SHIFT (16U) 445 #define LPSPI_FSR_RXCOUNT_WIDTH (3U) 446 #define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) 447 /*! @} */ 448 449 /*! @name TCR - Transmit Command Register */ 450 /*! @{ */ 451 452 #define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) 453 #define LPSPI_TCR_FRAMESZ_SHIFT (0U) 454 #define LPSPI_TCR_FRAMESZ_WIDTH (12U) 455 #define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) 456 457 #define LPSPI_TCR_WIDTH_MASK (0x30000U) 458 #define LPSPI_TCR_WIDTH_SHIFT (16U) 459 #define LPSPI_TCR_WIDTH_WIDTH (2U) 460 #define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) 461 462 #define LPSPI_TCR_TXMSK_MASK (0x40000U) 463 #define LPSPI_TCR_TXMSK_SHIFT (18U) 464 #define LPSPI_TCR_TXMSK_WIDTH (1U) 465 #define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) 466 467 #define LPSPI_TCR_RXMSK_MASK (0x80000U) 468 #define LPSPI_TCR_RXMSK_SHIFT (19U) 469 #define LPSPI_TCR_RXMSK_WIDTH (1U) 470 #define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) 471 472 #define LPSPI_TCR_CONTC_MASK (0x100000U) 473 #define LPSPI_TCR_CONTC_SHIFT (20U) 474 #define LPSPI_TCR_CONTC_WIDTH (1U) 475 #define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) 476 477 #define LPSPI_TCR_CONT_MASK (0x200000U) 478 #define LPSPI_TCR_CONT_SHIFT (21U) 479 #define LPSPI_TCR_CONT_WIDTH (1U) 480 #define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) 481 482 #define LPSPI_TCR_BYSW_MASK (0x400000U) 483 #define LPSPI_TCR_BYSW_SHIFT (22U) 484 #define LPSPI_TCR_BYSW_WIDTH (1U) 485 #define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) 486 487 #define LPSPI_TCR_LSBF_MASK (0x800000U) 488 #define LPSPI_TCR_LSBF_SHIFT (23U) 489 #define LPSPI_TCR_LSBF_WIDTH (1U) 490 #define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) 491 492 #define LPSPI_TCR_PCS_MASK (0x3000000U) 493 #define LPSPI_TCR_PCS_SHIFT (24U) 494 #define LPSPI_TCR_PCS_WIDTH (2U) 495 #define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) 496 497 #define LPSPI_TCR_PRESCALE_MASK (0x38000000U) 498 #define LPSPI_TCR_PRESCALE_SHIFT (27U) 499 #define LPSPI_TCR_PRESCALE_WIDTH (3U) 500 #define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) 501 502 #define LPSPI_TCR_CPHA_MASK (0x40000000U) 503 #define LPSPI_TCR_CPHA_SHIFT (30U) 504 #define LPSPI_TCR_CPHA_WIDTH (1U) 505 #define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) 506 507 #define LPSPI_TCR_CPOL_MASK (0x80000000U) 508 #define LPSPI_TCR_CPOL_SHIFT (31U) 509 #define LPSPI_TCR_CPOL_WIDTH (1U) 510 #define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) 511 /*! @} */ 512 513 /*! @name TDR - Transmit Data Register */ 514 /*! @{ */ 515 516 #define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) 517 #define LPSPI_TDR_DATA_SHIFT (0U) 518 #define LPSPI_TDR_DATA_WIDTH (32U) 519 #define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) 520 /*! @} */ 521 522 /*! @name RSR - Receive Status Register */ 523 /*! @{ */ 524 525 #define LPSPI_RSR_SOF_MASK (0x1U) 526 #define LPSPI_RSR_SOF_SHIFT (0U) 527 #define LPSPI_RSR_SOF_WIDTH (1U) 528 #define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) 529 530 #define LPSPI_RSR_RXEMPTY_MASK (0x2U) 531 #define LPSPI_RSR_RXEMPTY_SHIFT (1U) 532 #define LPSPI_RSR_RXEMPTY_WIDTH (1U) 533 #define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) 534 /*! @} */ 535 536 /*! @name RDR - Receive Data Register */ 537 /*! @{ */ 538 539 #define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) 540 #define LPSPI_RDR_DATA_SHIFT (0U) 541 #define LPSPI_RDR_DATA_WIDTH (32U) 542 #define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) 543 /*! @} */ 544 545 /*! 546 * @} 547 */ /* end of group LPSPI_Register_Masks */ 548 549 /*! 550 * @} 551 */ /* end of group LPSPI_Peripheral_Access_Layer */ 552 553 #endif /* #if !defined(S32K146_LPSPI_H_) */ 554
