1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K146_ADC.h 10 * @version 1.1 11 * @date 2022-01-31 12 * @brief Peripheral Access Layer for S32K146_ADC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K146_ADC_H_) /* Check if memory map has not been already included */ 58 #define S32K146_ADC_H_ 59 60 #include "S32K146_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- ADC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** ADC - Size of Registers Arrays */ 72 #define ADC_SC1_COUNT 24u 73 #define ADC_R_COUNT 24u 74 75 /** ADC - Register Layout Typedef */ 76 typedef struct { 77 __IO uint32_t SC1A; /**< ADC Status and Control Register 1, offset: 0x0 */ 78 __IO uint32_t SC1B; /**< ADC Status and Control Register 1, offset: 0x4 */ 79 __IO uint32_t SC1C; /**< ADC Status and Control Register 1, offset: 0x8 */ 80 __IO uint32_t SC1D; /**< ADC Status and Control Register 1, offset: 0xC */ 81 __IO uint32_t SC1E; /**< ADC Status and Control Register 1, offset: 0x10 */ 82 __IO uint32_t SC1F; /**< ADC Status and Control Register 1, offset: 0x14 */ 83 __IO uint32_t SC1G; /**< ADC Status and Control Register 1, offset: 0x18 */ 84 __IO uint32_t SC1H; /**< ADC Status and Control Register 1, offset: 0x1C */ 85 __IO uint32_t SC1I; /**< ADC Status and Control Register 1, offset: 0x20 */ 86 __IO uint32_t SC1J; /**< ADC Status and Control Register 1, offset: 0x24 */ 87 __IO uint32_t SC1K; /**< ADC Status and Control Register 1, offset: 0x28 */ 88 __IO uint32_t SC1L; /**< ADC Status and Control Register 1, offset: 0x2C */ 89 __IO uint32_t SC1M; /**< ADC Status and Control Register 1, offset: 0x30 */ 90 __IO uint32_t SC1N; /**< ADC Status and Control Register 1, offset: 0x34 */ 91 __IO uint32_t SC1O; /**< ADC Status and Control Register 1, offset: 0x38 */ 92 __IO uint32_t SC1P; /**< ADC Status and Control Register 1, offset: 0x3C */ 93 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ 94 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0x44 */ 95 __I uint32_t RA; /**< ADC Data Result Registers, offset: 0x48 */ 96 __I uint32_t RB; /**< ADC Data Result Registers, offset: 0x4C */ 97 __I uint32_t RC; /**< ADC Data Result Registers, offset: 0x50 */ 98 __I uint32_t RD; /**< ADC Data Result Registers, offset: 0x54 */ 99 __I uint32_t RE; /**< ADC Data Result Registers, offset: 0x58 */ 100 __I uint32_t RF; /**< ADC Data Result Registers, offset: 0x5C */ 101 __I uint32_t RG; /**< ADC Data Result Registers, offset: 0x60 */ 102 __I uint32_t RH; /**< ADC Data Result Registers, offset: 0x64 */ 103 __I uint32_t RI; /**< ADC Data Result Registers, offset: 0x68 */ 104 __I uint32_t RJ; /**< ADC Data Result Registers, offset: 0x6C */ 105 __I uint32_t RK; /**< ADC Data Result Registers, offset: 0x70 */ 106 __I uint32_t RL; /**< ADC Data Result Registers, offset: 0x74 */ 107 __I uint32_t RM; /**< ADC Data Result Registers, offset: 0x78 */ 108 __I uint32_t RN; /**< ADC Data Result Registers, offset: 0x7C */ 109 __I uint32_t RO; /**< ADC Data Result Registers, offset: 0x80 */ 110 __I uint32_t RP; /**< ADC Data Result Registers, offset: 0x84 */ 111 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x88 */ 112 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x8C */ 113 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x90 */ 114 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x94 */ 115 __IO uint32_t BASE_OFS; /**< BASE Offset Register, offset: 0x98 */ 116 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x9C */ 117 __IO uint32_t USR_OFS; /**< USER Offset Correction Register, offset: 0xA0 */ 118 __IO uint32_t XOFS; /**< ADC X Offset Correction Register, offset: 0xA4 */ 119 __IO uint32_t YOFS; /**< ADC Y Offset Correction Register, offset: 0xA8 */ 120 __IO uint32_t G; /**< ADC Gain Register, offset: 0xAC */ 121 __IO uint32_t UG; /**< ADC User Gain Register, offset: 0xB0 */ 122 __IO uint32_t CLPS; /**< ADC General Calibration Value Register S, offset: 0xB4 */ 123 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register 3, offset: 0xB8 */ 124 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register 2, offset: 0xBC */ 125 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register 1, offset: 0xC0 */ 126 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register 0, offset: 0xC4 */ 127 __IO uint32_t CLPX; /**< ADC Plus-Side General Calibration Value Register X, offset: 0xC8 */ 128 __IO uint32_t CLP9; /**< ADC Plus-Side General Calibration Value Register 9, offset: 0xCC */ 129 __IO uint32_t CLPS_OFS; /**< ADC General Calibration Offset Value Register S, offset: 0xD0 */ 130 __IO uint32_t CLP3_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 3, offset: 0xD4 */ 131 __IO uint32_t CLP2_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 2, offset: 0xD8 */ 132 __IO uint32_t CLP1_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 1, offset: 0xDC */ 133 __IO uint32_t CLP0_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 0, offset: 0xE0 */ 134 __IO uint32_t CLPX_OFS; /**< ADC Plus-Side General Calibration Offset Value Register X, offset: 0xE4 */ 135 __IO uint32_t CLP9_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 9, offset: 0xE8 */ 136 uint8_t RESERVED_0[28]; 137 __IO uint32_t SC1[ADC_SC1_COUNT]; /**< ADC Status and Control Register 1, array offset: 0x108, array step: 0x4 */ 138 uint8_t RESERVED_1[32]; 139 __I uint32_t R[ADC_R_COUNT]; /**< ADC Data Result Registers, array offset: 0x188, array step: 0x4 */ 140 } ADC_Type, *ADC_MemMapPtr; 141 142 /** Number of instances of the ADC module. */ 143 #define ADC_INSTANCE_COUNT (2u) 144 145 /* ADC - Peripheral instance base addresses */ 146 /** Peripheral ADC0 base address */ 147 #define IP_ADC0_BASE (0x4003B000u) 148 /** Peripheral ADC0 base pointer */ 149 #define IP_ADC0 ((ADC_Type *)IP_ADC0_BASE) 150 /** Peripheral ADC1 base address */ 151 #define IP_ADC1_BASE (0x40027000u) 152 /** Peripheral ADC1 base pointer */ 153 #define IP_ADC1 ((ADC_Type *)IP_ADC1_BASE) 154 /** Array initializer of ADC peripheral base addresses */ 155 #define IP_ADC_BASE_ADDRS { IP_ADC0_BASE, IP_ADC1_BASE } 156 /** Array initializer of ADC peripheral base pointers */ 157 #define IP_ADC_BASE_PTRS { IP_ADC0, IP_ADC1 } 158 159 /* ---------------------------------------------------------------------------- 160 -- ADC Register Masks 161 ---------------------------------------------------------------------------- */ 162 163 /*! 164 * @addtogroup ADC_Register_Masks ADC Register Masks 165 * @{ 166 */ 167 168 /*! @name SC1A - ADC Status and Control Register 1 */ 169 /*! @{ */ 170 171 #define ADC_SC1A_ADCH_MASK (0x3FU) 172 #define ADC_SC1A_ADCH_SHIFT (0U) 173 #define ADC_SC1A_ADCH_WIDTH (6U) 174 #define ADC_SC1A_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1A_ADCH_SHIFT)) & ADC_SC1A_ADCH_MASK) 175 176 #define ADC_SC1A_AIEN_MASK (0x40U) 177 #define ADC_SC1A_AIEN_SHIFT (6U) 178 #define ADC_SC1A_AIEN_WIDTH (1U) 179 #define ADC_SC1A_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1A_AIEN_SHIFT)) & ADC_SC1A_AIEN_MASK) 180 181 #define ADC_SC1A_COCO_MASK (0x80U) 182 #define ADC_SC1A_COCO_SHIFT (7U) 183 #define ADC_SC1A_COCO_WIDTH (1U) 184 #define ADC_SC1A_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1A_COCO_SHIFT)) & ADC_SC1A_COCO_MASK) 185 /*! @} */ 186 187 /*! @name SC1B - ADC Status and Control Register 1 */ 188 /*! @{ */ 189 190 #define ADC_SC1B_ADCH_MASK (0x3FU) 191 #define ADC_SC1B_ADCH_SHIFT (0U) 192 #define ADC_SC1B_ADCH_WIDTH (6U) 193 #define ADC_SC1B_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1B_ADCH_SHIFT)) & ADC_SC1B_ADCH_MASK) 194 195 #define ADC_SC1B_AIEN_MASK (0x40U) 196 #define ADC_SC1B_AIEN_SHIFT (6U) 197 #define ADC_SC1B_AIEN_WIDTH (1U) 198 #define ADC_SC1B_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1B_AIEN_SHIFT)) & ADC_SC1B_AIEN_MASK) 199 200 #define ADC_SC1B_COCO_MASK (0x80U) 201 #define ADC_SC1B_COCO_SHIFT (7U) 202 #define ADC_SC1B_COCO_WIDTH (1U) 203 #define ADC_SC1B_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1B_COCO_SHIFT)) & ADC_SC1B_COCO_MASK) 204 /*! @} */ 205 206 /*! @name SC1C - ADC Status and Control Register 1 */ 207 /*! @{ */ 208 209 #define ADC_SC1C_ADCH_MASK (0x3FU) 210 #define ADC_SC1C_ADCH_SHIFT (0U) 211 #define ADC_SC1C_ADCH_WIDTH (6U) 212 #define ADC_SC1C_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1C_ADCH_SHIFT)) & ADC_SC1C_ADCH_MASK) 213 214 #define ADC_SC1C_AIEN_MASK (0x40U) 215 #define ADC_SC1C_AIEN_SHIFT (6U) 216 #define ADC_SC1C_AIEN_WIDTH (1U) 217 #define ADC_SC1C_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1C_AIEN_SHIFT)) & ADC_SC1C_AIEN_MASK) 218 219 #define ADC_SC1C_COCO_MASK (0x80U) 220 #define ADC_SC1C_COCO_SHIFT (7U) 221 #define ADC_SC1C_COCO_WIDTH (1U) 222 #define ADC_SC1C_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1C_COCO_SHIFT)) & ADC_SC1C_COCO_MASK) 223 /*! @} */ 224 225 /*! @name SC1D - ADC Status and Control Register 1 */ 226 /*! @{ */ 227 228 #define ADC_SC1D_ADCH_MASK (0x3FU) 229 #define ADC_SC1D_ADCH_SHIFT (0U) 230 #define ADC_SC1D_ADCH_WIDTH (6U) 231 #define ADC_SC1D_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1D_ADCH_SHIFT)) & ADC_SC1D_ADCH_MASK) 232 233 #define ADC_SC1D_AIEN_MASK (0x40U) 234 #define ADC_SC1D_AIEN_SHIFT (6U) 235 #define ADC_SC1D_AIEN_WIDTH (1U) 236 #define ADC_SC1D_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1D_AIEN_SHIFT)) & ADC_SC1D_AIEN_MASK) 237 238 #define ADC_SC1D_COCO_MASK (0x80U) 239 #define ADC_SC1D_COCO_SHIFT (7U) 240 #define ADC_SC1D_COCO_WIDTH (1U) 241 #define ADC_SC1D_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1D_COCO_SHIFT)) & ADC_SC1D_COCO_MASK) 242 /*! @} */ 243 244 /*! @name SC1E - ADC Status and Control Register 1 */ 245 /*! @{ */ 246 247 #define ADC_SC1E_ADCH_MASK (0x3FU) 248 #define ADC_SC1E_ADCH_SHIFT (0U) 249 #define ADC_SC1E_ADCH_WIDTH (6U) 250 #define ADC_SC1E_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1E_ADCH_SHIFT)) & ADC_SC1E_ADCH_MASK) 251 252 #define ADC_SC1E_AIEN_MASK (0x40U) 253 #define ADC_SC1E_AIEN_SHIFT (6U) 254 #define ADC_SC1E_AIEN_WIDTH (1U) 255 #define ADC_SC1E_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1E_AIEN_SHIFT)) & ADC_SC1E_AIEN_MASK) 256 257 #define ADC_SC1E_COCO_MASK (0x80U) 258 #define ADC_SC1E_COCO_SHIFT (7U) 259 #define ADC_SC1E_COCO_WIDTH (1U) 260 #define ADC_SC1E_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1E_COCO_SHIFT)) & ADC_SC1E_COCO_MASK) 261 /*! @} */ 262 263 /*! @name SC1F - ADC Status and Control Register 1 */ 264 /*! @{ */ 265 266 #define ADC_SC1F_ADCH_MASK (0x3FU) 267 #define ADC_SC1F_ADCH_SHIFT (0U) 268 #define ADC_SC1F_ADCH_WIDTH (6U) 269 #define ADC_SC1F_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1F_ADCH_SHIFT)) & ADC_SC1F_ADCH_MASK) 270 271 #define ADC_SC1F_AIEN_MASK (0x40U) 272 #define ADC_SC1F_AIEN_SHIFT (6U) 273 #define ADC_SC1F_AIEN_WIDTH (1U) 274 #define ADC_SC1F_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1F_AIEN_SHIFT)) & ADC_SC1F_AIEN_MASK) 275 276 #define ADC_SC1F_COCO_MASK (0x80U) 277 #define ADC_SC1F_COCO_SHIFT (7U) 278 #define ADC_SC1F_COCO_WIDTH (1U) 279 #define ADC_SC1F_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1F_COCO_SHIFT)) & ADC_SC1F_COCO_MASK) 280 /*! @} */ 281 282 /*! @name SC1G - ADC Status and Control Register 1 */ 283 /*! @{ */ 284 285 #define ADC_SC1G_ADCH_MASK (0x3FU) 286 #define ADC_SC1G_ADCH_SHIFT (0U) 287 #define ADC_SC1G_ADCH_WIDTH (6U) 288 #define ADC_SC1G_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1G_ADCH_SHIFT)) & ADC_SC1G_ADCH_MASK) 289 290 #define ADC_SC1G_AIEN_MASK (0x40U) 291 #define ADC_SC1G_AIEN_SHIFT (6U) 292 #define ADC_SC1G_AIEN_WIDTH (1U) 293 #define ADC_SC1G_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1G_AIEN_SHIFT)) & ADC_SC1G_AIEN_MASK) 294 295 #define ADC_SC1G_COCO_MASK (0x80U) 296 #define ADC_SC1G_COCO_SHIFT (7U) 297 #define ADC_SC1G_COCO_WIDTH (1U) 298 #define ADC_SC1G_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1G_COCO_SHIFT)) & ADC_SC1G_COCO_MASK) 299 /*! @} */ 300 301 /*! @name SC1H - ADC Status and Control Register 1 */ 302 /*! @{ */ 303 304 #define ADC_SC1H_ADCH_MASK (0x3FU) 305 #define ADC_SC1H_ADCH_SHIFT (0U) 306 #define ADC_SC1H_ADCH_WIDTH (6U) 307 #define ADC_SC1H_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1H_ADCH_SHIFT)) & ADC_SC1H_ADCH_MASK) 308 309 #define ADC_SC1H_AIEN_MASK (0x40U) 310 #define ADC_SC1H_AIEN_SHIFT (6U) 311 #define ADC_SC1H_AIEN_WIDTH (1U) 312 #define ADC_SC1H_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1H_AIEN_SHIFT)) & ADC_SC1H_AIEN_MASK) 313 314 #define ADC_SC1H_COCO_MASK (0x80U) 315 #define ADC_SC1H_COCO_SHIFT (7U) 316 #define ADC_SC1H_COCO_WIDTH (1U) 317 #define ADC_SC1H_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1H_COCO_SHIFT)) & ADC_SC1H_COCO_MASK) 318 /*! @} */ 319 320 /*! @name SC1I - ADC Status and Control Register 1 */ 321 /*! @{ */ 322 323 #define ADC_SC1I_ADCH_MASK (0x3FU) 324 #define ADC_SC1I_ADCH_SHIFT (0U) 325 #define ADC_SC1I_ADCH_WIDTH (6U) 326 #define ADC_SC1I_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1I_ADCH_SHIFT)) & ADC_SC1I_ADCH_MASK) 327 328 #define ADC_SC1I_AIEN_MASK (0x40U) 329 #define ADC_SC1I_AIEN_SHIFT (6U) 330 #define ADC_SC1I_AIEN_WIDTH (1U) 331 #define ADC_SC1I_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1I_AIEN_SHIFT)) & ADC_SC1I_AIEN_MASK) 332 333 #define ADC_SC1I_COCO_MASK (0x80U) 334 #define ADC_SC1I_COCO_SHIFT (7U) 335 #define ADC_SC1I_COCO_WIDTH (1U) 336 #define ADC_SC1I_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1I_COCO_SHIFT)) & ADC_SC1I_COCO_MASK) 337 /*! @} */ 338 339 /*! @name SC1J - ADC Status and Control Register 1 */ 340 /*! @{ */ 341 342 #define ADC_SC1J_ADCH_MASK (0x3FU) 343 #define ADC_SC1J_ADCH_SHIFT (0U) 344 #define ADC_SC1J_ADCH_WIDTH (6U) 345 #define ADC_SC1J_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1J_ADCH_SHIFT)) & ADC_SC1J_ADCH_MASK) 346 347 #define ADC_SC1J_AIEN_MASK (0x40U) 348 #define ADC_SC1J_AIEN_SHIFT (6U) 349 #define ADC_SC1J_AIEN_WIDTH (1U) 350 #define ADC_SC1J_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1J_AIEN_SHIFT)) & ADC_SC1J_AIEN_MASK) 351 352 #define ADC_SC1J_COCO_MASK (0x80U) 353 #define ADC_SC1J_COCO_SHIFT (7U) 354 #define ADC_SC1J_COCO_WIDTH (1U) 355 #define ADC_SC1J_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1J_COCO_SHIFT)) & ADC_SC1J_COCO_MASK) 356 /*! @} */ 357 358 /*! @name SC1K - ADC Status and Control Register 1 */ 359 /*! @{ */ 360 361 #define ADC_SC1K_ADCH_MASK (0x3FU) 362 #define ADC_SC1K_ADCH_SHIFT (0U) 363 #define ADC_SC1K_ADCH_WIDTH (6U) 364 #define ADC_SC1K_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1K_ADCH_SHIFT)) & ADC_SC1K_ADCH_MASK) 365 366 #define ADC_SC1K_AIEN_MASK (0x40U) 367 #define ADC_SC1K_AIEN_SHIFT (6U) 368 #define ADC_SC1K_AIEN_WIDTH (1U) 369 #define ADC_SC1K_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1K_AIEN_SHIFT)) & ADC_SC1K_AIEN_MASK) 370 371 #define ADC_SC1K_COCO_MASK (0x80U) 372 #define ADC_SC1K_COCO_SHIFT (7U) 373 #define ADC_SC1K_COCO_WIDTH (1U) 374 #define ADC_SC1K_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1K_COCO_SHIFT)) & ADC_SC1K_COCO_MASK) 375 /*! @} */ 376 377 /*! @name SC1L - ADC Status and Control Register 1 */ 378 /*! @{ */ 379 380 #define ADC_SC1L_ADCH_MASK (0x3FU) 381 #define ADC_SC1L_ADCH_SHIFT (0U) 382 #define ADC_SC1L_ADCH_WIDTH (6U) 383 #define ADC_SC1L_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1L_ADCH_SHIFT)) & ADC_SC1L_ADCH_MASK) 384 385 #define ADC_SC1L_AIEN_MASK (0x40U) 386 #define ADC_SC1L_AIEN_SHIFT (6U) 387 #define ADC_SC1L_AIEN_WIDTH (1U) 388 #define ADC_SC1L_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1L_AIEN_SHIFT)) & ADC_SC1L_AIEN_MASK) 389 390 #define ADC_SC1L_COCO_MASK (0x80U) 391 #define ADC_SC1L_COCO_SHIFT (7U) 392 #define ADC_SC1L_COCO_WIDTH (1U) 393 #define ADC_SC1L_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1L_COCO_SHIFT)) & ADC_SC1L_COCO_MASK) 394 /*! @} */ 395 396 /*! @name SC1M - ADC Status and Control Register 1 */ 397 /*! @{ */ 398 399 #define ADC_SC1M_ADCH_MASK (0x3FU) 400 #define ADC_SC1M_ADCH_SHIFT (0U) 401 #define ADC_SC1M_ADCH_WIDTH (6U) 402 #define ADC_SC1M_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1M_ADCH_SHIFT)) & ADC_SC1M_ADCH_MASK) 403 404 #define ADC_SC1M_AIEN_MASK (0x40U) 405 #define ADC_SC1M_AIEN_SHIFT (6U) 406 #define ADC_SC1M_AIEN_WIDTH (1U) 407 #define ADC_SC1M_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1M_AIEN_SHIFT)) & ADC_SC1M_AIEN_MASK) 408 409 #define ADC_SC1M_COCO_MASK (0x80U) 410 #define ADC_SC1M_COCO_SHIFT (7U) 411 #define ADC_SC1M_COCO_WIDTH (1U) 412 #define ADC_SC1M_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1M_COCO_SHIFT)) & ADC_SC1M_COCO_MASK) 413 /*! @} */ 414 415 /*! @name SC1N - ADC Status and Control Register 1 */ 416 /*! @{ */ 417 418 #define ADC_SC1N_ADCH_MASK (0x3FU) 419 #define ADC_SC1N_ADCH_SHIFT (0U) 420 #define ADC_SC1N_ADCH_WIDTH (6U) 421 #define ADC_SC1N_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1N_ADCH_SHIFT)) & ADC_SC1N_ADCH_MASK) 422 423 #define ADC_SC1N_AIEN_MASK (0x40U) 424 #define ADC_SC1N_AIEN_SHIFT (6U) 425 #define ADC_SC1N_AIEN_WIDTH (1U) 426 #define ADC_SC1N_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1N_AIEN_SHIFT)) & ADC_SC1N_AIEN_MASK) 427 428 #define ADC_SC1N_COCO_MASK (0x80U) 429 #define ADC_SC1N_COCO_SHIFT (7U) 430 #define ADC_SC1N_COCO_WIDTH (1U) 431 #define ADC_SC1N_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1N_COCO_SHIFT)) & ADC_SC1N_COCO_MASK) 432 /*! @} */ 433 434 /*! @name SC1O - ADC Status and Control Register 1 */ 435 /*! @{ */ 436 437 #define ADC_SC1O_ADCH_MASK (0x3FU) 438 #define ADC_SC1O_ADCH_SHIFT (0U) 439 #define ADC_SC1O_ADCH_WIDTH (6U) 440 #define ADC_SC1O_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1O_ADCH_SHIFT)) & ADC_SC1O_ADCH_MASK) 441 442 #define ADC_SC1O_AIEN_MASK (0x40U) 443 #define ADC_SC1O_AIEN_SHIFT (6U) 444 #define ADC_SC1O_AIEN_WIDTH (1U) 445 #define ADC_SC1O_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1O_AIEN_SHIFT)) & ADC_SC1O_AIEN_MASK) 446 447 #define ADC_SC1O_COCO_MASK (0x80U) 448 #define ADC_SC1O_COCO_SHIFT (7U) 449 #define ADC_SC1O_COCO_WIDTH (1U) 450 #define ADC_SC1O_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1O_COCO_SHIFT)) & ADC_SC1O_COCO_MASK) 451 /*! @} */ 452 453 /*! @name SC1P - ADC Status and Control Register 1 */ 454 /*! @{ */ 455 456 #define ADC_SC1P_ADCH_MASK (0x3FU) 457 #define ADC_SC1P_ADCH_SHIFT (0U) 458 #define ADC_SC1P_ADCH_WIDTH (6U) 459 #define ADC_SC1P_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1P_ADCH_SHIFT)) & ADC_SC1P_ADCH_MASK) 460 461 #define ADC_SC1P_AIEN_MASK (0x40U) 462 #define ADC_SC1P_AIEN_SHIFT (6U) 463 #define ADC_SC1P_AIEN_WIDTH (1U) 464 #define ADC_SC1P_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1P_AIEN_SHIFT)) & ADC_SC1P_AIEN_MASK) 465 466 #define ADC_SC1P_COCO_MASK (0x80U) 467 #define ADC_SC1P_COCO_SHIFT (7U) 468 #define ADC_SC1P_COCO_WIDTH (1U) 469 #define ADC_SC1P_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1P_COCO_SHIFT)) & ADC_SC1P_COCO_MASK) 470 /*! @} */ 471 472 /*! @name CFG1 - ADC Configuration Register 1 */ 473 /*! @{ */ 474 475 #define ADC_CFG1_ADICLK_MASK (0x3U) 476 #define ADC_CFG1_ADICLK_SHIFT (0U) 477 #define ADC_CFG1_ADICLK_WIDTH (2U) 478 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) 479 480 #define ADC_CFG1_MODE_MASK (0xCU) 481 #define ADC_CFG1_MODE_SHIFT (2U) 482 #define ADC_CFG1_MODE_WIDTH (2U) 483 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) 484 485 #define ADC_CFG1_ADIV_MASK (0x60U) 486 #define ADC_CFG1_ADIV_SHIFT (5U) 487 #define ADC_CFG1_ADIV_WIDTH (2U) 488 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) 489 490 #define ADC_CFG1_CLRLTRG_MASK (0x100U) 491 #define ADC_CFG1_CLRLTRG_SHIFT (8U) 492 #define ADC_CFG1_CLRLTRG_WIDTH (1U) 493 #define ADC_CFG1_CLRLTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_CLRLTRG_SHIFT)) & ADC_CFG1_CLRLTRG_MASK) 494 /*! @} */ 495 496 /*! @name CFG2 - ADC Configuration Register 2 */ 497 /*! @{ */ 498 499 #define ADC_CFG2_SMPLTS_MASK (0xFFU) 500 #define ADC_CFG2_SMPLTS_SHIFT (0U) 501 #define ADC_CFG2_SMPLTS_WIDTH (8U) 502 #define ADC_CFG2_SMPLTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_SMPLTS_SHIFT)) & ADC_CFG2_SMPLTS_MASK) 503 /*! @} */ 504 505 /*! @name RA - ADC Data Result Registers */ 506 /*! @{ */ 507 508 #define ADC_RA_D_MASK (0xFFFU) 509 #define ADC_RA_D_SHIFT (0U) 510 #define ADC_RA_D_WIDTH (12U) 511 #define ADC_RA_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RA_D_SHIFT)) & ADC_RA_D_MASK) 512 /*! @} */ 513 514 /*! @name RB - ADC Data Result Registers */ 515 /*! @{ */ 516 517 #define ADC_RB_D_MASK (0xFFFU) 518 #define ADC_RB_D_SHIFT (0U) 519 #define ADC_RB_D_WIDTH (12U) 520 #define ADC_RB_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RB_D_SHIFT)) & ADC_RB_D_MASK) 521 /*! @} */ 522 523 /*! @name RC - ADC Data Result Registers */ 524 /*! @{ */ 525 526 #define ADC_RC_D_MASK (0xFFFU) 527 #define ADC_RC_D_SHIFT (0U) 528 #define ADC_RC_D_WIDTH (12U) 529 #define ADC_RC_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RC_D_SHIFT)) & ADC_RC_D_MASK) 530 /*! @} */ 531 532 /*! @name RD - ADC Data Result Registers */ 533 /*! @{ */ 534 535 #define ADC_RD_D_MASK (0xFFFU) 536 #define ADC_RD_D_SHIFT (0U) 537 #define ADC_RD_D_WIDTH (12U) 538 #define ADC_RD_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RD_D_SHIFT)) & ADC_RD_D_MASK) 539 /*! @} */ 540 541 /*! @name RE - ADC Data Result Registers */ 542 /*! @{ */ 543 544 #define ADC_RE_D_MASK (0xFFFU) 545 #define ADC_RE_D_SHIFT (0U) 546 #define ADC_RE_D_WIDTH (12U) 547 #define ADC_RE_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RE_D_SHIFT)) & ADC_RE_D_MASK) 548 /*! @} */ 549 550 /*! @name RF - ADC Data Result Registers */ 551 /*! @{ */ 552 553 #define ADC_RF_D_MASK (0xFFFU) 554 #define ADC_RF_D_SHIFT (0U) 555 #define ADC_RF_D_WIDTH (12U) 556 #define ADC_RF_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RF_D_SHIFT)) & ADC_RF_D_MASK) 557 /*! @} */ 558 559 /*! @name RG - ADC Data Result Registers */ 560 /*! @{ */ 561 562 #define ADC_RG_D_MASK (0xFFFU) 563 #define ADC_RG_D_SHIFT (0U) 564 #define ADC_RG_D_WIDTH (12U) 565 #define ADC_RG_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RG_D_SHIFT)) & ADC_RG_D_MASK) 566 /*! @} */ 567 568 /*! @name RH - ADC Data Result Registers */ 569 /*! @{ */ 570 571 #define ADC_RH_D_MASK (0xFFFU) 572 #define ADC_RH_D_SHIFT (0U) 573 #define ADC_RH_D_WIDTH (12U) 574 #define ADC_RH_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RH_D_SHIFT)) & ADC_RH_D_MASK) 575 /*! @} */ 576 577 /*! @name RI - ADC Data Result Registers */ 578 /*! @{ */ 579 580 #define ADC_RI_D_MASK (0xFFFU) 581 #define ADC_RI_D_SHIFT (0U) 582 #define ADC_RI_D_WIDTH (12U) 583 #define ADC_RI_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RI_D_SHIFT)) & ADC_RI_D_MASK) 584 /*! @} */ 585 586 /*! @name RJ - ADC Data Result Registers */ 587 /*! @{ */ 588 589 #define ADC_RJ_D_MASK (0xFFFU) 590 #define ADC_RJ_D_SHIFT (0U) 591 #define ADC_RJ_D_WIDTH (12U) 592 #define ADC_RJ_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RJ_D_SHIFT)) & ADC_RJ_D_MASK) 593 /*! @} */ 594 595 /*! @name RK - ADC Data Result Registers */ 596 /*! @{ */ 597 598 #define ADC_RK_D_MASK (0xFFFU) 599 #define ADC_RK_D_SHIFT (0U) 600 #define ADC_RK_D_WIDTH (12U) 601 #define ADC_RK_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RK_D_SHIFT)) & ADC_RK_D_MASK) 602 /*! @} */ 603 604 /*! @name RL - ADC Data Result Registers */ 605 /*! @{ */ 606 607 #define ADC_RL_D_MASK (0xFFFU) 608 #define ADC_RL_D_SHIFT (0U) 609 #define ADC_RL_D_WIDTH (12U) 610 #define ADC_RL_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RL_D_SHIFT)) & ADC_RL_D_MASK) 611 /*! @} */ 612 613 /*! @name RM - ADC Data Result Registers */ 614 /*! @{ */ 615 616 #define ADC_RM_D_MASK (0xFFFU) 617 #define ADC_RM_D_SHIFT (0U) 618 #define ADC_RM_D_WIDTH (12U) 619 #define ADC_RM_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RM_D_SHIFT)) & ADC_RM_D_MASK) 620 /*! @} */ 621 622 /*! @name RN - ADC Data Result Registers */ 623 /*! @{ */ 624 625 #define ADC_RN_D_MASK (0xFFFU) 626 #define ADC_RN_D_SHIFT (0U) 627 #define ADC_RN_D_WIDTH (12U) 628 #define ADC_RN_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RN_D_SHIFT)) & ADC_RN_D_MASK) 629 /*! @} */ 630 631 /*! @name RO - ADC Data Result Registers */ 632 /*! @{ */ 633 634 #define ADC_RO_D_MASK (0xFFFU) 635 #define ADC_RO_D_SHIFT (0U) 636 #define ADC_RO_D_WIDTH (12U) 637 #define ADC_RO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RO_D_SHIFT)) & ADC_RO_D_MASK) 638 /*! @} */ 639 640 /*! @name RP - ADC Data Result Registers */ 641 /*! @{ */ 642 643 #define ADC_RP_D_MASK (0xFFFU) 644 #define ADC_RP_D_SHIFT (0U) 645 #define ADC_RP_D_WIDTH (12U) 646 #define ADC_RP_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RP_D_SHIFT)) & ADC_RP_D_MASK) 647 /*! @} */ 648 649 /*! @name CV1 - Compare Value Registers */ 650 /*! @{ */ 651 652 #define ADC_CV1_CV_MASK (0xFFFFU) 653 #define ADC_CV1_CV_SHIFT (0U) 654 /*! CV - Compare Value. 655 */ 656 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK) 657 /*! @} */ 658 659 /*! @name CV2 - Compare Value Registers */ 660 /*! @{ */ 661 662 #define ADC_CV2_CV_MASK (0xFFFFU) 663 #define ADC_CV2_CV_SHIFT (0U) 664 /*! CV - Compare Value. 665 */ 666 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK) 667 /*! @} */ 668 669 /*! @name SC2 - Status and Control Register 2 */ 670 /*! @{ */ 671 672 #define ADC_SC2_REFSEL_MASK (0x3U) 673 #define ADC_SC2_REFSEL_SHIFT (0U) 674 #define ADC_SC2_REFSEL_WIDTH (2U) 675 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) 676 677 #define ADC_SC2_DMAEN_MASK (0x4U) 678 #define ADC_SC2_DMAEN_SHIFT (2U) 679 #define ADC_SC2_DMAEN_WIDTH (1U) 680 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) 681 682 #define ADC_SC2_ACREN_MASK (0x8U) 683 #define ADC_SC2_ACREN_SHIFT (3U) 684 #define ADC_SC2_ACREN_WIDTH (1U) 685 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) 686 687 #define ADC_SC2_ACFGT_MASK (0x10U) 688 #define ADC_SC2_ACFGT_SHIFT (4U) 689 #define ADC_SC2_ACFGT_WIDTH (1U) 690 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) 691 692 #define ADC_SC2_ACFE_MASK (0x20U) 693 #define ADC_SC2_ACFE_SHIFT (5U) 694 #define ADC_SC2_ACFE_WIDTH (1U) 695 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) 696 697 #define ADC_SC2_ADTRG_MASK (0x40U) 698 #define ADC_SC2_ADTRG_SHIFT (6U) 699 #define ADC_SC2_ADTRG_WIDTH (1U) 700 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) 701 702 #define ADC_SC2_ADACT_MASK (0x80U) 703 #define ADC_SC2_ADACT_SHIFT (7U) 704 #define ADC_SC2_ADACT_WIDTH (1U) 705 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) 706 707 #define ADC_SC2_TRGPRNUM_MASK (0x6000U) 708 #define ADC_SC2_TRGPRNUM_SHIFT (13U) 709 #define ADC_SC2_TRGPRNUM_WIDTH (2U) 710 #define ADC_SC2_TRGPRNUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_TRGPRNUM_SHIFT)) & ADC_SC2_TRGPRNUM_MASK) 711 712 #define ADC_SC2_TRGSTLAT_MASK (0xF0000U) 713 #define ADC_SC2_TRGSTLAT_SHIFT (16U) 714 #define ADC_SC2_TRGSTLAT_WIDTH (4U) 715 #define ADC_SC2_TRGSTLAT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_TRGSTLAT_SHIFT)) & ADC_SC2_TRGSTLAT_MASK) 716 717 #define ADC_SC2_TRGSTERR_MASK (0xF000000U) 718 #define ADC_SC2_TRGSTERR_SHIFT (24U) 719 #define ADC_SC2_TRGSTERR_WIDTH (4U) 720 #define ADC_SC2_TRGSTERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_TRGSTERR_SHIFT)) & ADC_SC2_TRGSTERR_MASK) 721 /*! @} */ 722 723 /*! @name SC3 - Status and Control Register 3 */ 724 /*! @{ */ 725 726 #define ADC_SC3_AVGS_MASK (0x3U) 727 #define ADC_SC3_AVGS_SHIFT (0U) 728 #define ADC_SC3_AVGS_WIDTH (2U) 729 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) 730 731 #define ADC_SC3_AVGE_MASK (0x4U) 732 #define ADC_SC3_AVGE_SHIFT (2U) 733 #define ADC_SC3_AVGE_WIDTH (1U) 734 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) 735 736 #define ADC_SC3_ADCO_MASK (0x8U) 737 #define ADC_SC3_ADCO_SHIFT (3U) 738 #define ADC_SC3_ADCO_WIDTH (1U) 739 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) 740 741 #define ADC_SC3_CAL_MASK (0x80U) 742 #define ADC_SC3_CAL_SHIFT (7U) 743 #define ADC_SC3_CAL_WIDTH (1U) 744 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) 745 /*! @} */ 746 747 /*! @name BASE_OFS - BASE Offset Register */ 748 /*! @{ */ 749 750 #define ADC_BASE_OFS_BA_OFS_MASK (0xFFU) 751 #define ADC_BASE_OFS_BA_OFS_SHIFT (0U) 752 #define ADC_BASE_OFS_BA_OFS_WIDTH (8U) 753 #define ADC_BASE_OFS_BA_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_BASE_OFS_BA_OFS_SHIFT)) & ADC_BASE_OFS_BA_OFS_MASK) 754 /*! @} */ 755 756 /*! @name OFS - ADC Offset Correction Register */ 757 /*! @{ */ 758 759 #define ADC_OFS_OFS_MASK (0xFFFFU) 760 #define ADC_OFS_OFS_SHIFT (0U) 761 #define ADC_OFS_OFS_WIDTH (16U) 762 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) 763 /*! @} */ 764 765 /*! @name USR_OFS - USER Offset Correction Register */ 766 /*! @{ */ 767 768 #define ADC_USR_OFS_USR_OFS_MASK (0xFFU) 769 #define ADC_USR_OFS_USR_OFS_SHIFT (0U) 770 #define ADC_USR_OFS_USR_OFS_WIDTH (8U) 771 #define ADC_USR_OFS_USR_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_USR_OFS_USR_OFS_SHIFT)) & ADC_USR_OFS_USR_OFS_MASK) 772 /*! @} */ 773 774 /*! @name XOFS - ADC X Offset Correction Register */ 775 /*! @{ */ 776 777 #define ADC_XOFS_XOFS_MASK (0x3FU) 778 #define ADC_XOFS_XOFS_SHIFT (0U) 779 #define ADC_XOFS_XOFS_WIDTH (6U) 780 #define ADC_XOFS_XOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_XOFS_XOFS_SHIFT)) & ADC_XOFS_XOFS_MASK) 781 /*! @} */ 782 783 /*! @name YOFS - ADC Y Offset Correction Register */ 784 /*! @{ */ 785 786 #define ADC_YOFS_YOFS_MASK (0xFFU) 787 #define ADC_YOFS_YOFS_SHIFT (0U) 788 #define ADC_YOFS_YOFS_WIDTH (8U) 789 #define ADC_YOFS_YOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_YOFS_YOFS_SHIFT)) & ADC_YOFS_YOFS_MASK) 790 /*! @} */ 791 792 /*! @name G - ADC Gain Register */ 793 /*! @{ */ 794 795 #define ADC_G_G_MASK (0x7FFU) 796 #define ADC_G_G_SHIFT (0U) 797 #define ADC_G_G_WIDTH (11U) 798 #define ADC_G_G(x) (((uint32_t)(((uint32_t)(x)) << ADC_G_G_SHIFT)) & ADC_G_G_MASK) 799 /*! @} */ 800 801 /*! @name UG - ADC User Gain Register */ 802 /*! @{ */ 803 804 #define ADC_UG_UG_MASK (0x3FFU) 805 #define ADC_UG_UG_SHIFT (0U) 806 #define ADC_UG_UG_WIDTH (10U) 807 #define ADC_UG_UG(x) (((uint32_t)(((uint32_t)(x)) << ADC_UG_UG_SHIFT)) & ADC_UG_UG_MASK) 808 /*! @} */ 809 810 /*! @name CLPS - ADC General Calibration Value Register S */ 811 /*! @{ */ 812 813 #define ADC_CLPS_CLPS_MASK (0x7FU) 814 #define ADC_CLPS_CLPS_SHIFT (0U) 815 #define ADC_CLPS_CLPS_WIDTH (7U) 816 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) 817 /*! @} */ 818 819 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register 3 */ 820 /*! @{ */ 821 822 #define ADC_CLP3_CLP3_MASK (0x3FFU) 823 #define ADC_CLP3_CLP3_SHIFT (0U) 824 #define ADC_CLP3_CLP3_WIDTH (10U) 825 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) 826 /*! @} */ 827 828 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register 2 */ 829 /*! @{ */ 830 831 #define ADC_CLP2_CLP2_MASK (0x3FFU) 832 #define ADC_CLP2_CLP2_SHIFT (0U) 833 #define ADC_CLP2_CLP2_WIDTH (10U) 834 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) 835 /*! @} */ 836 837 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register 1 */ 838 /*! @{ */ 839 840 #define ADC_CLP1_CLP1_MASK (0x1FFU) 841 #define ADC_CLP1_CLP1_SHIFT (0U) 842 #define ADC_CLP1_CLP1_WIDTH (9U) 843 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) 844 /*! @} */ 845 846 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register 0 */ 847 /*! @{ */ 848 849 #define ADC_CLP0_CLP0_MASK (0xFFU) 850 #define ADC_CLP0_CLP0_SHIFT (0U) 851 #define ADC_CLP0_CLP0_WIDTH (8U) 852 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) 853 /*! @} */ 854 855 /*! @name CLPX - ADC Plus-Side General Calibration Value Register X */ 856 /*! @{ */ 857 858 #define ADC_CLPX_CLPX_MASK (0x7FU) 859 #define ADC_CLPX_CLPX_SHIFT (0U) 860 #define ADC_CLPX_CLPX_WIDTH (7U) 861 #define ADC_CLPX_CLPX(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPX_CLPX_SHIFT)) & ADC_CLPX_CLPX_MASK) 862 /*! @} */ 863 864 /*! @name CLP9 - ADC Plus-Side General Calibration Value Register 9 */ 865 /*! @{ */ 866 867 #define ADC_CLP9_CLP9_MASK (0x7FU) 868 #define ADC_CLP9_CLP9_SHIFT (0U) 869 #define ADC_CLP9_CLP9_WIDTH (7U) 870 #define ADC_CLP9_CLP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP9_CLP9_SHIFT)) & ADC_CLP9_CLP9_MASK) 871 /*! @} */ 872 873 /*! @name CLPS_OFS - ADC General Calibration Offset Value Register S */ 874 /*! @{ */ 875 876 #define ADC_CLPS_OFS_CLPS_OFS_MASK (0xFU) 877 #define ADC_CLPS_OFS_CLPS_OFS_SHIFT (0U) 878 #define ADC_CLPS_OFS_CLPS_OFS_WIDTH (4U) 879 #define ADC_CLPS_OFS_CLPS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_OFS_CLPS_OFS_SHIFT)) & ADC_CLPS_OFS_CLPS_OFS_MASK) 880 /*! @} */ 881 882 /*! @name CLP3_OFS - ADC Plus-Side General Calibration Offset Value Register 3 */ 883 /*! @{ */ 884 885 #define ADC_CLP3_OFS_CLP3_OFS_MASK (0xFU) 886 #define ADC_CLP3_OFS_CLP3_OFS_SHIFT (0U) 887 #define ADC_CLP3_OFS_CLP3_OFS_WIDTH (4U) 888 #define ADC_CLP3_OFS_CLP3_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_OFS_CLP3_OFS_SHIFT)) & ADC_CLP3_OFS_CLP3_OFS_MASK) 889 /*! @} */ 890 891 /*! @name CLP2_OFS - ADC Plus-Side General Calibration Offset Value Register 2 */ 892 /*! @{ */ 893 894 #define ADC_CLP2_OFS_CLP2_OFS_MASK (0xFU) 895 #define ADC_CLP2_OFS_CLP2_OFS_SHIFT (0U) 896 #define ADC_CLP2_OFS_CLP2_OFS_WIDTH (4U) 897 #define ADC_CLP2_OFS_CLP2_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_OFS_CLP2_OFS_SHIFT)) & ADC_CLP2_OFS_CLP2_OFS_MASK) 898 /*! @} */ 899 900 /*! @name CLP1_OFS - ADC Plus-Side General Calibration Offset Value Register 1 */ 901 /*! @{ */ 902 903 #define ADC_CLP1_OFS_CLP1_OFS_MASK (0xFU) 904 #define ADC_CLP1_OFS_CLP1_OFS_SHIFT (0U) 905 #define ADC_CLP1_OFS_CLP1_OFS_WIDTH (4U) 906 #define ADC_CLP1_OFS_CLP1_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_OFS_CLP1_OFS_SHIFT)) & ADC_CLP1_OFS_CLP1_OFS_MASK) 907 /*! @} */ 908 909 /*! @name CLP0_OFS - ADC Plus-Side General Calibration Offset Value Register 0 */ 910 /*! @{ */ 911 912 #define ADC_CLP0_OFS_CLP0_OFS_MASK (0xFU) 913 #define ADC_CLP0_OFS_CLP0_OFS_SHIFT (0U) 914 #define ADC_CLP0_OFS_CLP0_OFS_WIDTH (4U) 915 #define ADC_CLP0_OFS_CLP0_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_OFS_CLP0_OFS_SHIFT)) & ADC_CLP0_OFS_CLP0_OFS_MASK) 916 /*! @} */ 917 918 /*! @name CLPX_OFS - ADC Plus-Side General Calibration Offset Value Register X */ 919 /*! @{ */ 920 921 #define ADC_CLPX_OFS_CLPX_OFS_MASK (0xFFFU) 922 #define ADC_CLPX_OFS_CLPX_OFS_SHIFT (0U) 923 #define ADC_CLPX_OFS_CLPX_OFS_WIDTH (12U) 924 #define ADC_CLPX_OFS_CLPX_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPX_OFS_CLPX_OFS_SHIFT)) & ADC_CLPX_OFS_CLPX_OFS_MASK) 925 /*! @} */ 926 927 /*! @name CLP9_OFS - ADC Plus-Side General Calibration Offset Value Register 9 */ 928 /*! @{ */ 929 930 #define ADC_CLP9_OFS_CLP9_OFS_MASK (0xFFFU) 931 #define ADC_CLP9_OFS_CLP9_OFS_SHIFT (0U) 932 #define ADC_CLP9_OFS_CLP9_OFS_WIDTH (12U) 933 #define ADC_CLP9_OFS_CLP9_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP9_OFS_CLP9_OFS_SHIFT)) & ADC_CLP9_OFS_CLP9_OFS_MASK) 934 /*! @} */ 935 936 /*! @name SC1 - ADC Status and Control Register 1 */ 937 /*! @{ */ 938 939 #define ADC_SC1_ADCH_MASK (0x3FU) 940 #define ADC_SC1_ADCH_SHIFT (0U) 941 #define ADC_SC1_ADCH_WIDTH (6U) 942 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) 943 944 #define ADC_SC1_AIEN_MASK (0x40U) 945 #define ADC_SC1_AIEN_SHIFT (6U) 946 #define ADC_SC1_AIEN_WIDTH (1U) 947 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) 948 949 #define ADC_SC1_COCO_MASK (0x80U) 950 #define ADC_SC1_COCO_SHIFT (7U) 951 #define ADC_SC1_COCO_WIDTH (1U) 952 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) 953 /*! @} */ 954 955 /*! @name R - ADC Data Result Registers */ 956 /*! @{ */ 957 958 #define ADC_R_D_MASK (0xFFFU) 959 #define ADC_R_D_SHIFT (0U) 960 #define ADC_R_D_WIDTH (12U) 961 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) 962 /*! @} */ 963 964 /*! 965 * @} 966 */ /* end of group ADC_Register_Masks */ 967 968 /*! 969 * @} 970 */ /* end of group ADC_Peripheral_Access_Layer */ 971 972 #endif /* #if !defined(S32K146_ADC_H_) */ 973
