1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K144_SMC.h 10 * @version 1.1 11 * @date 2022-02-07 12 * @brief Peripheral Access Layer for S32K144_SMC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K144_SMC_H_) /* Check if memory map has not been already included */ 58 #define S32K144_SMC_H_ 59 60 #include "S32K144_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SMC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SMC - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t VERID; /**< SMC Version ID Register, offset: 0x0 */ 74 __I uint32_t PARAM; /**< SMC Parameter Register, offset: 0x4 */ 75 __IO uint32_t PMPROT; /**< Power Mode Protection register, offset: 0x8 */ 76 __IO uint32_t PMCTRL; /**< Power Mode Control register, offset: 0xC */ 77 __IO uint32_t STOPCTRL; /**< Stop Control Register, offset: 0x10 */ 78 __I uint32_t PMSTAT; /**< Power Mode Status register, offset: 0x14 */ 79 } SMC_Type, *SMC_MemMapPtr; 80 81 /** Number of instances of the SMC module. */ 82 #define SMC_INSTANCE_COUNT (1u) 83 84 /* SMC - Peripheral instance base addresses */ 85 /** Peripheral SMC base address */ 86 #define IP_SMC_BASE (0x4007E000u) 87 /** Peripheral SMC base pointer */ 88 #define IP_SMC ((SMC_Type *)IP_SMC_BASE) 89 /** Array initializer of SMC peripheral base addresses */ 90 #define IP_SMC_BASE_ADDRS { IP_SMC_BASE } 91 /** Array initializer of SMC peripheral base pointers */ 92 #define IP_SMC_BASE_PTRS { IP_SMC } 93 94 /* ---------------------------------------------------------------------------- 95 -- SMC Register Masks 96 ---------------------------------------------------------------------------- */ 97 98 /*! 99 * @addtogroup SMC_Register_Masks SMC Register Masks 100 * @{ 101 */ 102 103 /*! @name VERID - SMC Version ID Register */ 104 /*! @{ */ 105 106 #define SMC_VERID_FEATURE_MASK (0xFFFFU) 107 #define SMC_VERID_FEATURE_SHIFT (0U) 108 #define SMC_VERID_FEATURE_WIDTH (16U) 109 #define SMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_FEATURE_SHIFT)) & SMC_VERID_FEATURE_MASK) 110 111 #define SMC_VERID_MINOR_MASK (0xFF0000U) 112 #define SMC_VERID_MINOR_SHIFT (16U) 113 #define SMC_VERID_MINOR_WIDTH (8U) 114 #define SMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_MINOR_SHIFT)) & SMC_VERID_MINOR_MASK) 115 116 #define SMC_VERID_MAJOR_MASK (0xFF000000U) 117 #define SMC_VERID_MAJOR_SHIFT (24U) 118 #define SMC_VERID_MAJOR_WIDTH (8U) 119 #define SMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_MAJOR_SHIFT)) & SMC_VERID_MAJOR_MASK) 120 /*! @} */ 121 122 /*! @name PARAM - SMC Parameter Register */ 123 /*! @{ */ 124 125 #define SMC_PARAM_EHSRUN_MASK (0x1U) 126 #define SMC_PARAM_EHSRUN_SHIFT (0U) 127 #define SMC_PARAM_EHSRUN_WIDTH (1U) 128 #define SMC_PARAM_EHSRUN(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_EHSRUN_SHIFT)) & SMC_PARAM_EHSRUN_MASK) 129 130 #define SMC_PARAM_ELLS_MASK (0x8U) 131 #define SMC_PARAM_ELLS_SHIFT (3U) 132 #define SMC_PARAM_ELLS_WIDTH (1U) 133 #define SMC_PARAM_ELLS(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_ELLS_SHIFT)) & SMC_PARAM_ELLS_MASK) 134 135 #define SMC_PARAM_ELLS2_MASK (0x20U) 136 #define SMC_PARAM_ELLS2_SHIFT (5U) 137 #define SMC_PARAM_ELLS2_WIDTH (1U) 138 #define SMC_PARAM_ELLS2(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_ELLS2_SHIFT)) & SMC_PARAM_ELLS2_MASK) 139 140 #define SMC_PARAM_EVLLS0_MASK (0x40U) 141 #define SMC_PARAM_EVLLS0_SHIFT (6U) 142 #define SMC_PARAM_EVLLS0_WIDTH (1U) 143 #define SMC_PARAM_EVLLS0(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_EVLLS0_SHIFT)) & SMC_PARAM_EVLLS0_MASK) 144 /*! @} */ 145 146 /*! @name PMPROT - Power Mode Protection register */ 147 /*! @{ */ 148 149 #define SMC_PMPROT_AVLP_MASK (0x20U) 150 #define SMC_PMPROT_AVLP_SHIFT (5U) 151 #define SMC_PMPROT_AVLP_WIDTH (1U) 152 #define SMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) 153 154 #define SMC_PMPROT_AHSRUN_MASK (0x80U) 155 #define SMC_PMPROT_AHSRUN_SHIFT (7U) 156 #define SMC_PMPROT_AHSRUN_WIDTH (1U) 157 #define SMC_PMPROT_AHSRUN(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK) 158 /*! @} */ 159 160 /*! @name PMCTRL - Power Mode Control register */ 161 /*! @{ */ 162 163 #define SMC_PMCTRL_STOPM_MASK (0x7U) 164 #define SMC_PMCTRL_STOPM_SHIFT (0U) 165 #define SMC_PMCTRL_STOPM_WIDTH (3U) 166 #define SMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) 167 168 #define SMC_PMCTRL_VLPSA_MASK (0x8U) 169 #define SMC_PMCTRL_VLPSA_SHIFT (3U) 170 #define SMC_PMCTRL_VLPSA_WIDTH (1U) 171 #define SMC_PMCTRL_VLPSA(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_VLPSA_SHIFT)) & SMC_PMCTRL_VLPSA_MASK) 172 173 #define SMC_PMCTRL_RUNM_MASK (0x60U) 174 #define SMC_PMCTRL_RUNM_SHIFT (5U) 175 #define SMC_PMCTRL_RUNM_WIDTH (2U) 176 #define SMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) 177 /*! @} */ 178 179 /*! @name STOPCTRL - Stop Control Register */ 180 /*! @{ */ 181 182 #define SMC_STOPCTRL_STOPO_MASK (0xC0U) 183 #define SMC_STOPCTRL_STOPO_SHIFT (6U) 184 #define SMC_STOPCTRL_STOPO_WIDTH (2U) 185 #define SMC_STOPCTRL_STOPO(x) (((uint32_t)(((uint32_t)(x)) << SMC_STOPCTRL_STOPO_SHIFT)) & SMC_STOPCTRL_STOPO_MASK) 186 /*! @} */ 187 188 /*! @name PMSTAT - Power Mode Status register */ 189 /*! @{ */ 190 191 #define SMC_PMSTAT_PMSTAT_MASK (0xFFU) 192 #define SMC_PMSTAT_PMSTAT_SHIFT (0U) 193 #define SMC_PMSTAT_PMSTAT_WIDTH (8U) 194 #define SMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) 195 /*! @} */ 196 197 /*! 198 * @} 199 */ /* end of group SMC_Register_Masks */ 200 201 /*! 202 * @} 203 */ /* end of group SMC_Peripheral_Access_Layer */ 204 205 #endif /* #if !defined(S32K144_SMC_H_) */ 206
