1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K144W_PCC.h 10 * @version 1.4 11 * @date 2022-02-09 12 * @brief Peripheral Access Layer for S32K144W_PCC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K144W_PCC_H_) /* Check if memory map has not been already included */ 58 #define S32K144W_PCC_H_ 59 60 #include "S32K144W_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- PCC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup PCC_Peripheral_Access_Layer PCC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** PCC - Size of Registers Arrays */ 72 #define PCC_PCCn_COUNT 116u 73 74 /** PCC - Register Layout Typedef */ 75 typedef struct { 76 __IO uint32_t PCCn[PCC_PCCn_COUNT]; /**< PCC FTFM Register..PCC CMP0 Register, array offset: 0x0, array step: 0x4 */ 77 } PCC_Type, *PCC_MemMapPtr; 78 79 /** Number of instances of the PCC module. */ 80 #define PCC_INSTANCE_COUNT (1u) 81 82 /* PCC - Peripheral instance base addresses */ 83 /** Peripheral PCC base address */ 84 #define IP_PCC_BASE (0x40065000u) 85 /** Peripheral PCC base pointer */ 86 #define IP_PCC ((PCC_Type *)IP_PCC_BASE) 87 /** Array initializer of PCC peripheral base addresses */ 88 #define IP_PCC_BASE_ADDRS { IP_PCC_BASE } 89 /** Array initializer of PCC peripheral base pointers */ 90 #define IP_PCC_BASE_PTRS { IP_PCC } 91 92 /* ---------------------------------------------------------------------------- 93 -- PCC Register Masks 94 ---------------------------------------------------------------------------- */ 95 96 /*! 97 * @addtogroup PCC_Register_Masks PCC Register Masks 98 * @{ 99 */ 100 101 /*! @name PCCn - PCC FTFM Register..PCC CMP0 Register */ 102 /*! @{ */ 103 104 #define PCC_PCCn_PCD_MASK (0x7U) 105 #define PCC_PCCn_PCD_SHIFT (0U) 106 #define PCC_PCCn_PCD_WIDTH (3U) 107 #define PCC_PCCn_PCD(x) (((uint32_t)(((uint32_t)(x)) << PCC_PCCn_PCD_SHIFT)) & PCC_PCCn_PCD_MASK) 108 109 #define PCC_PCCn_FRAC_MASK (0x8U) 110 #define PCC_PCCn_FRAC_SHIFT (3U) 111 #define PCC_PCCn_FRAC_WIDTH (1U) 112 #define PCC_PCCn_FRAC(x) (((uint32_t)(((uint32_t)(x)) << PCC_PCCn_FRAC_SHIFT)) & PCC_PCCn_FRAC_MASK) 113 114 #define PCC_PCCn_PCS_MASK (0x7000000U) 115 #define PCC_PCCn_PCS_SHIFT (24U) 116 #define PCC_PCCn_PCS_WIDTH (3U) 117 #define PCC_PCCn_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC_PCCn_PCS_SHIFT)) & PCC_PCCn_PCS_MASK) 118 119 #define PCC_PCCn_CGC_MASK (0x40000000U) 120 #define PCC_PCCn_CGC_SHIFT (30U) 121 #define PCC_PCCn_CGC_WIDTH (1U) 122 #define PCC_PCCn_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC_PCCn_CGC_SHIFT)) & PCC_PCCn_CGC_MASK) 123 124 #define PCC_PCCn_PR_MASK (0x80000000U) 125 #define PCC_PCCn_PR_SHIFT (31U) 126 #define PCC_PCCn_PR_WIDTH (1U) 127 #define PCC_PCCn_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC_PCCn_PR_SHIFT)) & PCC_PCCn_PR_MASK) 128 /*! @} */ 129 130 /*! 131 * @} 132 */ /* end of group PCC_Register_Masks */ 133 #define PCC_FTFM_INDEX 32 134 #define PCC_DMAMUX_INDEX 33 135 #define PCC_FlexCAN0_INDEX 36 136 #define PCC_FlexCAN1_INDEX 37 137 #define PCC_FTM3_INDEX 38 138 #define PCC_ADC1_INDEX 39 139 #define PCC_LPSPI0_INDEX 44 140 #define PCC_LPSPI1_INDEX 45 141 #define PCC_LPSPI2_INDEX 46 142 #define PCC_PDB1_INDEX 49 143 #define PCC_CRC_INDEX 50 144 #define PCC_PDB0_INDEX 54 145 #define PCC_LPIT_INDEX 55 146 #define PCC_FTM0_INDEX 56 147 #define PCC_FTM1_INDEX 57 148 #define PCC_FTM2_INDEX 58 149 #define PCC_ADC0_INDEX 59 150 #define PCC_RTC_INDEX 61 151 #define PCC_LPTMR0_INDEX 64 152 #define PCC_PORTA_INDEX 73 153 #define PCC_PORTB_INDEX 74 154 #define PCC_PORTC_INDEX 75 155 #define PCC_PORTD_INDEX 76 156 #define PCC_PORTE_INDEX 77 157 #define PCC_FlexIO_INDEX 90 158 #define PCC_EWM_INDEX 97 159 #define PCC_LPI2C0_INDEX 102 160 #define PCC_LPUART0_INDEX 106 161 #define PCC_LPUART1_INDEX 107 162 #define PCC_LPUART2_INDEX 108 163 #define PCC_CMP0_INDEX 115 164 165 166 /*! 167 * @} 168 */ /* end of group PCC_Peripheral_Access_Layer */ 169 170 #endif /* #if !defined(S32K144W_PCC_H_) */ 171
