1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K144W_FLEXCAN.h 10 * @version 1.4 11 * @date 2022-02-09 12 * @brief Peripheral Access Layer for S32K144W_FLEXCAN 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K144W_FLEXCAN_H_) /* Check if memory map has not been already included */ 58 #define S32K144W_FLEXCAN_H_ 59 60 #include "S32K144W_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- FLEXCAN Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CAN_Peripheral_Access_Layer FLEXCAN Peripheral Access Layer 68 * @{ 69 */ 70 71 /** FLEXCAN - Size of Registers Arrays */ 72 #define CAN_RAMn_COUNT 128u 73 #define CAN_RXIMR_COUNT 64u 74 #define CAN_WMB_COUNT 4u 75 76 /** FLEXCAN - Register Layout Typedef */ 77 typedef struct { 78 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ 79 __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */ 80 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */ 81 uint8_t RESERVED_0[4]; 82 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ 83 __IO uint32_t RX14MASK; /**< Rx 14 Mask Register, offset: 0x14 */ 84 __IO uint32_t RX15MASK; /**< Rx 15 Mask Register, offset: 0x18 */ 85 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ 86 __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */ 87 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ 88 __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ 89 __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */ 90 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */ 91 __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ 92 __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */ 93 uint8_t RESERVED_1[8]; 94 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ 95 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */ 96 __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ 97 __IO uint32_t CBT; /**< CAN Bit Timing Register, offset: 0x50 */ 98 uint8_t RESERVED_2[44]; 99 struct { /* offset: 0x80, array step: 0x10 */ 100 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 95 CS Register, array offset: 0x80, array step: 0x10 */ 101 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 95 ID Register, array offset: 0x84, array step: 0x10 */ 102 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 95 WORD0 Register, array offset: 0x88, array step: 0x10 */ 103 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 95 WORD1 Register, array offset: 0x8C, array step: 0x10 */ 104 } MB[64]; 105 uint8_t RESERVED_3[1536]; 106 __IO uint32_t RXIMR[CAN_RXIMR_COUNT]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ 107 uint8_t RESERVED_4[384]; 108 __IO uint32_t CTRL1_PN; /**< Pretended Networking Control 1 Register, offset: 0xB00 */ 109 __IO uint32_t CTRL2_PN; /**< Pretended Networking Control 2 Register, offset: 0xB04 */ 110 __IO uint32_t WU_MTC; /**< Pretended Networking Wake Up Match Register, offset: 0xB08 */ 111 __IO uint32_t FLT_ID1; /**< Pretended Networking ID Filter 1 Register, offset: 0xB0C */ 112 __IO uint32_t FLT_DLC; /**< Pretended Networking DLC Filter Register, offset: 0xB10 */ 113 __IO uint32_t PL1_LO; /**< Pretended Networking Payload Low Filter 1 Register, offset: 0xB14 */ 114 __IO uint32_t PL1_HI; /**< Pretended Networking Payload High Filter 1 Register, offset: 0xB18 */ 115 __IO uint32_t FLT_ID2_IDMASK; /**< Pretended Networking ID Filter 2 Register / ID Mask Register, offset: 0xB1C */ 116 __IO uint32_t PL2_PLMASK_LO; /**< Pretended Networking Payload Low Filter 2 Register / Payload Low Mask register, offset: 0xB20 */ 117 __IO uint32_t PL2_PLMASK_HI; /**< Pretended Networking Payload High Filter 2 low order bits / Payload High Mask register, offset: 0xB24 */ 118 uint8_t RESERVED_5[24]; 119 struct { /* offset: 0xB40, array step: 0x10 */ 120 __I uint32_t WMBn_CS; /**< Wake Up Message Buffer register for C/S, array offset: 0xB40, array step: 0x10 */ 121 __I uint32_t WMBn_ID; /**< Wake Up Message Buffer Register for ID, array offset: 0xB44, array step: 0x10 */ 122 __I uint32_t WMBn_D03; /**< Wake Up Message Buffer Register for Data 0-3, array offset: 0xB48, array step: 0x10 */ 123 __I uint32_t WMBn_D47; /**< Wake Up Message Buffer Register Data 4-7, array offset: 0xB4C, array step: 0x10 */ 124 } WMB[CAN_WMB_COUNT]; 125 uint8_t RESERVED_6[128]; 126 __IO uint32_t FDCTRL; /**< CAN FD Control Register, offset: 0xC00 */ 127 __IO uint32_t FDCBT; /**< CAN FD Bit Timing Register, offset: 0xC04 */ 128 __I uint32_t FDCRC; /**< CAN FD CRC Register, offset: 0xC08 */ 129 } CAN_Type, *CAN_MemMapPtr; 130 131 /** Number of instances of the FLEXCAN module. */ 132 #define CAN_INSTANCE_COUNT (2u) 133 134 /* FLEXCAN - Peripheral instance base addresses */ 135 /** Peripheral FLEXCAN0 base address */ 136 #define IP_FLEXCAN0_BASE (0x40024000u) 137 /** Peripheral FLEXCAN0 base pointer */ 138 #define IP_FLEXCAN0 ((CAN_Type *)IP_FLEXCAN0_BASE) 139 /** Peripheral FLEXCAN1 base address */ 140 #define IP_FLEXCAN1_BASE (0x40025000u) 141 /** Peripheral FLEXCAN1 base pointer */ 142 #define IP_FLEXCAN1 ((CAN_Type *)IP_FLEXCAN1_BASE) 143 /** Array initializer of FLEXCAN peripheral base addresses */ 144 #define IP_FLEXCAN_BASE_ADDRS { IP_FLEXCAN0_BASE, IP_FLEXCAN1_BASE } 145 /** Array initializer of FLEXCAN peripheral base pointers */ 146 #define IP_FLEXCAN_BASE_PTRS { IP_FLEXCAN0, IP_FLEXCAN1 } 147 148 /* ---------------------------------------------------------------------------- 149 -- FLEXCAN Register Masks 150 ---------------------------------------------------------------------------- */ 151 152 /*! 153 * @addtogroup CAN_Register_Masks FLEXCAN Register Masks 154 * @{ 155 */ 156 157 /*! @name MCR - Module Configuration Register */ 158 /*! @{ */ 159 160 #define CAN_MCR_MAXMB_MASK (0x7FU) 161 #define CAN_MCR_MAXMB_SHIFT (0U) 162 #define CAN_MCR_MAXMB_WIDTH (7U) 163 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) 164 165 #define CAN_MCR_IDAM_MASK (0x300U) 166 #define CAN_MCR_IDAM_SHIFT (8U) 167 #define CAN_MCR_IDAM_WIDTH (2U) 168 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) 169 170 #define CAN_MCR_FDEN_MASK (0x800U) 171 #define CAN_MCR_FDEN_SHIFT (11U) 172 #define CAN_MCR_FDEN_WIDTH (1U) 173 #define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK) 174 175 #define CAN_MCR_AEN_MASK (0x1000U) 176 #define CAN_MCR_AEN_SHIFT (12U) 177 #define CAN_MCR_AEN_WIDTH (1U) 178 #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) 179 180 #define CAN_MCR_LPRIOEN_MASK (0x2000U) 181 #define CAN_MCR_LPRIOEN_SHIFT (13U) 182 #define CAN_MCR_LPRIOEN_WIDTH (1U) 183 #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) 184 185 #define CAN_MCR_PNET_EN_MASK (0x4000U) 186 #define CAN_MCR_PNET_EN_SHIFT (14U) 187 #define CAN_MCR_PNET_EN_WIDTH (1U) 188 #define CAN_MCR_PNET_EN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_PNET_EN_SHIFT)) & CAN_MCR_PNET_EN_MASK) 189 190 #define CAN_MCR_DMA_MASK (0x8000U) 191 #define CAN_MCR_DMA_SHIFT (15U) 192 #define CAN_MCR_DMA_WIDTH (1U) 193 #define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK) 194 195 #define CAN_MCR_IRMQ_MASK (0x10000U) 196 #define CAN_MCR_IRMQ_SHIFT (16U) 197 #define CAN_MCR_IRMQ_WIDTH (1U) 198 #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) 199 200 #define CAN_MCR_SRXDIS_MASK (0x20000U) 201 #define CAN_MCR_SRXDIS_SHIFT (17U) 202 #define CAN_MCR_SRXDIS_WIDTH (1U) 203 #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) 204 205 #define CAN_MCR_DOZE_MASK (0x40000U) 206 #define CAN_MCR_DOZE_SHIFT (18U) 207 #define CAN_MCR_DOZE_WIDTH (1U) 208 #define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK) 209 210 #define CAN_MCR_WAKSRC_MASK (0x80000U) /* Reserved */ 211 #define CAN_MCR_WAKSRC_SHIFT (19U) 212 #define CAN_MCR_WAKSRC_WIDTH (1U) 213 #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) 214 215 #define CAN_MCR_LPMACK_MASK (0x100000U) 216 #define CAN_MCR_LPMACK_SHIFT (20U) 217 #define CAN_MCR_LPMACK_WIDTH (1U) 218 #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) 219 220 #define CAN_MCR_WRNEN_MASK (0x200000U) 221 #define CAN_MCR_WRNEN_SHIFT (21U) 222 #define CAN_MCR_WRNEN_WIDTH (1U) 223 #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) 224 225 #define CAN_MCR_SLFWAK_MASK (0x400000U) /* Reserved */ 226 #define CAN_MCR_SLFWAK_SHIFT (22U) 227 #define CAN_MCR_SLFWAK_WIDTH (1U) 228 #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) 229 230 #define CAN_MCR_SUPV_MASK (0x800000U) 231 #define CAN_MCR_SUPV_SHIFT (23U) 232 #define CAN_MCR_SUPV_WIDTH (1U) 233 #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) 234 235 #define CAN_MCR_FRZACK_MASK (0x1000000U) 236 #define CAN_MCR_FRZACK_SHIFT (24U) 237 #define CAN_MCR_FRZACK_WIDTH (1U) 238 #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) 239 240 #define CAN_MCR_SOFTRST_MASK (0x2000000U) 241 #define CAN_MCR_SOFTRST_SHIFT (25U) 242 #define CAN_MCR_SOFTRST_WIDTH (1U) 243 #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) 244 245 #define CAN_MCR_WAKMSK_MASK (0x4000000U) /* Reserved */ 246 #define CAN_MCR_WAKMSK_SHIFT (26U) 247 #define CAN_MCR_WAKMSK_WIDTH (1U) 248 #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) 249 250 #define CAN_MCR_NOTRDY_MASK (0x8000000U) 251 #define CAN_MCR_NOTRDY_SHIFT (27U) 252 #define CAN_MCR_NOTRDY_WIDTH (1U) 253 #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) 254 255 #define CAN_MCR_HALT_MASK (0x10000000U) 256 #define CAN_MCR_HALT_SHIFT (28U) 257 #define CAN_MCR_HALT_WIDTH (1U) 258 #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) 259 260 #define CAN_MCR_RFEN_MASK (0x20000000U) 261 #define CAN_MCR_RFEN_SHIFT (29U) 262 #define CAN_MCR_RFEN_WIDTH (1U) 263 #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) 264 265 #define CAN_MCR_FRZ_MASK (0x40000000U) 266 #define CAN_MCR_FRZ_SHIFT (30U) 267 #define CAN_MCR_FRZ_WIDTH (1U) 268 #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) 269 270 #define CAN_MCR_MDIS_MASK (0x80000000U) 271 #define CAN_MCR_MDIS_SHIFT (31U) 272 #define CAN_MCR_MDIS_WIDTH (1U) 273 #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) 274 /*! @} */ 275 276 /*! @name CTRL1 - Control 1 Register */ 277 /*! @{ */ 278 279 #define CAN_CTRL1_PROPSEG_MASK (0x7U) 280 #define CAN_CTRL1_PROPSEG_SHIFT (0U) 281 #define CAN_CTRL1_PROPSEG_WIDTH (3U) 282 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) 283 284 #define CAN_CTRL1_LOM_MASK (0x8U) 285 #define CAN_CTRL1_LOM_SHIFT (3U) 286 #define CAN_CTRL1_LOM_WIDTH (1U) 287 #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) 288 289 #define CAN_CTRL1_LBUF_MASK (0x10U) 290 #define CAN_CTRL1_LBUF_SHIFT (4U) 291 #define CAN_CTRL1_LBUF_WIDTH (1U) 292 #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) 293 294 #define CAN_CTRL1_TSYN_MASK (0x20U) 295 #define CAN_CTRL1_TSYN_SHIFT (5U) 296 #define CAN_CTRL1_TSYN_WIDTH (1U) 297 #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) 298 299 #define CAN_CTRL1_BOFFREC_MASK (0x40U) 300 #define CAN_CTRL1_BOFFREC_SHIFT (6U) 301 #define CAN_CTRL1_BOFFREC_WIDTH (1U) 302 #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) 303 304 #define CAN_CTRL1_SMP_MASK (0x80U) 305 #define CAN_CTRL1_SMP_SHIFT (7U) 306 #define CAN_CTRL1_SMP_WIDTH (1U) 307 #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) 308 309 #define CAN_CTRL1_RWRNMSK_MASK (0x400U) 310 #define CAN_CTRL1_RWRNMSK_SHIFT (10U) 311 #define CAN_CTRL1_RWRNMSK_WIDTH (1U) 312 #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) 313 314 #define CAN_CTRL1_TWRNMSK_MASK (0x800U) 315 #define CAN_CTRL1_TWRNMSK_SHIFT (11U) 316 #define CAN_CTRL1_TWRNMSK_WIDTH (1U) 317 #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) 318 319 #define CAN_CTRL1_LPB_MASK (0x1000U) 320 #define CAN_CTRL1_LPB_SHIFT (12U) 321 #define CAN_CTRL1_LPB_WIDTH (1U) 322 #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) 323 324 #define CAN_CTRL1_CLKSRC_MASK (0x2000U) 325 #define CAN_CTRL1_CLKSRC_SHIFT (13U) 326 #define CAN_CTRL1_CLKSRC_WIDTH (1U) 327 #define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK) 328 329 #define CAN_CTRL1_ERRMSK_MASK (0x4000U) 330 #define CAN_CTRL1_ERRMSK_SHIFT (14U) 331 #define CAN_CTRL1_ERRMSK_WIDTH (1U) 332 #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) 333 334 #define CAN_CTRL1_BOFFMSK_MASK (0x8000U) 335 #define CAN_CTRL1_BOFFMSK_SHIFT (15U) 336 #define CAN_CTRL1_BOFFMSK_WIDTH (1U) 337 #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) 338 339 #define CAN_CTRL1_PSEG2_MASK (0x70000U) 340 #define CAN_CTRL1_PSEG2_SHIFT (16U) 341 #define CAN_CTRL1_PSEG2_WIDTH (3U) 342 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) 343 344 #define CAN_CTRL1_PSEG1_MASK (0x380000U) 345 #define CAN_CTRL1_PSEG1_SHIFT (19U) 346 #define CAN_CTRL1_PSEG1_WIDTH (3U) 347 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) 348 349 #define CAN_CTRL1_RJW_MASK (0xC00000U) 350 #define CAN_CTRL1_RJW_SHIFT (22U) 351 #define CAN_CTRL1_RJW_WIDTH (2U) 352 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) 353 354 #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) 355 #define CAN_CTRL1_PRESDIV_SHIFT (24U) 356 #define CAN_CTRL1_PRESDIV_WIDTH (8U) 357 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) 358 /*! @} */ 359 360 /*! @name TIMER - Free Running Timer */ 361 /*! @{ */ 362 363 #define CAN_TIMER_TIMER_MASK (0xFFFFU) 364 #define CAN_TIMER_TIMER_SHIFT (0U) 365 #define CAN_TIMER_TIMER_WIDTH (16U) 366 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) 367 /*! @} */ 368 369 /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ 370 /*! @{ */ 371 372 #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) 373 #define CAN_RXMGMASK_MG_SHIFT (0U) 374 #define CAN_RXMGMASK_MG_WIDTH (32U) 375 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) 376 /*! @} */ 377 378 /*! @name RX14MASK - Rx 14 Mask Register */ 379 /*! @{ */ 380 381 #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) 382 #define CAN_RX14MASK_RX14M_SHIFT (0U) 383 #define CAN_RX14MASK_RX14M_WIDTH (32U) 384 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) 385 /*! @} */ 386 387 /*! @name RX15MASK - Rx 15 Mask Register */ 388 /*! @{ */ 389 390 #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) 391 #define CAN_RX15MASK_RX15M_SHIFT (0U) 392 #define CAN_RX15MASK_RX15M_WIDTH (32U) 393 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) 394 /*! @} */ 395 396 /*! @name ECR - Error Counter */ 397 /*! @{ */ 398 399 #define CAN_ECR_TXERRCNT_MASK (0xFFU) 400 #define CAN_ECR_TXERRCNT_SHIFT (0U) 401 #define CAN_ECR_TXERRCNT_WIDTH (8U) 402 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) 403 404 #define CAN_ECR_RXERRCNT_MASK (0xFF00U) 405 #define CAN_ECR_RXERRCNT_SHIFT (8U) 406 #define CAN_ECR_RXERRCNT_WIDTH (8U) 407 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) 408 409 #define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U) 410 #define CAN_ECR_TXERRCNT_FAST_SHIFT (16U) 411 #define CAN_ECR_TXERRCNT_FAST_WIDTH (8U) 412 #define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK) 413 414 #define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U) 415 #define CAN_ECR_RXERRCNT_FAST_SHIFT (24U) 416 #define CAN_ECR_RXERRCNT_FAST_WIDTH (8U) 417 #define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK) 418 /*! @} */ 419 420 /*! @name ESR1 - Error and Status 1 Register */ 421 /*! @{ */ 422 423 #define CAN_ESR1_WAKINT_MASK (0x1U) /* Reserved */ 424 #define CAN_ESR1_WAKINT_SHIFT (0U) 425 #define CAN_ESR1_WAKINT_WIDTH (1U) 426 #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) 427 428 #define CAN_ESR1_ERRINT_MASK (0x2U) 429 #define CAN_ESR1_ERRINT_SHIFT (1U) 430 #define CAN_ESR1_ERRINT_WIDTH (1U) 431 #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) 432 433 #define CAN_ESR1_BOFFINT_MASK (0x4U) 434 #define CAN_ESR1_BOFFINT_SHIFT (2U) 435 #define CAN_ESR1_BOFFINT_WIDTH (1U) 436 #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) 437 438 #define CAN_ESR1_RX_MASK (0x8U) 439 #define CAN_ESR1_RX_SHIFT (3U) 440 #define CAN_ESR1_RX_WIDTH (1U) 441 #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) 442 443 #define CAN_ESR1_FLTCONF_MASK (0x30U) 444 #define CAN_ESR1_FLTCONF_SHIFT (4U) 445 #define CAN_ESR1_FLTCONF_WIDTH (2U) 446 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) 447 448 #define CAN_ESR1_TX_MASK (0x40U) 449 #define CAN_ESR1_TX_SHIFT (6U) 450 #define CAN_ESR1_TX_WIDTH (1U) 451 #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) 452 453 #define CAN_ESR1_IDLE_MASK (0x80U) 454 #define CAN_ESR1_IDLE_SHIFT (7U) 455 #define CAN_ESR1_IDLE_WIDTH (1U) 456 #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) 457 458 #define CAN_ESR1_RXWRN_MASK (0x100U) 459 #define CAN_ESR1_RXWRN_SHIFT (8U) 460 #define CAN_ESR1_RXWRN_WIDTH (1U) 461 #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) 462 463 #define CAN_ESR1_TXWRN_MASK (0x200U) 464 #define CAN_ESR1_TXWRN_SHIFT (9U) 465 #define CAN_ESR1_TXWRN_WIDTH (1U) 466 #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) 467 468 #define CAN_ESR1_STFERR_MASK (0x400U) 469 #define CAN_ESR1_STFERR_SHIFT (10U) 470 #define CAN_ESR1_STFERR_WIDTH (1U) 471 #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) 472 473 #define CAN_ESR1_FRMERR_MASK (0x800U) 474 #define CAN_ESR1_FRMERR_SHIFT (11U) 475 #define CAN_ESR1_FRMERR_WIDTH (1U) 476 #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) 477 478 #define CAN_ESR1_CRCERR_MASK (0x1000U) 479 #define CAN_ESR1_CRCERR_SHIFT (12U) 480 #define CAN_ESR1_CRCERR_WIDTH (1U) 481 #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) 482 483 #define CAN_ESR1_ACKERR_MASK (0x2000U) 484 #define CAN_ESR1_ACKERR_SHIFT (13U) 485 #define CAN_ESR1_ACKERR_WIDTH (1U) 486 #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) 487 488 #define CAN_ESR1_BIT0ERR_MASK (0x4000U) 489 #define CAN_ESR1_BIT0ERR_SHIFT (14U) 490 #define CAN_ESR1_BIT0ERR_WIDTH (1U) 491 #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) 492 493 #define CAN_ESR1_BIT1ERR_MASK (0x8000U) 494 #define CAN_ESR1_BIT1ERR_SHIFT (15U) 495 #define CAN_ESR1_BIT1ERR_WIDTH (1U) 496 #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) 497 498 #define CAN_ESR1_RWRNINT_MASK (0x10000U) 499 #define CAN_ESR1_RWRNINT_SHIFT (16U) 500 #define CAN_ESR1_RWRNINT_WIDTH (1U) 501 #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) 502 503 #define CAN_ESR1_TWRNINT_MASK (0x20000U) 504 #define CAN_ESR1_TWRNINT_SHIFT (17U) 505 #define CAN_ESR1_TWRNINT_WIDTH (1U) 506 #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) 507 508 #define CAN_ESR1_SYNCH_MASK (0x40000U) 509 #define CAN_ESR1_SYNCH_SHIFT (18U) 510 #define CAN_ESR1_SYNCH_WIDTH (1U) 511 #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) 512 513 #define CAN_ESR1_BOFFDONEINT_MASK (0x80000U) 514 #define CAN_ESR1_BOFFDONEINT_SHIFT (19U) 515 #define CAN_ESR1_BOFFDONEINT_WIDTH (1U) 516 #define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK) 517 518 #define CAN_ESR1_ERRINT_FAST_MASK (0x100000U) 519 #define CAN_ESR1_ERRINT_FAST_SHIFT (20U) 520 #define CAN_ESR1_ERRINT_FAST_WIDTH (1U) 521 #define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK) 522 523 #define CAN_ESR1_ERROVR_MASK (0x200000U) 524 #define CAN_ESR1_ERROVR_SHIFT (21U) 525 #define CAN_ESR1_ERROVR_WIDTH (1U) 526 #define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK) 527 528 #define CAN_ESR1_STFERR_FAST_MASK (0x4000000U) 529 #define CAN_ESR1_STFERR_FAST_SHIFT (26U) 530 #define CAN_ESR1_STFERR_FAST_WIDTH (1U) 531 #define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK) 532 533 #define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U) 534 #define CAN_ESR1_FRMERR_FAST_SHIFT (27U) 535 #define CAN_ESR1_FRMERR_FAST_WIDTH (1U) 536 #define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK) 537 538 #define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U) 539 #define CAN_ESR1_CRCERR_FAST_SHIFT (28U) 540 #define CAN_ESR1_CRCERR_FAST_WIDTH (1U) 541 #define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK) 542 543 #define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) 544 #define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U) 545 #define CAN_ESR1_BIT0ERR_FAST_WIDTH (1U) 546 #define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK) 547 548 #define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) 549 #define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U) 550 #define CAN_ESR1_BIT1ERR_FAST_WIDTH (1U) 551 #define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK) 552 /*! @} */ 553 554 /*! @name IMASK2 - Interrupt Masks 2 Register */ 555 /*! @{ */ 556 557 #define CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU) 558 #define CAN_IMASK2_BUF63TO32M_SHIFT (0U) 559 #define CAN_IMASK2_BUF63TO32M_WIDTH (32U) 560 #define CAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK) 561 /*! @} */ 562 563 /*! @name IMASK1 - Interrupt Masks 1 Register */ 564 /*! @{ */ 565 566 #define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU) 567 #define CAN_IMASK1_BUF31TO0M_SHIFT (0U) 568 #define CAN_IMASK1_BUF31TO0M_WIDTH (32U) 569 #define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK) 570 /*! @} */ 571 572 /*! @name IFLAG2 - Interrupt Flags 2 Register */ 573 /*! @{ */ 574 575 #define CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU) 576 #define CAN_IFLAG2_BUF63TO32I_SHIFT (0U) 577 #define CAN_IFLAG2_BUF63TO32I_WIDTH (32U) 578 #define CAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK) 579 /*! @} */ 580 581 /*! @name IFLAG1 - Interrupt Flags 1 Register */ 582 /*! @{ */ 583 584 #define CAN_IFLAG1_BUF0I_MASK (0x1U) 585 #define CAN_IFLAG1_BUF0I_SHIFT (0U) 586 #define CAN_IFLAG1_BUF0I_WIDTH (1U) 587 #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) 588 589 #define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) 590 #define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) 591 #define CAN_IFLAG1_BUF4TO1I_WIDTH (4U) 592 #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) 593 594 #define CAN_IFLAG1_BUF5I_MASK (0x20U) 595 #define CAN_IFLAG1_BUF5I_SHIFT (5U) 596 #define CAN_IFLAG1_BUF5I_WIDTH (1U) 597 #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) 598 599 #define CAN_IFLAG1_BUF6I_MASK (0x40U) 600 #define CAN_IFLAG1_BUF6I_SHIFT (6U) 601 #define CAN_IFLAG1_BUF6I_WIDTH (1U) 602 #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) 603 604 #define CAN_IFLAG1_BUF7I_MASK (0x80U) 605 #define CAN_IFLAG1_BUF7I_SHIFT (7U) 606 #define CAN_IFLAG1_BUF7I_WIDTH (1U) 607 #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) 608 609 #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) 610 #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) 611 #define CAN_IFLAG1_BUF31TO8I_WIDTH (24U) 612 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) 613 /*! @} */ 614 615 /*! @name CTRL2 - Control 2 Register */ 616 /*! @{ */ 617 618 #define CAN_CTRL2_EDFLTDIS_MASK (0x800U) 619 #define CAN_CTRL2_EDFLTDIS_SHIFT (11U) 620 #define CAN_CTRL2_EDFLTDIS_WIDTH (1U) 621 #define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK) 622 623 #define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U) 624 #define CAN_CTRL2_ISOCANFDEN_SHIFT (12U) 625 #define CAN_CTRL2_ISOCANFDEN_WIDTH (1U) 626 #define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK) 627 628 #define CAN_CTRL2_PREXCEN_MASK (0x4000U) 629 #define CAN_CTRL2_PREXCEN_SHIFT (14U) 630 #define CAN_CTRL2_PREXCEN_WIDTH (1U) 631 #define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK) 632 633 #define CAN_CTRL2_TIMER_SRC_MASK (0x8000U) 634 #define CAN_CTRL2_TIMER_SRC_SHIFT (15U) 635 #define CAN_CTRL2_TIMER_SRC_WIDTH (1U) 636 #define CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK) 637 638 #define CAN_CTRL2_EACEN_MASK (0x10000U) 639 #define CAN_CTRL2_EACEN_SHIFT (16U) 640 #define CAN_CTRL2_EACEN_WIDTH (1U) 641 #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) 642 643 #define CAN_CTRL2_RRS_MASK (0x20000U) 644 #define CAN_CTRL2_RRS_SHIFT (17U) 645 #define CAN_CTRL2_RRS_WIDTH (1U) 646 #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) 647 648 #define CAN_CTRL2_MRP_MASK (0x40000U) 649 #define CAN_CTRL2_MRP_SHIFT (18U) 650 #define CAN_CTRL2_MRP_WIDTH (1U) 651 #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) 652 653 #define CAN_CTRL2_TASD_MASK (0xF80000U) 654 #define CAN_CTRL2_TASD_SHIFT (19U) 655 #define CAN_CTRL2_TASD_WIDTH (5U) 656 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) 657 658 #define CAN_CTRL2_RFFN_MASK (0xF000000U) 659 #define CAN_CTRL2_RFFN_SHIFT (24U) 660 #define CAN_CTRL2_RFFN_WIDTH (4U) 661 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) 662 663 #define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U) 664 #define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U) 665 #define CAN_CTRL2_BOFFDONEMSK_WIDTH (1U) 666 #define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK) 667 668 #define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) 669 #define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U) 670 #define CAN_CTRL2_ERRMSK_FAST_WIDTH (1U) 671 #define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK) 672 /*! @} */ 673 674 /*! @name ESR2 - Error and Status 2 Register */ 675 /*! @{ */ 676 677 #define CAN_ESR2_IMB_MASK (0x2000U) 678 #define CAN_ESR2_IMB_SHIFT (13U) 679 #define CAN_ESR2_IMB_WIDTH (1U) 680 #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) 681 682 #define CAN_ESR2_VPS_MASK (0x4000U) 683 #define CAN_ESR2_VPS_SHIFT (14U) 684 #define CAN_ESR2_VPS_WIDTH (1U) 685 #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) 686 687 #define CAN_ESR2_LPTM_MASK (0x7F0000U) 688 #define CAN_ESR2_LPTM_SHIFT (16U) 689 #define CAN_ESR2_LPTM_WIDTH (7U) 690 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) 691 /*! @} */ 692 693 /*! @name CRCR - CRC Register */ 694 /*! @{ */ 695 696 #define CAN_CRCR_TXCRC_MASK (0x7FFFU) 697 #define CAN_CRCR_TXCRC_SHIFT (0U) 698 #define CAN_CRCR_TXCRC_WIDTH (15U) 699 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) 700 701 #define CAN_CRCR_MBCRC_MASK (0x7F0000U) 702 #define CAN_CRCR_MBCRC_SHIFT (16U) 703 #define CAN_CRCR_MBCRC_WIDTH (7U) 704 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) 705 /*! @} */ 706 707 /*! @name RXFGMASK - Rx FIFO Global Mask Register */ 708 /*! @{ */ 709 710 #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) 711 #define CAN_RXFGMASK_FGM_SHIFT (0U) 712 #define CAN_RXFGMASK_FGM_WIDTH (32U) 713 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) 714 /*! @} */ 715 716 /*! @name RXFIR - Rx FIFO Information Register */ 717 /*! @{ */ 718 719 #define CAN_RXFIR_IDHIT_MASK (0x1FFU) 720 #define CAN_RXFIR_IDHIT_SHIFT (0U) 721 #define CAN_RXFIR_IDHIT_WIDTH (9U) 722 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) 723 /*! @} */ 724 725 /*! @name CBT - CAN Bit Timing Register */ 726 /*! @{ */ 727 728 #define CAN_CBT_EPSEG2_MASK (0x1FU) 729 #define CAN_CBT_EPSEG2_SHIFT (0U) 730 #define CAN_CBT_EPSEG2_WIDTH (5U) 731 #define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK) 732 733 #define CAN_CBT_EPSEG1_MASK (0x3E0U) 734 #define CAN_CBT_EPSEG1_SHIFT (5U) 735 #define CAN_CBT_EPSEG1_WIDTH (5U) 736 #define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK) 737 738 #define CAN_CBT_EPROPSEG_MASK (0xFC00U) 739 #define CAN_CBT_EPROPSEG_SHIFT (10U) 740 #define CAN_CBT_EPROPSEG_WIDTH (6U) 741 #define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK) 742 743 #define CAN_CBT_ERJW_MASK (0x1F0000U) 744 #define CAN_CBT_ERJW_SHIFT (16U) 745 #define CAN_CBT_ERJW_WIDTH (5U) 746 #define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK) 747 748 #define CAN_CBT_EPRESDIV_MASK (0x7FE00000U) 749 #define CAN_CBT_EPRESDIV_SHIFT (21U) 750 #define CAN_CBT_EPRESDIV_WIDTH (10U) 751 #define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK) 752 753 #define CAN_CBT_BTF_MASK (0x80000000U) 754 #define CAN_CBT_BTF_SHIFT (31U) 755 #define CAN_CBT_BTF_WIDTH (1U) 756 #define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK) 757 /*! @} */ 758 759 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 31 CS Register */ 760 /*! @{ */ 761 762 #define CAN_CS_TIME_STAMP_MASK (0xFFFFU) 763 #define CAN_CS_TIME_STAMP_SHIFT (0U) 764 #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) 765 766 #define CAN_CS_DLC_MASK (0xF0000U) 767 #define CAN_CS_DLC_SHIFT (16U) 768 #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) 769 770 #define CAN_CS_RTR_MASK (0x100000U) 771 #define CAN_CS_RTR_SHIFT (20U) 772 #define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) 773 774 #define CAN_CS_IDE_MASK (0x200000U) 775 #define CAN_CS_IDE_SHIFT (21U) 776 #define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) 777 778 #define CAN_CS_SRR_MASK (0x400000U) 779 #define CAN_CS_SRR_SHIFT (22U) 780 #define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) 781 782 #define CAN_CS_CODE_MASK (0xF000000U) 783 #define CAN_CS_CODE_SHIFT (24U) 784 #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) 785 786 #define CAN_CS_ESI_MASK (0x20000000U) 787 #define CAN_CS_ESI_SHIFT (29U) 788 #define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK) 789 790 #define CAN_CS_BRS_MASK (0x40000000U) 791 #define CAN_CS_BRS_SHIFT (30U) 792 #define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK) 793 794 #define CAN_CS_EDL_MASK (0x80000000U) 795 #define CAN_CS_EDL_SHIFT (31U) 796 #define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK) 797 /*! @} */ 798 799 /* The count of CAN_CS */ 800 #define CAN_CS_COUNT (64U) 801 802 /*! @name ID - Message Buffer 0 ID Register..Message Buffer 31 ID Register */ 803 /*! @{ */ 804 805 #define CAN_ID_EXT_MASK (0x3FFFFU) 806 #define CAN_ID_EXT_SHIFT (0U) 807 #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) 808 809 #define CAN_ID_STD_MASK (0x1FFC0000U) 810 #define CAN_ID_STD_SHIFT (18U) 811 #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) 812 813 #define CAN_ID_PRIO_MASK (0xE0000000U) 814 #define CAN_ID_PRIO_SHIFT (29U) 815 #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) 816 /*! @} */ 817 818 /* The count of CAN_ID */ 819 #define CAN_ID_COUNT (64U) 820 821 /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 31 WORD0 Register */ 822 /*! @{ */ 823 824 #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) 825 #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) 826 #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) 827 828 #define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) 829 #define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) 830 #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) 831 832 #define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) 833 #define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) 834 #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) 835 836 #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) 837 #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) 838 #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) 839 /*! @} */ 840 841 /* The count of CAN_WORD0 */ 842 #define CAN_WORD0_COUNT (64U) 843 844 /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 31 WORD1 Register */ 845 /*! @{ */ 846 847 #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) 848 #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) 849 #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) 850 851 #define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) 852 #define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) 853 #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) 854 855 #define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) 856 #define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) 857 #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) 858 859 #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) 860 #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) 861 #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) 862 /*! @} */ 863 864 /* The count of CAN_WORD1 */ 865 #define CAN_WORD1_COUNT (64U) 866 867 /*! @name RXIMR - Rx Individual Mask Registers */ 868 /*! @{ */ 869 870 #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) 871 #define CAN_RXIMR_MI_SHIFT (0U) 872 #define CAN_RXIMR_MI_WIDTH (32U) 873 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) 874 /*! @} */ 875 876 /*! @name CTRL1_PN - Pretended Networking Control 1 Register */ 877 /*! @{ */ 878 879 #define CAN_CTRL1_PN_FCS_MASK (0x3U) 880 #define CAN_CTRL1_PN_FCS_SHIFT (0U) 881 #define CAN_CTRL1_PN_FCS_WIDTH (2U) 882 #define CAN_CTRL1_PN_FCS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_FCS_SHIFT)) & CAN_CTRL1_PN_FCS_MASK) 883 884 #define CAN_CTRL1_PN_IDFS_MASK (0xCU) 885 #define CAN_CTRL1_PN_IDFS_SHIFT (2U) 886 #define CAN_CTRL1_PN_IDFS_WIDTH (2U) 887 #define CAN_CTRL1_PN_IDFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_IDFS_SHIFT)) & CAN_CTRL1_PN_IDFS_MASK) 888 889 #define CAN_CTRL1_PN_PLFS_MASK (0x30U) 890 #define CAN_CTRL1_PN_PLFS_SHIFT (4U) 891 #define CAN_CTRL1_PN_PLFS_WIDTH (2U) 892 #define CAN_CTRL1_PN_PLFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_PLFS_SHIFT)) & CAN_CTRL1_PN_PLFS_MASK) 893 894 #define CAN_CTRL1_PN_NMATCH_MASK (0xFF00U) 895 #define CAN_CTRL1_PN_NMATCH_SHIFT (8U) 896 #define CAN_CTRL1_PN_NMATCH_WIDTH (8U) 897 #define CAN_CTRL1_PN_NMATCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_NMATCH_SHIFT)) & CAN_CTRL1_PN_NMATCH_MASK) 898 899 #define CAN_CTRL1_PN_WUMF_MSK_MASK (0x10000U) 900 #define CAN_CTRL1_PN_WUMF_MSK_SHIFT (16U) 901 #define CAN_CTRL1_PN_WUMF_MSK_WIDTH (1U) 902 #define CAN_CTRL1_PN_WUMF_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WUMF_MSK_SHIFT)) & CAN_CTRL1_PN_WUMF_MSK_MASK) 903 904 #define CAN_CTRL1_PN_WTOF_MSK_MASK (0x20000U) 905 #define CAN_CTRL1_PN_WTOF_MSK_SHIFT (17U) 906 #define CAN_CTRL1_PN_WTOF_MSK_WIDTH (1U) 907 #define CAN_CTRL1_PN_WTOF_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WTOF_MSK_SHIFT)) & CAN_CTRL1_PN_WTOF_MSK_MASK) 908 /*! @} */ 909 910 /*! @name CTRL2_PN - Pretended Networking Control 2 Register */ 911 /*! @{ */ 912 913 #define CAN_CTRL2_PN_MATCHTO_MASK (0xFFFFU) 914 #define CAN_CTRL2_PN_MATCHTO_SHIFT (0U) 915 #define CAN_CTRL2_PN_MATCHTO_WIDTH (16U) 916 #define CAN_CTRL2_PN_MATCHTO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PN_MATCHTO_SHIFT)) & CAN_CTRL2_PN_MATCHTO_MASK) 917 /*! @} */ 918 919 /*! @name WU_MTC - Pretended Networking Wake Up Match Register */ 920 /*! @{ */ 921 922 #define CAN_WU_MTC_MCOUNTER_MASK (0xFF00U) 923 #define CAN_WU_MTC_MCOUNTER_SHIFT (8U) 924 #define CAN_WU_MTC_MCOUNTER_WIDTH (8U) 925 #define CAN_WU_MTC_MCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_MCOUNTER_SHIFT)) & CAN_WU_MTC_MCOUNTER_MASK) 926 927 #define CAN_WU_MTC_WUMF_MASK (0x10000U) 928 #define CAN_WU_MTC_WUMF_SHIFT (16U) 929 #define CAN_WU_MTC_WUMF_WIDTH (1U) 930 #define CAN_WU_MTC_WUMF(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WUMF_SHIFT)) & CAN_WU_MTC_WUMF_MASK) 931 932 #define CAN_WU_MTC_WTOF_MASK (0x20000U) 933 #define CAN_WU_MTC_WTOF_SHIFT (17U) 934 #define CAN_WU_MTC_WTOF_WIDTH (1U) 935 #define CAN_WU_MTC_WTOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WTOF_SHIFT)) & CAN_WU_MTC_WTOF_MASK) 936 /*! @} */ 937 938 /*! @name FLT_ID1 - Pretended Networking ID Filter 1 Register */ 939 /*! @{ */ 940 941 #define CAN_FLT_ID1_FLT_ID1_MASK (0x1FFFFFFFU) 942 #define CAN_FLT_ID1_FLT_ID1_SHIFT (0U) 943 #define CAN_FLT_ID1_FLT_ID1_WIDTH (29U) 944 #define CAN_FLT_ID1_FLT_ID1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_ID1_SHIFT)) & CAN_FLT_ID1_FLT_ID1_MASK) 945 946 #define CAN_FLT_ID1_FLT_RTR_MASK (0x20000000U) 947 #define CAN_FLT_ID1_FLT_RTR_SHIFT (29U) 948 #define CAN_FLT_ID1_FLT_RTR_WIDTH (1U) 949 #define CAN_FLT_ID1_FLT_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_RTR_SHIFT)) & CAN_FLT_ID1_FLT_RTR_MASK) 950 951 #define CAN_FLT_ID1_FLT_IDE_MASK (0x40000000U) 952 #define CAN_FLT_ID1_FLT_IDE_SHIFT (30U) 953 #define CAN_FLT_ID1_FLT_IDE_WIDTH (1U) 954 #define CAN_FLT_ID1_FLT_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_IDE_SHIFT)) & CAN_FLT_ID1_FLT_IDE_MASK) 955 /*! @} */ 956 957 /*! @name FLT_DLC - Pretended Networking DLC Filter Register */ 958 /*! @{ */ 959 960 #define CAN_FLT_DLC_FLT_DLC_HI_MASK (0xFU) 961 #define CAN_FLT_DLC_FLT_DLC_HI_SHIFT (0U) 962 #define CAN_FLT_DLC_FLT_DLC_HI_WIDTH (4U) 963 #define CAN_FLT_DLC_FLT_DLC_HI(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_HI_SHIFT)) & CAN_FLT_DLC_FLT_DLC_HI_MASK) 964 965 #define CAN_FLT_DLC_FLT_DLC_LO_MASK (0xF0000U) 966 #define CAN_FLT_DLC_FLT_DLC_LO_SHIFT (16U) 967 #define CAN_FLT_DLC_FLT_DLC_LO_WIDTH (4U) 968 #define CAN_FLT_DLC_FLT_DLC_LO(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_LO_SHIFT)) & CAN_FLT_DLC_FLT_DLC_LO_MASK) 969 /*! @} */ 970 971 /*! @name PL1_LO - Pretended Networking Payload Low Filter 1 Register */ 972 /*! @{ */ 973 974 #define CAN_PL1_LO_Data_byte_3_MASK (0xFFU) 975 #define CAN_PL1_LO_Data_byte_3_SHIFT (0U) 976 #define CAN_PL1_LO_Data_byte_3_WIDTH (8U) 977 #define CAN_PL1_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_3_SHIFT)) & CAN_PL1_LO_Data_byte_3_MASK) 978 979 #define CAN_PL1_LO_Data_byte_2_MASK (0xFF00U) 980 #define CAN_PL1_LO_Data_byte_2_SHIFT (8U) 981 #define CAN_PL1_LO_Data_byte_2_WIDTH (8U) 982 #define CAN_PL1_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_2_SHIFT)) & CAN_PL1_LO_Data_byte_2_MASK) 983 984 #define CAN_PL1_LO_Data_byte_1_MASK (0xFF0000U) 985 #define CAN_PL1_LO_Data_byte_1_SHIFT (16U) 986 #define CAN_PL1_LO_Data_byte_1_WIDTH (8U) 987 #define CAN_PL1_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_1_SHIFT)) & CAN_PL1_LO_Data_byte_1_MASK) 988 989 #define CAN_PL1_LO_Data_byte_0_MASK (0xFF000000U) 990 #define CAN_PL1_LO_Data_byte_0_SHIFT (24U) 991 #define CAN_PL1_LO_Data_byte_0_WIDTH (8U) 992 #define CAN_PL1_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_0_SHIFT)) & CAN_PL1_LO_Data_byte_0_MASK) 993 /*! @} */ 994 995 /*! @name PL1_HI - Pretended Networking Payload High Filter 1 Register */ 996 /*! @{ */ 997 998 #define CAN_PL1_HI_Data_byte_7_MASK (0xFFU) 999 #define CAN_PL1_HI_Data_byte_7_SHIFT (0U) 1000 #define CAN_PL1_HI_Data_byte_7_WIDTH (8U) 1001 #define CAN_PL1_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_7_SHIFT)) & CAN_PL1_HI_Data_byte_7_MASK) 1002 1003 #define CAN_PL1_HI_Data_byte_6_MASK (0xFF00U) 1004 #define CAN_PL1_HI_Data_byte_6_SHIFT (8U) 1005 #define CAN_PL1_HI_Data_byte_6_WIDTH (8U) 1006 #define CAN_PL1_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_6_SHIFT)) & CAN_PL1_HI_Data_byte_6_MASK) 1007 1008 #define CAN_PL1_HI_Data_byte_5_MASK (0xFF0000U) 1009 #define CAN_PL1_HI_Data_byte_5_SHIFT (16U) 1010 #define CAN_PL1_HI_Data_byte_5_WIDTH (8U) 1011 #define CAN_PL1_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_5_SHIFT)) & CAN_PL1_HI_Data_byte_5_MASK) 1012 1013 #define CAN_PL1_HI_Data_byte_4_MASK (0xFF000000U) 1014 #define CAN_PL1_HI_Data_byte_4_SHIFT (24U) 1015 #define CAN_PL1_HI_Data_byte_4_WIDTH (8U) 1016 #define CAN_PL1_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_4_SHIFT)) & CAN_PL1_HI_Data_byte_4_MASK) 1017 /*! @} */ 1018 1019 /*! @name FLT_ID2_IDMASK - Pretended Networking ID Filter 2 Register / ID Mask Register */ 1020 /*! @{ */ 1021 1022 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK (0x1FFFFFFFU) 1023 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT (0U) 1024 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_WIDTH (29U) 1025 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT)) & CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK) 1026 1027 #define CAN_FLT_ID2_IDMASK_RTR_MSK_MASK (0x20000000U) 1028 #define CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT (29U) 1029 #define CAN_FLT_ID2_IDMASK_RTR_MSK_WIDTH (1U) 1030 #define CAN_FLT_ID2_IDMASK_RTR_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_RTR_MSK_MASK) 1031 1032 #define CAN_FLT_ID2_IDMASK_IDE_MSK_MASK (0x40000000U) 1033 #define CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT (30U) 1034 #define CAN_FLT_ID2_IDMASK_IDE_MSK_WIDTH (1U) 1035 #define CAN_FLT_ID2_IDMASK_IDE_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_IDE_MSK_MASK) 1036 /*! @} */ 1037 1038 /*! @name PL2_PLMASK_LO - Pretended Networking Payload Low Filter 2 Register / Payload Low Mask register */ 1039 /*! @{ */ 1040 1041 #define CAN_PL2_PLMASK_LO_Data_byte_3_MASK (0xFFU) 1042 #define CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT (0U) 1043 #define CAN_PL2_PLMASK_LO_Data_byte_3_WIDTH (8U) 1044 #define CAN_PL2_PLMASK_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_3_MASK) 1045 1046 #define CAN_PL2_PLMASK_LO_Data_byte_2_MASK (0xFF00U) 1047 #define CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT (8U) 1048 #define CAN_PL2_PLMASK_LO_Data_byte_2_WIDTH (8U) 1049 #define CAN_PL2_PLMASK_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_2_MASK) 1050 1051 #define CAN_PL2_PLMASK_LO_Data_byte_1_MASK (0xFF0000U) 1052 #define CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT (16U) 1053 #define CAN_PL2_PLMASK_LO_Data_byte_1_WIDTH (8U) 1054 #define CAN_PL2_PLMASK_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_1_MASK) 1055 1056 #define CAN_PL2_PLMASK_LO_Data_byte_0_MASK (0xFF000000U) 1057 #define CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT (24U) 1058 #define CAN_PL2_PLMASK_LO_Data_byte_0_WIDTH (8U) 1059 #define CAN_PL2_PLMASK_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_0_MASK) 1060 /*! @} */ 1061 1062 /*! @name PL2_PLMASK_HI - Pretended Networking Payload High Filter 2 low order bits / Payload High Mask register */ 1063 /*! @{ */ 1064 1065 #define CAN_PL2_PLMASK_HI_Data_byte_7_MASK (0xFFU) 1066 #define CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT (0U) 1067 #define CAN_PL2_PLMASK_HI_Data_byte_7_WIDTH (8U) 1068 #define CAN_PL2_PLMASK_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_7_MASK) 1069 1070 #define CAN_PL2_PLMASK_HI_Data_byte_6_MASK (0xFF00U) 1071 #define CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT (8U) 1072 #define CAN_PL2_PLMASK_HI_Data_byte_6_WIDTH (8U) 1073 #define CAN_PL2_PLMASK_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_6_MASK) 1074 1075 #define CAN_PL2_PLMASK_HI_Data_byte_5_MASK (0xFF0000U) 1076 #define CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT (16U) 1077 #define CAN_PL2_PLMASK_HI_Data_byte_5_WIDTH (8U) 1078 #define CAN_PL2_PLMASK_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_5_MASK) 1079 1080 #define CAN_PL2_PLMASK_HI_Data_byte_4_MASK (0xFF000000U) 1081 #define CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT (24U) 1082 #define CAN_PL2_PLMASK_HI_Data_byte_4_WIDTH (8U) 1083 #define CAN_PL2_PLMASK_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_4_MASK) 1084 /*! @} */ 1085 1086 /*! @name WMBn_CS - Wake Up Message Buffer register for C/S */ 1087 /*! @{ */ 1088 1089 #define CAN_WMBn_CS_DLC_MASK (0xF0000U) 1090 #define CAN_WMBn_CS_DLC_SHIFT (16U) 1091 #define CAN_WMBn_CS_DLC_WIDTH (4U) 1092 #define CAN_WMBn_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_CS_DLC_SHIFT)) & CAN_WMBn_CS_DLC_MASK) 1093 1094 #define CAN_WMBn_CS_RTR_MASK (0x100000U) 1095 #define CAN_WMBn_CS_RTR_SHIFT (20U) 1096 #define CAN_WMBn_CS_RTR_WIDTH (1U) 1097 #define CAN_WMBn_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_CS_RTR_SHIFT)) & CAN_WMBn_CS_RTR_MASK) 1098 1099 #define CAN_WMBn_CS_IDE_MASK (0x200000U) 1100 #define CAN_WMBn_CS_IDE_SHIFT (21U) 1101 #define CAN_WMBn_CS_IDE_WIDTH (1U) 1102 #define CAN_WMBn_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_CS_IDE_SHIFT)) & CAN_WMBn_CS_IDE_MASK) 1103 1104 #define CAN_WMBn_CS_SRR_MASK (0x400000U) 1105 #define CAN_WMBn_CS_SRR_SHIFT (22U) 1106 #define CAN_WMBn_CS_SRR_WIDTH (1U) 1107 #define CAN_WMBn_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_CS_SRR_SHIFT)) & CAN_WMBn_CS_SRR_MASK) 1108 /*! @} */ 1109 1110 /*! @name WMBn_ID - Wake Up Message Buffer Register for ID */ 1111 /*! @{ */ 1112 1113 #define CAN_WMBn_ID_ID_MASK (0x1FFFFFFFU) 1114 #define CAN_WMBn_ID_ID_SHIFT (0U) 1115 #define CAN_WMBn_ID_ID_WIDTH (29U) 1116 #define CAN_WMBn_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_ID_ID_SHIFT)) & CAN_WMBn_ID_ID_MASK) 1117 /*! @} */ 1118 1119 /*! @name WMBn_D03 - Wake Up Message Buffer Register for Data 0-3 */ 1120 /*! @{ */ 1121 1122 #define CAN_WMBn_D03_Data_byte_3_MASK (0xFFU) 1123 #define CAN_WMBn_D03_Data_byte_3_SHIFT (0U) 1124 #define CAN_WMBn_D03_Data_byte_3_WIDTH (8U) 1125 #define CAN_WMBn_D03_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_D03_Data_byte_3_SHIFT)) & CAN_WMBn_D03_Data_byte_3_MASK) 1126 1127 #define CAN_WMBn_D03_Data_byte_2_MASK (0xFF00U) 1128 #define CAN_WMBn_D03_Data_byte_2_SHIFT (8U) 1129 #define CAN_WMBn_D03_Data_byte_2_WIDTH (8U) 1130 #define CAN_WMBn_D03_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_D03_Data_byte_2_SHIFT)) & CAN_WMBn_D03_Data_byte_2_MASK) 1131 1132 #define CAN_WMBn_D03_Data_byte_1_MASK (0xFF0000U) 1133 #define CAN_WMBn_D03_Data_byte_1_SHIFT (16U) 1134 #define CAN_WMBn_D03_Data_byte_1_WIDTH (8U) 1135 #define CAN_WMBn_D03_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_D03_Data_byte_1_SHIFT)) & CAN_WMBn_D03_Data_byte_1_MASK) 1136 1137 #define CAN_WMBn_D03_Data_byte_0_MASK (0xFF000000U) 1138 #define CAN_WMBn_D03_Data_byte_0_SHIFT (24U) 1139 #define CAN_WMBn_D03_Data_byte_0_WIDTH (8U) 1140 #define CAN_WMBn_D03_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_D03_Data_byte_0_SHIFT)) & CAN_WMBn_D03_Data_byte_0_MASK) 1141 /*! @} */ 1142 1143 /*! @name WMBn_D47 - Wake Up Message Buffer Register Data 4-7 */ 1144 /*! @{ */ 1145 1146 #define CAN_WMBn_D47_Data_byte_7_MASK (0xFFU) 1147 #define CAN_WMBn_D47_Data_byte_7_SHIFT (0U) 1148 #define CAN_WMBn_D47_Data_byte_7_WIDTH (8U) 1149 #define CAN_WMBn_D47_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_D47_Data_byte_7_SHIFT)) & CAN_WMBn_D47_Data_byte_7_MASK) 1150 1151 #define CAN_WMBn_D47_Data_byte_6_MASK (0xFF00U) 1152 #define CAN_WMBn_D47_Data_byte_6_SHIFT (8U) 1153 #define CAN_WMBn_D47_Data_byte_6_WIDTH (8U) 1154 #define CAN_WMBn_D47_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_D47_Data_byte_6_SHIFT)) & CAN_WMBn_D47_Data_byte_6_MASK) 1155 1156 #define CAN_WMBn_D47_Data_byte_5_MASK (0xFF0000U) 1157 #define CAN_WMBn_D47_Data_byte_5_SHIFT (16U) 1158 #define CAN_WMBn_D47_Data_byte_5_WIDTH (8U) 1159 #define CAN_WMBn_D47_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_D47_Data_byte_5_SHIFT)) & CAN_WMBn_D47_Data_byte_5_MASK) 1160 1161 #define CAN_WMBn_D47_Data_byte_4_MASK (0xFF000000U) 1162 #define CAN_WMBn_D47_Data_byte_4_SHIFT (24U) 1163 #define CAN_WMBn_D47_Data_byte_4_WIDTH (8U) 1164 #define CAN_WMBn_D47_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_D47_Data_byte_4_SHIFT)) & CAN_WMBn_D47_Data_byte_4_MASK) 1165 /*! @} */ 1166 1167 /*! @name FDCTRL - CAN FD Control Register */ 1168 /*! @{ */ 1169 1170 #define CAN_FDCTRL_TDCVAL_MASK (0x3FU) 1171 #define CAN_FDCTRL_TDCVAL_SHIFT (0U) 1172 #define CAN_FDCTRL_TDCVAL_WIDTH (6U) 1173 #define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK) 1174 1175 #define CAN_FDCTRL_TDCOFF_MASK (0x1F00U) 1176 #define CAN_FDCTRL_TDCOFF_SHIFT (8U) 1177 #define CAN_FDCTRL_TDCOFF_WIDTH (5U) 1178 #define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK) 1179 1180 #define CAN_FDCTRL_TDCFAIL_MASK (0x4000U) 1181 #define CAN_FDCTRL_TDCFAIL_SHIFT (14U) 1182 #define CAN_FDCTRL_TDCFAIL_WIDTH (1U) 1183 #define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK) 1184 1185 #define CAN_FDCTRL_TDCEN_MASK (0x8000U) 1186 #define CAN_FDCTRL_TDCEN_SHIFT (15U) 1187 #define CAN_FDCTRL_TDCEN_WIDTH (1U) 1188 #define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK) 1189 1190 #define CAN_FDCTRL_MBDSR0_MASK (0x30000U) 1191 #define CAN_FDCTRL_MBDSR0_SHIFT (16U) 1192 #define CAN_FDCTRL_MBDSR0_WIDTH (2U) 1193 #define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK) 1194 1195 #define CAN_FDCTRL_MBDSR1_MASK (0x180000U) 1196 #define CAN_FDCTRL_MBDSR1_SHIFT (19U) 1197 #define CAN_FDCTRL_MBDSR1_WIDTH (2U) 1198 #define CAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK) 1199 1200 #define CAN_FDCTRL_FDRATE_MASK (0x80000000U) 1201 #define CAN_FDCTRL_FDRATE_SHIFT (31U) 1202 #define CAN_FDCTRL_FDRATE_WIDTH (1U) 1203 #define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK) 1204 /*! @} */ 1205 1206 /*! @name FDCBT - CAN FD Bit Timing Register */ 1207 /*! @{ */ 1208 1209 #define CAN_FDCBT_FPSEG2_MASK (0x7U) 1210 #define CAN_FDCBT_FPSEG2_SHIFT (0U) 1211 #define CAN_FDCBT_FPSEG2_WIDTH (3U) 1212 #define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK) 1213 1214 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) 1215 #define CAN_FDCBT_FPSEG1_SHIFT (5U) 1216 #define CAN_FDCBT_FPSEG1_WIDTH (3U) 1217 #define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK) 1218 1219 #define CAN_FDCBT_FPROPSEG_MASK (0x7C00U) 1220 #define CAN_FDCBT_FPROPSEG_SHIFT (10U) 1221 #define CAN_FDCBT_FPROPSEG_WIDTH (5U) 1222 #define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK) 1223 1224 #define CAN_FDCBT_FRJW_MASK (0x70000U) 1225 #define CAN_FDCBT_FRJW_SHIFT (16U) 1226 #define CAN_FDCBT_FRJW_WIDTH (3U) 1227 #define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK) 1228 1229 #define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U) 1230 #define CAN_FDCBT_FPRESDIV_SHIFT (20U) 1231 #define CAN_FDCBT_FPRESDIV_WIDTH (10U) 1232 #define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK) 1233 /*! @} */ 1234 1235 /*! @name FDCRC - CAN FD CRC Register */ 1236 /*! @{ */ 1237 1238 #define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU) 1239 #define CAN_FDCRC_FD_TXCRC_SHIFT (0U) 1240 #define CAN_FDCRC_FD_TXCRC_WIDTH (21U) 1241 #define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK) 1242 1243 #define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U) 1244 #define CAN_FDCRC_FD_MBCRC_SHIFT (24U) 1245 #define CAN_FDCRC_FD_MBCRC_WIDTH (7U) 1246 #define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK) 1247 /*! @} */ 1248 1249 /*! 1250 * @} 1251 */ /* end of group CAN_Register_Masks */ 1252 1253 /*! 1254 * @} 1255 */ /* end of group CAN_Peripheral_Access_Layer */ 1256 1257 #endif /* #if !defined(S32K144W_FLEXCAN_H_) */ 1258
