1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K142_EIM.h 10 * @version 1.1 11 * @date 2022-02-01 12 * @brief Peripheral Access Layer for S32K142_EIM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K142_EIM_H_) /* Check if memory map has not been already included */ 58 #define S32K142_EIM_H_ 59 60 #include "S32K142_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- EIM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** EIM - Size of Registers Arrays */ 72 #define EIM_EICHDn_COUNT 2u 73 74 /** EIM - Register Layout Typedef */ 75 typedef struct { 76 __IO uint32_t EIMCR; /**< Error Injection Module Configuration Register, offset: 0x0 */ 77 __IO uint32_t EICHEN; /**< Error Injection Channel Enable register, offset: 0x4 */ 78 uint8_t RESERVED_0[248]; 79 struct { /* offset: 0x100, array step: 0x100 */ 80 __IO uint32_t WORD0; /**< Error Injection Channel Descriptor n, Word0, array offset: 0x100, array step: 0x100 */ 81 __IO uint32_t WORD1; /**< Error Injection Channel Descriptor n, Word1, array offset: 0x104, array step: 0x100 */ 82 uint8_t RESERVED_0[248]; 83 } EICHDn[EIM_EICHDn_COUNT]; 84 } EIM_Type, *EIM_MemMapPtr; 85 86 /** Number of instances of the EIM module. */ 87 #define EIM_INSTANCE_COUNT (1u) 88 89 /* EIM - Peripheral instance base addresses */ 90 /** Peripheral EIM base address */ 91 #define IP_EIM_BASE (0x40019000u) 92 /** Peripheral EIM base pointer */ 93 #define IP_EIM ((EIM_Type *)IP_EIM_BASE) 94 /** Array initializer of EIM peripheral base addresses */ 95 #define IP_EIM_BASE_ADDRS { IP_EIM_BASE } 96 /** Array initializer of EIM peripheral base pointers */ 97 #define IP_EIM_BASE_PTRS { IP_EIM } 98 99 /* ---------------------------------------------------------------------------- 100 -- EIM Register Masks 101 ---------------------------------------------------------------------------- */ 102 103 /*! 104 * @addtogroup EIM_Register_Masks EIM Register Masks 105 * @{ 106 */ 107 108 /*! @name EIMCR - Error Injection Module Configuration Register */ 109 /*! @{ */ 110 111 #define EIM_EIMCR_GEIEN_MASK (0x1U) 112 #define EIM_EIMCR_GEIEN_SHIFT (0U) 113 #define EIM_EIMCR_GEIEN_WIDTH (1U) 114 #define EIM_EIMCR_GEIEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EIMCR_GEIEN_SHIFT)) & EIM_EIMCR_GEIEN_MASK) 115 /*! @} */ 116 117 /*! @name EICHEN - Error Injection Channel Enable register */ 118 /*! @{ */ 119 120 #define EIM_EICHEN_EICH1EN_MASK (0x40000000U) 121 #define EIM_EICHEN_EICH1EN_SHIFT (30U) 122 #define EIM_EICHEN_EICH1EN_WIDTH (1U) 123 #define EIM_EICHEN_EICH1EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH1EN_SHIFT)) & EIM_EICHEN_EICH1EN_MASK) 124 125 #define EIM_EICHEN_EICH0EN_MASK (0x80000000U) 126 #define EIM_EICHEN_EICH0EN_SHIFT (31U) 127 #define EIM_EICHEN_EICH0EN_WIDTH (1U) 128 #define EIM_EICHEN_EICH0EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH0EN_SHIFT)) & EIM_EICHEN_EICH0EN_MASK) 129 /*! @} */ 130 131 /*! @name EICHDn_WORD0 - Error Injection Channel Descriptor n, Word0 */ 132 /*! @{ */ 133 134 #define EIM_EICHDn_WORD0_CHKBIT_MASK_MASK (0xFE000000U) 135 #define EIM_EICHDn_WORD0_CHKBIT_MASK_SHIFT (25U) 136 #define EIM_EICHDn_WORD0_CHKBIT_MASK_WIDTH (7U) 137 #define EIM_EICHDn_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHDn_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHDn_WORD0_CHKBIT_MASK_MASK) 138 /*! @} */ 139 140 /*! @name EICHDn_WORD1 - Error Injection Channel Descriptor n, Word1 */ 141 /*! @{ */ 142 143 #define EIM_EICHDn_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 144 #define EIM_EICHDn_WORD1_B0_3DATA_MASK_SHIFT (0U) 145 #define EIM_EICHDn_WORD1_B0_3DATA_MASK_WIDTH (32U) 146 #define EIM_EICHDn_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHDn_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHDn_WORD1_B0_3DATA_MASK_MASK) 147 /*! @} */ 148 149 /*! 150 * @} 151 */ /* end of group EIM_Register_Masks */ 152 153 /*! 154 * @} 155 */ /* end of group EIM_Peripheral_Access_Layer */ 156 157 #endif /* #if !defined(S32K142_EIM_H_) */ 158
