1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K142_CMP.h 10 * @version 1.1 11 * @date 2022-02-01 12 * @brief Peripheral Access Layer for S32K142_CMP 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K142_CMP_H_) /* Check if memory map has not been already included */ 58 #define S32K142_CMP_H_ 59 60 #include "S32K142_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- CMP Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer 68 * @{ 69 */ 70 71 /** CMP - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x0 */ 74 __IO uint32_t C1; /**< CMP Control Register 1, offset: 0x4 */ 75 __IO uint32_t C2; /**< CMP Control Register 2, offset: 0x8 */ 76 } CMP_Type, *CMP_MemMapPtr; 77 78 /** Number of instances of the CMP module. */ 79 #define CMP_INSTANCE_COUNT (1u) 80 81 /* CMP - Peripheral instance base addresses */ 82 /** Peripheral CMP0 base address */ 83 #define IP_CMP0_BASE (0x40073000u) 84 /** Peripheral CMP0 base pointer */ 85 #define IP_CMP0 ((CMP_Type *)IP_CMP0_BASE) 86 /** Array initializer of CMP peripheral base addresses */ 87 #define IP_CMP_BASE_ADDRS { IP_CMP0_BASE } 88 /** Array initializer of CMP peripheral base pointers */ 89 #define IP_CMP_BASE_PTRS { IP_CMP0 } 90 91 /* ---------------------------------------------------------------------------- 92 -- CMP Register Masks 93 ---------------------------------------------------------------------------- */ 94 95 /*! 96 * @addtogroup CMP_Register_Masks CMP Register Masks 97 * @{ 98 */ 99 100 /*! @name C0 - CMP Control Register 0 */ 101 /*! @{ */ 102 103 #define CMP_C0_HYSTCTR_MASK (0x3U) 104 #define CMP_C0_HYSTCTR_SHIFT (0U) 105 #define CMP_C0_HYSTCTR_WIDTH (2U) 106 #define CMP_C0_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_HYSTCTR_SHIFT)) & CMP_C0_HYSTCTR_MASK) 107 108 #define CMP_C0_OFFSET_MASK (0x4U) 109 #define CMP_C0_OFFSET_SHIFT (2U) 110 #define CMP_C0_OFFSET_WIDTH (1U) 111 #define CMP_C0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_OFFSET_SHIFT)) & CMP_C0_OFFSET_MASK) 112 113 #define CMP_C0_FILTER_CNT_MASK (0x70U) 114 #define CMP_C0_FILTER_CNT_SHIFT (4U) 115 #define CMP_C0_FILTER_CNT_WIDTH (3U) 116 #define CMP_C0_FILTER_CNT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FILTER_CNT_SHIFT)) & CMP_C0_FILTER_CNT_MASK) 117 118 #define CMP_C0_EN_MASK (0x100U) 119 #define CMP_C0_EN_SHIFT (8U) 120 #define CMP_C0_EN_WIDTH (1U) 121 #define CMP_C0_EN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_EN_SHIFT)) & CMP_C0_EN_MASK) 122 123 #define CMP_C0_OPE_MASK (0x200U) 124 #define CMP_C0_OPE_SHIFT (9U) 125 #define CMP_C0_OPE_WIDTH (1U) 126 #define CMP_C0_OPE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_OPE_SHIFT)) & CMP_C0_OPE_MASK) 127 128 #define CMP_C0_COS_MASK (0x400U) 129 #define CMP_C0_COS_SHIFT (10U) 130 #define CMP_C0_COS_WIDTH (1U) 131 #define CMP_C0_COS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COS_SHIFT)) & CMP_C0_COS_MASK) 132 133 #define CMP_C0_INVT_MASK (0x800U) 134 #define CMP_C0_INVT_SHIFT (11U) 135 #define CMP_C0_INVT_WIDTH (1U) 136 #define CMP_C0_INVT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_INVT_SHIFT)) & CMP_C0_INVT_MASK) 137 138 #define CMP_C0_PMODE_MASK (0x1000U) 139 #define CMP_C0_PMODE_SHIFT (12U) 140 #define CMP_C0_PMODE_WIDTH (1U) 141 #define CMP_C0_PMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_PMODE_SHIFT)) & CMP_C0_PMODE_MASK) 142 143 #define CMP_C0_WE_MASK (0x4000U) 144 #define CMP_C0_WE_SHIFT (14U) 145 #define CMP_C0_WE_WIDTH (1U) 146 #define CMP_C0_WE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_WE_SHIFT)) & CMP_C0_WE_MASK) 147 148 #define CMP_C0_SE_MASK (0x8000U) 149 #define CMP_C0_SE_SHIFT (15U) 150 #define CMP_C0_SE_WIDTH (1U) 151 #define CMP_C0_SE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_SE_SHIFT)) & CMP_C0_SE_MASK) 152 153 #define CMP_C0_FPR_MASK (0xFF0000U) 154 #define CMP_C0_FPR_SHIFT (16U) 155 #define CMP_C0_FPR_WIDTH (8U) 156 #define CMP_C0_FPR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FPR_SHIFT)) & CMP_C0_FPR_MASK) 157 158 #define CMP_C0_COUT_MASK (0x1000000U) 159 #define CMP_C0_COUT_SHIFT (24U) 160 #define CMP_C0_COUT_WIDTH (1U) 161 #define CMP_C0_COUT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COUT_SHIFT)) & CMP_C0_COUT_MASK) 162 163 #define CMP_C0_CFF_MASK (0x2000000U) 164 #define CMP_C0_CFF_SHIFT (25U) 165 #define CMP_C0_CFF_WIDTH (1U) 166 #define CMP_C0_CFF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFF_SHIFT)) & CMP_C0_CFF_MASK) 167 168 #define CMP_C0_CFR_MASK (0x4000000U) 169 #define CMP_C0_CFR_SHIFT (26U) 170 #define CMP_C0_CFR_WIDTH (1U) 171 #define CMP_C0_CFR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK) 172 173 #define CMP_C0_IEF_MASK (0x8000000U) 174 #define CMP_C0_IEF_SHIFT (27U) 175 #define CMP_C0_IEF_WIDTH (1U) 176 #define CMP_C0_IEF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IEF_SHIFT)) & CMP_C0_IEF_MASK) 177 178 #define CMP_C0_IER_MASK (0x10000000U) 179 #define CMP_C0_IER_SHIFT (28U) 180 #define CMP_C0_IER_WIDTH (1U) 181 #define CMP_C0_IER(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IER_SHIFT)) & CMP_C0_IER_MASK) 182 183 #define CMP_C0_DMAEN_MASK (0x40000000U) 184 #define CMP_C0_DMAEN_SHIFT (30U) 185 #define CMP_C0_DMAEN_WIDTH (1U) 186 #define CMP_C0_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_DMAEN_SHIFT)) & CMP_C0_DMAEN_MASK) 187 /*! @} */ 188 189 /*! @name C1 - CMP Control Register 1 */ 190 /*! @{ */ 191 192 #define CMP_C1_VOSEL_MASK (0xFFU) 193 #define CMP_C1_VOSEL_SHIFT (0U) 194 #define CMP_C1_VOSEL_WIDTH (8U) 195 #define CMP_C1_VOSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VOSEL_SHIFT)) & CMP_C1_VOSEL_MASK) 196 197 #define CMP_C1_MSEL_MASK (0x700U) 198 #define CMP_C1_MSEL_SHIFT (8U) 199 #define CMP_C1_MSEL_WIDTH (3U) 200 #define CMP_C1_MSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_MSEL_SHIFT)) & CMP_C1_MSEL_MASK) 201 202 #define CMP_C1_PSEL_MASK (0x3800U) 203 #define CMP_C1_PSEL_SHIFT (11U) 204 #define CMP_C1_PSEL_WIDTH (3U) 205 #define CMP_C1_PSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SHIFT)) & CMP_C1_PSEL_MASK) 206 207 #define CMP_C1_VRSEL_MASK (0x4000U) 208 #define CMP_C1_VRSEL_SHIFT (14U) 209 #define CMP_C1_VRSEL_WIDTH (1U) 210 #define CMP_C1_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VRSEL_SHIFT)) & CMP_C1_VRSEL_MASK) 211 212 #define CMP_C1_DACEN_MASK (0x8000U) 213 #define CMP_C1_DACEN_SHIFT (15U) 214 #define CMP_C1_DACEN_WIDTH (1U) 215 #define CMP_C1_DACEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACEN_SHIFT)) & CMP_C1_DACEN_MASK) 216 217 #define CMP_C1_CHN0_MASK (0x10000U) 218 #define CMP_C1_CHN0_SHIFT (16U) 219 #define CMP_C1_CHN0_WIDTH (1U) 220 #define CMP_C1_CHN0(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN0_SHIFT)) & CMP_C1_CHN0_MASK) 221 222 #define CMP_C1_CHN1_MASK (0x20000U) 223 #define CMP_C1_CHN1_SHIFT (17U) 224 #define CMP_C1_CHN1_WIDTH (1U) 225 #define CMP_C1_CHN1(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN1_SHIFT)) & CMP_C1_CHN1_MASK) 226 227 #define CMP_C1_CHN2_MASK (0x40000U) 228 #define CMP_C1_CHN2_SHIFT (18U) 229 #define CMP_C1_CHN2_WIDTH (1U) 230 #define CMP_C1_CHN2(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN2_SHIFT)) & CMP_C1_CHN2_MASK) 231 232 #define CMP_C1_CHN3_MASK (0x80000U) 233 #define CMP_C1_CHN3_SHIFT (19U) 234 #define CMP_C1_CHN3_WIDTH (1U) 235 #define CMP_C1_CHN3(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN3_SHIFT)) & CMP_C1_CHN3_MASK) 236 237 #define CMP_C1_CHN4_MASK (0x100000U) 238 #define CMP_C1_CHN4_SHIFT (20U) 239 #define CMP_C1_CHN4_WIDTH (1U) 240 #define CMP_C1_CHN4(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN4_SHIFT)) & CMP_C1_CHN4_MASK) 241 242 #define CMP_C1_CHN5_MASK (0x200000U) 243 #define CMP_C1_CHN5_SHIFT (21U) 244 #define CMP_C1_CHN5_WIDTH (1U) 245 #define CMP_C1_CHN5(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN5_SHIFT)) & CMP_C1_CHN5_MASK) 246 247 #define CMP_C1_CHN6_MASK (0x400000U) 248 #define CMP_C1_CHN6_SHIFT (22U) 249 #define CMP_C1_CHN6_WIDTH (1U) 250 #define CMP_C1_CHN6(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN6_SHIFT)) & CMP_C1_CHN6_MASK) 251 252 #define CMP_C1_CHN7_MASK (0x800000U) 253 #define CMP_C1_CHN7_SHIFT (23U) 254 #define CMP_C1_CHN7_WIDTH (1U) 255 #define CMP_C1_CHN7(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN7_SHIFT)) & CMP_C1_CHN7_MASK) 256 257 #define CMP_C1_INNSEL_MASK (0x3000000U) 258 #define CMP_C1_INNSEL_SHIFT (24U) 259 #define CMP_C1_INNSEL_WIDTH (2U) 260 #define CMP_C1_INNSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_INNSEL_SHIFT)) & CMP_C1_INNSEL_MASK) 261 262 #define CMP_C1_INPSEL_MASK (0x18000000U) 263 #define CMP_C1_INPSEL_SHIFT (27U) 264 #define CMP_C1_INPSEL_WIDTH (2U) 265 #define CMP_C1_INPSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK) 266 /*! @} */ 267 268 /*! @name C2 - CMP Control Register 2 */ 269 /*! @{ */ 270 271 #define CMP_C2_ACOn_MASK (0xFFU) 272 #define CMP_C2_ACOn_SHIFT (0U) 273 #define CMP_C2_ACOn_WIDTH (8U) 274 #define CMP_C2_ACOn(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_ACOn_SHIFT)) & CMP_C2_ACOn_MASK) 275 276 #define CMP_C2_INITMOD_MASK (0x3F00U) 277 #define CMP_C2_INITMOD_SHIFT (8U) 278 #define CMP_C2_INITMOD_WIDTH (6U) 279 #define CMP_C2_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_INITMOD_SHIFT)) & CMP_C2_INITMOD_MASK) 280 281 #define CMP_C2_NSAM_MASK (0xC000U) 282 #define CMP_C2_NSAM_SHIFT (14U) 283 #define CMP_C2_NSAM_WIDTH (2U) 284 #define CMP_C2_NSAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_NSAM_SHIFT)) & CMP_C2_NSAM_MASK) 285 286 #define CMP_C2_CH0F_MASK (0x10000U) 287 #define CMP_C2_CH0F_SHIFT (16U) 288 #define CMP_C2_CH0F_WIDTH (1U) 289 #define CMP_C2_CH0F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH0F_SHIFT)) & CMP_C2_CH0F_MASK) 290 291 #define CMP_C2_CH1F_MASK (0x20000U) 292 #define CMP_C2_CH1F_SHIFT (17U) 293 #define CMP_C2_CH1F_WIDTH (1U) 294 #define CMP_C2_CH1F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH1F_SHIFT)) & CMP_C2_CH1F_MASK) 295 296 #define CMP_C2_CH2F_MASK (0x40000U) 297 #define CMP_C2_CH2F_SHIFT (18U) 298 #define CMP_C2_CH2F_WIDTH (1U) 299 #define CMP_C2_CH2F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH2F_SHIFT)) & CMP_C2_CH2F_MASK) 300 301 #define CMP_C2_CH3F_MASK (0x80000U) 302 #define CMP_C2_CH3F_SHIFT (19U) 303 #define CMP_C2_CH3F_WIDTH (1U) 304 #define CMP_C2_CH3F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH3F_SHIFT)) & CMP_C2_CH3F_MASK) 305 306 #define CMP_C2_CH4F_MASK (0x100000U) 307 #define CMP_C2_CH4F_SHIFT (20U) 308 #define CMP_C2_CH4F_WIDTH (1U) 309 #define CMP_C2_CH4F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH4F_SHIFT)) & CMP_C2_CH4F_MASK) 310 311 #define CMP_C2_CH5F_MASK (0x200000U) 312 #define CMP_C2_CH5F_SHIFT (21U) 313 #define CMP_C2_CH5F_WIDTH (1U) 314 #define CMP_C2_CH5F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH5F_SHIFT)) & CMP_C2_CH5F_MASK) 315 316 #define CMP_C2_CH6F_MASK (0x400000U) 317 #define CMP_C2_CH6F_SHIFT (22U) 318 #define CMP_C2_CH6F_WIDTH (1U) 319 #define CMP_C2_CH6F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH6F_SHIFT)) & CMP_C2_CH6F_MASK) 320 321 #define CMP_C2_CH7F_MASK (0x800000U) 322 #define CMP_C2_CH7F_SHIFT (23U) 323 #define CMP_C2_CH7F_WIDTH (1U) 324 #define CMP_C2_CH7F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH7F_SHIFT)) & CMP_C2_CH7F_MASK) 325 326 #define CMP_C2_FXMXCH_MASK (0xE000000U) 327 #define CMP_C2_FXMXCH_SHIFT (25U) 328 #define CMP_C2_FXMXCH_WIDTH (3U) 329 #define CMP_C2_FXMXCH(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMXCH_SHIFT)) & CMP_C2_FXMXCH_MASK) 330 331 #define CMP_C2_FXMP_MASK (0x20000000U) 332 #define CMP_C2_FXMP_SHIFT (29U) 333 #define CMP_C2_FXMP_WIDTH (1U) 334 #define CMP_C2_FXMP(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMP_SHIFT)) & CMP_C2_FXMP_MASK) 335 336 #define CMP_C2_RRIE_MASK (0x40000000U) 337 #define CMP_C2_RRIE_SHIFT (30U) 338 #define CMP_C2_RRIE_WIDTH (1U) 339 #define CMP_C2_RRIE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRIE_SHIFT)) & CMP_C2_RRIE_MASK) 340 341 #define CMP_C2_RRE_MASK (0x80000000U) 342 #define CMP_C2_RRE_SHIFT (31U) 343 #define CMP_C2_RRE_WIDTH (1U) 344 #define CMP_C2_RRE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRE_SHIFT)) & CMP_C2_RRE_MASK) 345 /*! @} */ 346 347 /*! 348 * @} 349 */ /* end of group CMP_Register_Masks */ 350 351 /*! 352 * @} 353 */ /* end of group CMP_Peripheral_Access_Layer */ 354 355 #endif /* #if !defined(S32K142_CMP_H_) */ 356
