1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K142W_FLEXIO.h 10 * @version 1.2 11 * @date 2022-02-10 12 * @brief Peripheral Access Layer for S32K142W_FLEXIO 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K142W_FLEXIO_H_) /* Check if memory map has not been already included */ 58 #define S32K142W_FLEXIO_H_ 59 60 #include "S32K142W_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- FLEXIO Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer 68 * @{ 69 */ 70 71 /** FLEXIO - Size of Registers Arrays */ 72 #define FLEXIO_SHIFTCTL_COUNT 4u 73 #define FLEXIO_SHIFTCFG_COUNT 4u 74 #define FLEXIO_SHIFTBUF_COUNT 4u 75 #define FLEXIO_SHIFTBUFBIS_COUNT 4u 76 #define FLEXIO_SHIFTBUFBYS_COUNT 4u 77 #define FLEXIO_SHIFTBUFBBS_COUNT 4u 78 #define FLEXIO_TIMCTL_COUNT 4u 79 #define FLEXIO_TIMCFG_COUNT 4u 80 #define FLEXIO_TIMCMP_COUNT 4u 81 82 /** FLEXIO - Register Layout Typedef */ 83 typedef struct { 84 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ 85 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ 86 __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */ 87 __I uint32_t PIN; /**< Pin State Register, offset: 0xC */ 88 __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */ 89 __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */ 90 __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */ 91 uint8_t RESERVED_0[4]; 92 __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ 93 __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ 94 __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */ 95 uint8_t RESERVED_1[4]; 96 __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ 97 uint8_t RESERVED_2[76]; 98 __IO uint32_t SHIFTCTL[FLEXIO_SHIFTCTL_COUNT]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */ 99 uint8_t RESERVED_3[112]; 100 __IO uint32_t SHIFTCFG[FLEXIO_SHIFTCFG_COUNT]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */ 101 uint8_t RESERVED_4[240]; 102 __IO uint32_t SHIFTBUF[FLEXIO_SHIFTBUF_COUNT]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */ 103 uint8_t RESERVED_5[112]; 104 __IO uint32_t SHIFTBUFBIS[FLEXIO_SHIFTBUFBIS_COUNT]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */ 105 uint8_t RESERVED_6[112]; 106 __IO uint32_t SHIFTBUFBYS[FLEXIO_SHIFTBUFBYS_COUNT]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */ 107 uint8_t RESERVED_7[112]; 108 __IO uint32_t SHIFTBUFBBS[FLEXIO_SHIFTBUFBBS_COUNT]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */ 109 uint8_t RESERVED_8[112]; 110 __IO uint32_t TIMCTL[FLEXIO_TIMCTL_COUNT]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */ 111 uint8_t RESERVED_9[112]; 112 __IO uint32_t TIMCFG[FLEXIO_TIMCFG_COUNT]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */ 113 uint8_t RESERVED_10[112]; 114 __IO uint32_t TIMCMP[FLEXIO_TIMCMP_COUNT]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */ 115 } FLEXIO_Type, *FLEXIO_MemMapPtr; 116 117 /** Number of instances of the FLEXIO module. */ 118 #define FLEXIO_INSTANCE_COUNT (1u) 119 120 /* FLEXIO - Peripheral instance base addresses */ 121 /** Peripheral FLEXIO base address */ 122 #define IP_FLEXIO_BASE (0x4005A000u) 123 /** Peripheral FLEXIO base pointer */ 124 #define IP_FLEXIO ((FLEXIO_Type *)IP_FLEXIO_BASE) 125 /** Array initializer of FLEXIO peripheral base addresses */ 126 #define IP_FLEXIO_BASE_ADDRS { IP_FLEXIO_BASE } 127 /** Array initializer of FLEXIO peripheral base pointers */ 128 #define IP_FLEXIO_BASE_PTRS { IP_FLEXIO } 129 130 /* ---------------------------------------------------------------------------- 131 -- FLEXIO Register Masks 132 ---------------------------------------------------------------------------- */ 133 134 /*! 135 * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks 136 * @{ 137 */ 138 139 /*! @name VERID - Version ID Register */ 140 /*! @{ */ 141 142 #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) 143 #define FLEXIO_VERID_FEATURE_SHIFT (0U) 144 #define FLEXIO_VERID_FEATURE_WIDTH (16U) 145 #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) 146 147 #define FLEXIO_VERID_MINOR_MASK (0xFF0000U) 148 #define FLEXIO_VERID_MINOR_SHIFT (16U) 149 #define FLEXIO_VERID_MINOR_WIDTH (8U) 150 #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) 151 152 #define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) 153 #define FLEXIO_VERID_MAJOR_SHIFT (24U) 154 #define FLEXIO_VERID_MAJOR_WIDTH (8U) 155 #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) 156 /*! @} */ 157 158 /*! @name PARAM - Parameter Register */ 159 /*! @{ */ 160 161 #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) 162 #define FLEXIO_PARAM_SHIFTER_SHIFT (0U) 163 #define FLEXIO_PARAM_SHIFTER_WIDTH (8U) 164 #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) 165 166 #define FLEXIO_PARAM_TIMER_MASK (0xFF00U) 167 #define FLEXIO_PARAM_TIMER_SHIFT (8U) 168 #define FLEXIO_PARAM_TIMER_WIDTH (8U) 169 #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) 170 171 #define FLEXIO_PARAM_PIN_MASK (0xFF0000U) 172 #define FLEXIO_PARAM_PIN_SHIFT (16U) 173 #define FLEXIO_PARAM_PIN_WIDTH (8U) 174 #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) 175 176 #define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) 177 #define FLEXIO_PARAM_TRIGGER_SHIFT (24U) 178 #define FLEXIO_PARAM_TRIGGER_WIDTH (8U) 179 #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) 180 /*! @} */ 181 182 /*! @name CTRL - FlexIO Control Register */ 183 /*! @{ */ 184 185 #define FLEXIO_CTRL_FLEXEN_MASK (0x1U) 186 #define FLEXIO_CTRL_FLEXEN_SHIFT (0U) 187 #define FLEXIO_CTRL_FLEXEN_WIDTH (1U) 188 #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) 189 190 #define FLEXIO_CTRL_SWRST_MASK (0x2U) 191 #define FLEXIO_CTRL_SWRST_SHIFT (1U) 192 #define FLEXIO_CTRL_SWRST_WIDTH (1U) 193 #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) 194 195 #define FLEXIO_CTRL_FASTACC_MASK (0x4U) 196 #define FLEXIO_CTRL_FASTACC_SHIFT (2U) 197 #define FLEXIO_CTRL_FASTACC_WIDTH (1U) 198 #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) 199 200 #define FLEXIO_CTRL_DBGE_MASK (0x40000000U) 201 #define FLEXIO_CTRL_DBGE_SHIFT (30U) 202 #define FLEXIO_CTRL_DBGE_WIDTH (1U) 203 #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) 204 205 #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) 206 #define FLEXIO_CTRL_DOZEN_SHIFT (31U) 207 #define FLEXIO_CTRL_DOZEN_WIDTH (1U) 208 #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) 209 /*! @} */ 210 211 /*! @name PIN - Pin State Register */ 212 /*! @{ */ 213 214 #define FLEXIO_PIN_PDI_MASK (0xFFU) 215 #define FLEXIO_PIN_PDI_SHIFT (0U) 216 #define FLEXIO_PIN_PDI_WIDTH (8U) 217 #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) 218 /*! @} */ 219 220 /*! @name SHIFTSTAT - Shifter Status Register */ 221 /*! @{ */ 222 223 #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU) 224 #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) 225 #define FLEXIO_SHIFTSTAT_SSF_WIDTH (4U) 226 #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) 227 /*! @} */ 228 229 /*! @name SHIFTERR - Shifter Error Register */ 230 /*! @{ */ 231 232 #define FLEXIO_SHIFTERR_SEF_MASK (0xFU) 233 #define FLEXIO_SHIFTERR_SEF_SHIFT (0U) 234 #define FLEXIO_SHIFTERR_SEF_WIDTH (4U) 235 #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) 236 /*! @} */ 237 238 /*! @name TIMSTAT - Timer Status Register */ 239 /*! @{ */ 240 241 #define FLEXIO_TIMSTAT_TSF_MASK (0xFU) 242 #define FLEXIO_TIMSTAT_TSF_SHIFT (0U) 243 #define FLEXIO_TIMSTAT_TSF_WIDTH (4U) 244 #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) 245 /*! @} */ 246 247 /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ 248 /*! @{ */ 249 250 #define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU) 251 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) 252 #define FLEXIO_SHIFTSIEN_SSIE_WIDTH (4U) 253 #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) 254 /*! @} */ 255 256 /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ 257 /*! @{ */ 258 259 #define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU) 260 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) 261 #define FLEXIO_SHIFTEIEN_SEIE_WIDTH (4U) 262 #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) 263 /*! @} */ 264 265 /*! @name TIMIEN - Timer Interrupt Enable Register */ 266 /*! @{ */ 267 268 #define FLEXIO_TIMIEN_TEIE_MASK (0xFU) 269 #define FLEXIO_TIMIEN_TEIE_SHIFT (0U) 270 #define FLEXIO_TIMIEN_TEIE_WIDTH (4U) 271 #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) 272 /*! @} */ 273 274 /*! @name SHIFTSDEN - Shifter Status DMA Enable */ 275 /*! @{ */ 276 277 #define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU) 278 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) 279 #define FLEXIO_SHIFTSDEN_SSDE_WIDTH (4U) 280 #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) 281 /*! @} */ 282 283 /*! @name SHIFTCTL - Shifter Control N Register */ 284 /*! @{ */ 285 286 #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) 287 #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) 288 #define FLEXIO_SHIFTCTL_SMOD_WIDTH (3U) 289 #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) 290 291 #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) 292 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) 293 #define FLEXIO_SHIFTCTL_PINPOL_WIDTH (1U) 294 #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) 295 296 #define FLEXIO_SHIFTCTL_PINSEL_MASK (0x700U) 297 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) 298 #define FLEXIO_SHIFTCTL_PINSEL_WIDTH (3U) 299 #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) 300 301 #define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) 302 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) 303 #define FLEXIO_SHIFTCTL_PINCFG_WIDTH (2U) 304 #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) 305 306 #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) 307 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) 308 #define FLEXIO_SHIFTCTL_TIMPOL_WIDTH (1U) 309 #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) 310 311 #define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U) 312 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) 313 #define FLEXIO_SHIFTCTL_TIMSEL_WIDTH (2U) 314 #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) 315 /*! @} */ 316 317 /*! @name SHIFTCFG - Shifter Configuration N Register */ 318 /*! @{ */ 319 320 #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) 321 #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) 322 #define FLEXIO_SHIFTCFG_SSTART_WIDTH (2U) 323 #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) 324 325 #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) 326 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) 327 #define FLEXIO_SHIFTCFG_SSTOP_WIDTH (2U) 328 #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) 329 330 #define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) 331 #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) 332 #define FLEXIO_SHIFTCFG_INSRC_WIDTH (1U) 333 #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) 334 /*! @} */ 335 336 /*! @name SHIFTBUF - Shifter Buffer N Register */ 337 /*! @{ */ 338 339 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) 340 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) 341 #define FLEXIO_SHIFTBUF_SHIFTBUF_WIDTH (32U) 342 #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) 343 /*! @} */ 344 345 /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ 346 /*! @{ */ 347 348 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) 349 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) 350 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_WIDTH (32U) 351 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) 352 /*! @} */ 353 354 /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ 355 /*! @{ */ 356 357 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) 358 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) 359 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_WIDTH (32U) 360 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) 361 /*! @} */ 362 363 /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ 364 /*! @{ */ 365 366 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) 367 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) 368 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_WIDTH (32U) 369 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) 370 /*! @} */ 371 372 /*! @name TIMCTL - Timer Control N Register */ 373 /*! @{ */ 374 375 #define FLEXIO_TIMCTL_TIMOD_MASK (0x3U) 376 #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) 377 #define FLEXIO_TIMCTL_TIMOD_WIDTH (2U) 378 #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) 379 380 #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) 381 #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) 382 #define FLEXIO_TIMCTL_PINPOL_WIDTH (1U) 383 #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) 384 385 #define FLEXIO_TIMCTL_PINSEL_MASK (0x700U) 386 #define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) 387 #define FLEXIO_TIMCTL_PINSEL_WIDTH (3U) 388 #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) 389 390 #define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) 391 #define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) 392 #define FLEXIO_TIMCTL_PINCFG_WIDTH (2U) 393 #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) 394 395 #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) 396 #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) 397 #define FLEXIO_TIMCTL_TRGSRC_WIDTH (1U) 398 #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) 399 400 #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) 401 #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) 402 #define FLEXIO_TIMCTL_TRGPOL_WIDTH (1U) 403 #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) 404 405 #define FLEXIO_TIMCTL_TRGSEL_MASK (0xF000000U) 406 #define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) 407 #define FLEXIO_TIMCTL_TRGSEL_WIDTH (4U) 408 #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) 409 /*! @} */ 410 411 /*! @name TIMCFG - Timer Configuration N Register */ 412 /*! @{ */ 413 414 #define FLEXIO_TIMCFG_TSTART_MASK (0x2U) 415 #define FLEXIO_TIMCFG_TSTART_SHIFT (1U) 416 #define FLEXIO_TIMCFG_TSTART_WIDTH (1U) 417 #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) 418 419 #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) 420 #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) 421 #define FLEXIO_TIMCFG_TSTOP_WIDTH (2U) 422 #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) 423 424 #define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) 425 #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) 426 #define FLEXIO_TIMCFG_TIMENA_WIDTH (3U) 427 #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) 428 429 #define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) 430 #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) 431 #define FLEXIO_TIMCFG_TIMDIS_WIDTH (3U) 432 #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) 433 434 #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) 435 #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) 436 #define FLEXIO_TIMCFG_TIMRST_WIDTH (3U) 437 #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) 438 439 #define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U) 440 #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) 441 #define FLEXIO_TIMCFG_TIMDEC_WIDTH (2U) 442 #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) 443 444 #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) 445 #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) 446 #define FLEXIO_TIMCFG_TIMOUT_WIDTH (2U) 447 #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) 448 /*! @} */ 449 450 /*! @name TIMCMP - Timer Compare N Register */ 451 /*! @{ */ 452 453 #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) 454 #define FLEXIO_TIMCMP_CMP_SHIFT (0U) 455 #define FLEXIO_TIMCMP_CMP_WIDTH (16U) 456 #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) 457 /*! @} */ 458 459 /*! 460 * @} 461 */ /* end of group FLEXIO_Register_Masks */ 462 463 /*! 464 * @} 465 */ /* end of group FLEXIO_Peripheral_Access_Layer */ 466 467 #endif /* #if !defined(S32K142W_FLEXIO_H_) */ 468
