1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K142W_AIPS.h 10 * @version 1.2 11 * @date 2022-02-10 12 * @brief Peripheral Access Layer for S32K142W_AIPS 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K142W_AIPS_H_) /* Check if memory map has not been already included */ 58 #define S32K142W_AIPS_H_ 59 60 #include "S32K142W_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- AIPS Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer 68 * @{ 69 */ 70 71 /** AIPS - Size of Registers Arrays */ 72 #define AIPS_OPACR_COUNT 12u 73 74 /** AIPS - Register Layout Typedef */ 75 typedef struct { 76 __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */ 77 uint8_t RESERVED_0[28]; 78 __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */ 79 __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */ 80 uint8_t RESERVED_1[4]; 81 __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */ 82 uint8_t RESERVED_2[16]; 83 __IO uint32_t OPACR[AIPS_OPACR_COUNT]; /**< Off-Platform Peripheral Access Control Register, array offset: 0x40, array step: 0x4 */ 84 } AIPS_Type, *AIPS_MemMapPtr; 85 86 /** Number of instances of the AIPS module. */ 87 #define AIPS_INSTANCE_COUNT (1u) 88 89 /* AIPS - Peripheral instance base addresses */ 90 /** Peripheral AIPS base address */ 91 #define IP_AIPS_BASE (0x40000000u) 92 /** Peripheral AIPS base pointer */ 93 #define IP_AIPS ((AIPS_Type *)IP_AIPS_BASE) 94 /** Array initializer of AIPS peripheral base addresses */ 95 #define IP_AIPS_BASE_ADDRS { IP_AIPS_BASE } 96 /** Array initializer of AIPS peripheral base pointers */ 97 #define IP_AIPS_BASE_PTRS { IP_AIPS } 98 99 /* ---------------------------------------------------------------------------- 100 -- AIPS Register Masks 101 ---------------------------------------------------------------------------- */ 102 103 /*! 104 * @addtogroup AIPS_Register_Masks AIPS Register Masks 105 * @{ 106 */ 107 108 /*! @name MPRA - Master Privilege Register A */ 109 /*! @{ */ 110 111 #define AIPS_MPRA_MPL2_MASK (0x100000U) 112 #define AIPS_MPRA_MPL2_SHIFT (20U) 113 #define AIPS_MPRA_MPL2_WIDTH (1U) 114 #define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK) 115 116 #define AIPS_MPRA_MTW2_MASK (0x200000U) 117 #define AIPS_MPRA_MTW2_SHIFT (21U) 118 #define AIPS_MPRA_MTW2_WIDTH (1U) 119 #define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK) 120 121 #define AIPS_MPRA_MTR2_MASK (0x400000U) 122 #define AIPS_MPRA_MTR2_SHIFT (22U) 123 #define AIPS_MPRA_MTR2_WIDTH (1U) 124 #define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK) 125 126 #define AIPS_MPRA_MPL1_MASK (0x1000000U) 127 #define AIPS_MPRA_MPL1_SHIFT (24U) 128 #define AIPS_MPRA_MPL1_WIDTH (1U) 129 #define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK) 130 131 #define AIPS_MPRA_MTW1_MASK (0x2000000U) 132 #define AIPS_MPRA_MTW1_SHIFT (25U) 133 #define AIPS_MPRA_MTW1_WIDTH (1U) 134 #define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK) 135 136 #define AIPS_MPRA_MTR1_MASK (0x4000000U) 137 #define AIPS_MPRA_MTR1_SHIFT (26U) 138 #define AIPS_MPRA_MTR1_WIDTH (1U) 139 #define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK) 140 141 #define AIPS_MPRA_MPL0_MASK (0x10000000U) 142 #define AIPS_MPRA_MPL0_SHIFT (28U) 143 #define AIPS_MPRA_MPL0_WIDTH (1U) 144 #define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK) 145 146 #define AIPS_MPRA_MTW0_MASK (0x20000000U) 147 #define AIPS_MPRA_MTW0_SHIFT (29U) 148 #define AIPS_MPRA_MTW0_WIDTH (1U) 149 #define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK) 150 151 #define AIPS_MPRA_MTR0_MASK (0x40000000U) 152 #define AIPS_MPRA_MTR0_SHIFT (30U) 153 #define AIPS_MPRA_MTR0_WIDTH (1U) 154 #define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK) 155 /*! @} */ 156 157 /*! @name PACRA - Peripheral Access Control Register */ 158 /*! @{ */ 159 160 #define AIPS_PACRA_TP1_MASK (0x1000000U) 161 #define AIPS_PACRA_TP1_SHIFT (24U) 162 #define AIPS_PACRA_TP1_WIDTH (1U) 163 #define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK) 164 165 #define AIPS_PACRA_WP1_MASK (0x2000000U) 166 #define AIPS_PACRA_WP1_SHIFT (25U) 167 #define AIPS_PACRA_WP1_WIDTH (1U) 168 #define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK) 169 170 #define AIPS_PACRA_SP1_MASK (0x4000000U) 171 #define AIPS_PACRA_SP1_SHIFT (26U) 172 #define AIPS_PACRA_SP1_WIDTH (1U) 173 #define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK) 174 175 #define AIPS_PACRA_TP0_MASK (0x10000000U) 176 #define AIPS_PACRA_TP0_SHIFT (28U) 177 #define AIPS_PACRA_TP0_WIDTH (1U) 178 #define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK) 179 180 #define AIPS_PACRA_WP0_MASK (0x20000000U) 181 #define AIPS_PACRA_WP0_SHIFT (29U) 182 #define AIPS_PACRA_WP0_WIDTH (1U) 183 #define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK) 184 185 #define AIPS_PACRA_SP0_MASK (0x40000000U) 186 #define AIPS_PACRA_SP0_SHIFT (30U) 187 #define AIPS_PACRA_SP0_WIDTH (1U) 188 #define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK) 189 /*! @} */ 190 191 /*! @name PACRB - Peripheral Access Control Register */ 192 /*! @{ */ 193 194 #define AIPS_PACRB_TP5_MASK (0x100U) 195 #define AIPS_PACRB_TP5_SHIFT (8U) 196 #define AIPS_PACRB_TP5_WIDTH (1U) 197 #define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK) 198 199 #define AIPS_PACRB_WP5_MASK (0x200U) 200 #define AIPS_PACRB_WP5_SHIFT (9U) 201 #define AIPS_PACRB_WP5_WIDTH (1U) 202 #define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK) 203 204 #define AIPS_PACRB_SP5_MASK (0x400U) 205 #define AIPS_PACRB_SP5_SHIFT (10U) 206 #define AIPS_PACRB_SP5_WIDTH (1U) 207 #define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK) 208 209 #define AIPS_PACRB_TP1_MASK (0x1000000U) 210 #define AIPS_PACRB_TP1_SHIFT (24U) 211 #define AIPS_PACRB_TP1_WIDTH (1U) 212 #define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK) 213 214 #define AIPS_PACRB_WP1_MASK (0x2000000U) 215 #define AIPS_PACRB_WP1_SHIFT (25U) 216 #define AIPS_PACRB_WP1_WIDTH (1U) 217 #define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK) 218 219 #define AIPS_PACRB_SP1_MASK (0x4000000U) 220 #define AIPS_PACRB_SP1_SHIFT (26U) 221 #define AIPS_PACRB_SP1_WIDTH (1U) 222 #define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK) 223 224 #define AIPS_PACRB_TP0_MASK (0x10000000U) 225 #define AIPS_PACRB_TP0_SHIFT (28U) 226 #define AIPS_PACRB_TP0_WIDTH (1U) 227 #define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK) 228 229 #define AIPS_PACRB_WP0_MASK (0x20000000U) 230 #define AIPS_PACRB_WP0_SHIFT (29U) 231 #define AIPS_PACRB_WP0_WIDTH (1U) 232 #define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK) 233 234 #define AIPS_PACRB_SP0_MASK (0x40000000U) 235 #define AIPS_PACRB_SP0_SHIFT (30U) 236 #define AIPS_PACRB_SP0_WIDTH (1U) 237 #define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK) 238 /*! @} */ 239 240 /*! @name PACRD - Peripheral Access Control Register */ 241 /*! @{ */ 242 243 #define AIPS_PACRD_TP1_MASK (0x1000000U) 244 #define AIPS_PACRD_TP1_SHIFT (24U) 245 #define AIPS_PACRD_TP1_WIDTH (1U) 246 #define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK) 247 248 #define AIPS_PACRD_WP1_MASK (0x2000000U) 249 #define AIPS_PACRD_WP1_SHIFT (25U) 250 #define AIPS_PACRD_WP1_WIDTH (1U) 251 #define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK) 252 253 #define AIPS_PACRD_SP1_MASK (0x4000000U) 254 #define AIPS_PACRD_SP1_SHIFT (26U) 255 #define AIPS_PACRD_SP1_WIDTH (1U) 256 #define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK) 257 258 #define AIPS_PACRD_TP0_MASK (0x10000000U) 259 #define AIPS_PACRD_TP0_SHIFT (28U) 260 #define AIPS_PACRD_TP0_WIDTH (1U) 261 #define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK) 262 263 #define AIPS_PACRD_WP0_MASK (0x20000000U) 264 #define AIPS_PACRD_WP0_SHIFT (29U) 265 #define AIPS_PACRD_WP0_WIDTH (1U) 266 #define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK) 267 268 #define AIPS_PACRD_SP0_MASK (0x40000000U) 269 #define AIPS_PACRD_SP0_SHIFT (30U) 270 #define AIPS_PACRD_SP0_WIDTH (1U) 271 #define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK) 272 /*! @} */ 273 274 /*! @name OPACR - Off-Platform Peripheral Access Control Register */ 275 /*! @{ */ 276 277 #define AIPS_OPACR_TP7_MASK (0x1U) 278 #define AIPS_OPACR_TP7_SHIFT (0U) 279 #define AIPS_OPACR_TP7_WIDTH (1U) 280 #define AIPS_OPACR_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_TP7_SHIFT)) & AIPS_OPACR_TP7_MASK) 281 282 #define AIPS_OPACR_WP7_MASK (0x2U) 283 #define AIPS_OPACR_WP7_SHIFT (1U) 284 #define AIPS_OPACR_WP7_WIDTH (1U) 285 #define AIPS_OPACR_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_WP7_SHIFT)) & AIPS_OPACR_WP7_MASK) 286 287 #define AIPS_OPACR_SP7_MASK (0x4U) 288 #define AIPS_OPACR_SP7_SHIFT (2U) 289 #define AIPS_OPACR_SP7_WIDTH (1U) 290 #define AIPS_OPACR_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_SP7_SHIFT)) & AIPS_OPACR_SP7_MASK) 291 292 #define AIPS_OPACR_TP6_MASK (0x10U) 293 #define AIPS_OPACR_TP6_SHIFT (4U) 294 #define AIPS_OPACR_TP6_WIDTH (1U) 295 #define AIPS_OPACR_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_TP6_SHIFT)) & AIPS_OPACR_TP6_MASK) 296 297 #define AIPS_OPACR_WP6_MASK (0x20U) 298 #define AIPS_OPACR_WP6_SHIFT (5U) 299 #define AIPS_OPACR_WP6_WIDTH (1U) 300 #define AIPS_OPACR_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_WP6_SHIFT)) & AIPS_OPACR_WP6_MASK) 301 302 #define AIPS_OPACR_SP6_MASK (0x40U) 303 #define AIPS_OPACR_SP6_SHIFT (6U) 304 #define AIPS_OPACR_SP6_WIDTH (1U) 305 #define AIPS_OPACR_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_SP6_SHIFT)) & AIPS_OPACR_SP6_MASK) 306 307 #define AIPS_OPACR_TP5_MASK (0x100U) 308 #define AIPS_OPACR_TP5_SHIFT (8U) 309 #define AIPS_OPACR_TP5_WIDTH (1U) 310 #define AIPS_OPACR_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_TP5_SHIFT)) & AIPS_OPACR_TP5_MASK) 311 312 #define AIPS_OPACR_WP5_MASK (0x200U) 313 #define AIPS_OPACR_WP5_SHIFT (9U) 314 #define AIPS_OPACR_WP5_WIDTH (1U) 315 #define AIPS_OPACR_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_WP5_SHIFT)) & AIPS_OPACR_WP5_MASK) 316 317 #define AIPS_OPACR_SP5_MASK (0x400U) 318 #define AIPS_OPACR_SP5_SHIFT (10U) 319 #define AIPS_OPACR_SP5_WIDTH (1U) 320 #define AIPS_OPACR_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_SP5_SHIFT)) & AIPS_OPACR_SP5_MASK) 321 322 #define AIPS_OPACR_TP4_MASK (0x1000U) 323 #define AIPS_OPACR_TP4_SHIFT (12U) 324 #define AIPS_OPACR_TP4_WIDTH (1U) 325 #define AIPS_OPACR_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_TP4_SHIFT)) & AIPS_OPACR_TP4_MASK) 326 327 #define AIPS_OPACR_WP4_MASK (0x2000U) 328 #define AIPS_OPACR_WP4_SHIFT (13U) 329 #define AIPS_OPACR_WP4_WIDTH (1U) 330 #define AIPS_OPACR_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_WP4_SHIFT)) & AIPS_OPACR_WP4_MASK) 331 332 #define AIPS_OPACR_SP4_MASK (0x4000U) 333 #define AIPS_OPACR_SP4_SHIFT (14U) 334 #define AIPS_OPACR_SP4_WIDTH (1U) 335 #define AIPS_OPACR_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_SP4_SHIFT)) & AIPS_OPACR_SP4_MASK) 336 337 #define AIPS_OPACR_TP3_MASK (0x10000U) 338 #define AIPS_OPACR_TP3_SHIFT (16U) 339 #define AIPS_OPACR_TP3_WIDTH (1U) 340 #define AIPS_OPACR_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_TP3_SHIFT)) & AIPS_OPACR_TP3_MASK) 341 342 #define AIPS_OPACR_WP3_MASK (0x20000U) 343 #define AIPS_OPACR_WP3_SHIFT (17U) 344 #define AIPS_OPACR_WP3_WIDTH (1U) 345 #define AIPS_OPACR_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_WP3_SHIFT)) & AIPS_OPACR_WP3_MASK) 346 347 #define AIPS_OPACR_SP3_MASK (0x40000U) 348 #define AIPS_OPACR_SP3_SHIFT (18U) 349 #define AIPS_OPACR_SP3_WIDTH (1U) 350 #define AIPS_OPACR_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_SP3_SHIFT)) & AIPS_OPACR_SP3_MASK) 351 352 #define AIPS_OPACR_TP2_MASK (0x100000U) 353 #define AIPS_OPACR_TP2_SHIFT (20U) 354 #define AIPS_OPACR_TP2_WIDTH (1U) 355 #define AIPS_OPACR_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_TP2_SHIFT)) & AIPS_OPACR_TP2_MASK) 356 357 #define AIPS_OPACR_WP2_MASK (0x200000U) 358 #define AIPS_OPACR_WP2_SHIFT (21U) 359 #define AIPS_OPACR_WP2_WIDTH (1U) 360 #define AIPS_OPACR_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_WP2_SHIFT)) & AIPS_OPACR_WP2_MASK) 361 362 #define AIPS_OPACR_SP2_MASK (0x400000U) 363 #define AIPS_OPACR_SP2_SHIFT (22U) 364 #define AIPS_OPACR_SP2_WIDTH (1U) 365 #define AIPS_OPACR_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_SP2_SHIFT)) & AIPS_OPACR_SP2_MASK) 366 367 #define AIPS_OPACR_TP1_MASK (0x1000000U) 368 #define AIPS_OPACR_TP1_SHIFT (24U) 369 #define AIPS_OPACR_TP1_WIDTH (1U) 370 #define AIPS_OPACR_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_TP1_SHIFT)) & AIPS_OPACR_TP1_MASK) 371 372 #define AIPS_OPACR_WP1_MASK (0x2000000U) 373 #define AIPS_OPACR_WP1_SHIFT (25U) 374 #define AIPS_OPACR_WP1_WIDTH (1U) 375 #define AIPS_OPACR_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_WP1_SHIFT)) & AIPS_OPACR_WP1_MASK) 376 377 #define AIPS_OPACR_SP1_MASK (0x4000000U) 378 #define AIPS_OPACR_SP1_SHIFT (26U) 379 #define AIPS_OPACR_SP1_WIDTH (1U) 380 #define AIPS_OPACR_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_SP1_SHIFT)) & AIPS_OPACR_SP1_MASK) 381 382 #define AIPS_OPACR_TP0_MASK (0x10000000U) 383 #define AIPS_OPACR_TP0_SHIFT (28U) 384 #define AIPS_OPACR_TP0_WIDTH (1U) 385 #define AIPS_OPACR_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_TP0_SHIFT)) & AIPS_OPACR_TP0_MASK) 386 387 #define AIPS_OPACR_WP0_MASK (0x20000000U) 388 #define AIPS_OPACR_WP0_SHIFT (29U) 389 #define AIPS_OPACR_WP0_WIDTH (1U) 390 #define AIPS_OPACR_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_WP0_SHIFT)) & AIPS_OPACR_WP0_MASK) 391 392 #define AIPS_OPACR_SP0_MASK (0x40000000U) 393 #define AIPS_OPACR_SP0_SHIFT (30U) 394 #define AIPS_OPACR_SP0_WIDTH (1U) 395 #define AIPS_OPACR_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_SP0_SHIFT)) & AIPS_OPACR_SP0_MASK) 396 /*! @} */ 397 398 /*! 399 * @} 400 */ /* end of group AIPS_Register_Masks */ 401 402 /*! 403 * @} 404 */ /* end of group AIPS_Peripheral_Access_Layer */ 405 406 #endif /* #if !defined(S32K142W_AIPS_H_) */ 407
