1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K118_SCG.h 10 * @version 1.1 11 * @date 2022-01-24 12 * @brief Peripheral Access Layer for S32K118_SCG 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K118_SCG_H_) /* Check if memory map has not been already included */ 58 #define S32K118_SCG_H_ 59 60 #include "S32K118_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SCG Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SCG - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ 74 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ 75 uint8_t RESERVED_0[8]; 76 __I uint32_t CSR; /**< Clock Status Register, offset: 0x10 */ 77 __IO uint32_t RCCR; /**< Run Clock Control Register, offset: 0x14 */ 78 __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ 79 uint8_t RESERVED_1[4]; 80 __IO uint32_t CLKOUTCNFG; /**< SCG CLKOUT Configuration Register, offset: 0x20 */ 81 uint8_t RESERVED_2[220]; 82 __IO uint32_t SOSCCSR; /**< System OSC Control Status Register, offset: 0x100 */ 83 __IO uint32_t SOSCDIV; /**< System OSC Divide Register, offset: 0x104 */ 84 __IO uint32_t SOSCCFG; /**< System Oscillator Configuration Register, offset: 0x108 */ 85 uint8_t RESERVED_3[244]; 86 __IO uint32_t SIRCCSR; /**< Slow IRC Control Status Register, offset: 0x200 */ 87 __IO uint32_t SIRCDIV; /**< Slow IRC Divide Register, offset: 0x204 */ 88 __IO uint32_t SIRCCFG; /**< Slow IRC Configuration Register, offset: 0x208 */ 89 uint8_t RESERVED_4[244]; 90 __IO uint32_t FIRCCSR; /**< Fast IRC Control Status Register, offset: 0x300 */ 91 __IO uint32_t FIRCDIV; /**< Fast IRC Divide Register, offset: 0x304 */ 92 __IO uint32_t FIRCCFG; /**< Fast IRC Configuration Register, offset: 0x308 */ 93 } SCG_Type, *SCG_MemMapPtr; 94 95 /** Number of instances of the SCG module. */ 96 #define SCG_INSTANCE_COUNT (1u) 97 98 /* SCG - Peripheral instance base addresses */ 99 /** Peripheral SCG base address */ 100 #define IP_SCG_BASE (0x40064000u) 101 /** Peripheral SCG base pointer */ 102 #define IP_SCG ((SCG_Type *)IP_SCG_BASE) 103 /** Array initializer of SCG peripheral base addresses */ 104 #define IP_SCG_BASE_ADDRS { IP_SCG_BASE } 105 /** Array initializer of SCG peripheral base pointers */ 106 #define IP_SCG_BASE_PTRS { IP_SCG } 107 108 /* ---------------------------------------------------------------------------- 109 -- SCG Register Masks 110 ---------------------------------------------------------------------------- */ 111 112 /*! 113 * @addtogroup SCG_Register_Masks SCG Register Masks 114 * @{ 115 */ 116 117 /*! @name VERID - Version ID Register */ 118 /*! @{ */ 119 120 #define SCG_VERID_VERSION_MASK (0xFFFFFFFFU) 121 #define SCG_VERID_VERSION_SHIFT (0U) 122 #define SCG_VERID_VERSION_WIDTH (32U) 123 #define SCG_VERID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SCG_VERID_VERSION_SHIFT)) & SCG_VERID_VERSION_MASK) 124 /*! @} */ 125 126 /*! @name PARAM - Parameter Register */ 127 /*! @{ */ 128 129 #define SCG_PARAM_CLKPRES_MASK (0xFFU) 130 #define SCG_PARAM_CLKPRES_SHIFT (0U) 131 #define SCG_PARAM_CLKPRES_WIDTH (8U) 132 #define SCG_PARAM_CLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_CLKPRES_SHIFT)) & SCG_PARAM_CLKPRES_MASK) 133 134 #define SCG_PARAM_DIVPRES_MASK (0xF8000000U) 135 #define SCG_PARAM_DIVPRES_SHIFT (27U) 136 #define SCG_PARAM_DIVPRES_WIDTH (5U) 137 #define SCG_PARAM_DIVPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_DIVPRES_SHIFT)) & SCG_PARAM_DIVPRES_MASK) 138 /*! @} */ 139 140 /*! @name CSR - Clock Status Register */ 141 /*! @{ */ 142 143 #define SCG_CSR_DIVSLOW_MASK (0xFU) 144 #define SCG_CSR_DIVSLOW_SHIFT (0U) 145 #define SCG_CSR_DIVSLOW_WIDTH (4U) 146 #define SCG_CSR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK) 147 148 #define SCG_CSR_DIVBUS_MASK (0xF0U) 149 #define SCG_CSR_DIVBUS_SHIFT (4U) 150 #define SCG_CSR_DIVBUS_WIDTH (4U) 151 #define SCG_CSR_DIVBUS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVBUS_SHIFT)) & SCG_CSR_DIVBUS_MASK) 152 153 #define SCG_CSR_DIVCORE_MASK (0xF0000U) 154 #define SCG_CSR_DIVCORE_SHIFT (16U) 155 #define SCG_CSR_DIVCORE_WIDTH (4U) 156 #define SCG_CSR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVCORE_SHIFT)) & SCG_CSR_DIVCORE_MASK) 157 158 #define SCG_CSR_SCS_MASK (0xF000000U) 159 #define SCG_CSR_SCS_SHIFT (24U) 160 #define SCG_CSR_SCS_WIDTH (4U) 161 #define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK) 162 /*! @} */ 163 164 /*! @name RCCR - Run Clock Control Register */ 165 /*! @{ */ 166 167 #define SCG_RCCR_DIVSLOW_MASK (0xFU) 168 #define SCG_RCCR_DIVSLOW_SHIFT (0U) 169 #define SCG_RCCR_DIVSLOW_WIDTH (4U) 170 #define SCG_RCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVSLOW_SHIFT)) & SCG_RCCR_DIVSLOW_MASK) 171 172 #define SCG_RCCR_DIVBUS_MASK (0xF0U) 173 #define SCG_RCCR_DIVBUS_SHIFT (4U) 174 #define SCG_RCCR_DIVBUS_WIDTH (4U) 175 #define SCG_RCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVBUS_SHIFT)) & SCG_RCCR_DIVBUS_MASK) 176 177 #define SCG_RCCR_DIVCORE_MASK (0xF0000U) 178 #define SCG_RCCR_DIVCORE_SHIFT (16U) 179 #define SCG_RCCR_DIVCORE_WIDTH (4U) 180 #define SCG_RCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVCORE_SHIFT)) & SCG_RCCR_DIVCORE_MASK) 181 182 #define SCG_RCCR_SCS_MASK (0xF000000U) 183 #define SCG_RCCR_SCS_SHIFT (24U) 184 #define SCG_RCCR_SCS_WIDTH (4U) 185 #define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK) 186 /*! @} */ 187 188 /*! @name VCCR - VLPR Clock Control Register */ 189 /*! @{ */ 190 191 #define SCG_VCCR_DIVSLOW_MASK (0xFU) 192 #define SCG_VCCR_DIVSLOW_SHIFT (0U) 193 #define SCG_VCCR_DIVSLOW_WIDTH (4U) 194 #define SCG_VCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVSLOW_SHIFT)) & SCG_VCCR_DIVSLOW_MASK) 195 196 #define SCG_VCCR_DIVBUS_MASK (0xF0U) 197 #define SCG_VCCR_DIVBUS_SHIFT (4U) 198 #define SCG_VCCR_DIVBUS_WIDTH (4U) 199 #define SCG_VCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVBUS_SHIFT)) & SCG_VCCR_DIVBUS_MASK) 200 201 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) 202 #define SCG_VCCR_DIVCORE_SHIFT (16U) 203 #define SCG_VCCR_DIVCORE_WIDTH (4U) 204 #define SCG_VCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK) 205 206 #define SCG_VCCR_SCS_MASK (0xF000000U) 207 #define SCG_VCCR_SCS_SHIFT (24U) 208 #define SCG_VCCR_SCS_WIDTH (4U) 209 #define SCG_VCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_SCS_SHIFT)) & SCG_VCCR_SCS_MASK) 210 /*! @} */ 211 212 /*! @name CLKOUTCNFG - SCG CLKOUT Configuration Register */ 213 /*! @{ */ 214 215 #define SCG_CLKOUTCNFG_CLKOUTSEL_MASK (0xF000000U) 216 #define SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT (24U) 217 #define SCG_CLKOUTCNFG_CLKOUTSEL_WIDTH (4U) 218 #define SCG_CLKOUTCNFG_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT)) & SCG_CLKOUTCNFG_CLKOUTSEL_MASK) 219 /*! @} */ 220 221 /*! @name SOSCCSR - System OSC Control Status Register */ 222 /*! @{ */ 223 224 #define SCG_SOSCCSR_SOSCEN_MASK (0x1U) 225 #define SCG_SOSCCSR_SOSCEN_SHIFT (0U) 226 #define SCG_SOSCCSR_SOSCEN_WIDTH (1U) 227 #define SCG_SOSCCSR_SOSCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK) 228 229 #define SCG_SOSCCSR_SOSCCM_MASK (0x10000U) 230 #define SCG_SOSCCSR_SOSCCM_SHIFT (16U) 231 #define SCG_SOSCCSR_SOSCCM_WIDTH (1U) 232 #define SCG_SOSCCSR_SOSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCM_SHIFT)) & SCG_SOSCCSR_SOSCCM_MASK) 233 234 #define SCG_SOSCCSR_SOSCCMRE_MASK (0x20000U) 235 #define SCG_SOSCCSR_SOSCCMRE_SHIFT (17U) 236 #define SCG_SOSCCSR_SOSCCMRE_WIDTH (1U) 237 #define SCG_SOSCCSR_SOSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCMRE_SHIFT)) & SCG_SOSCCSR_SOSCCMRE_MASK) 238 239 #define SCG_SOSCCSR_LK_MASK (0x800000U) 240 #define SCG_SOSCCSR_LK_SHIFT (23U) 241 #define SCG_SOSCCSR_LK_WIDTH (1U) 242 #define SCG_SOSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_LK_SHIFT)) & SCG_SOSCCSR_LK_MASK) 243 244 #define SCG_SOSCCSR_SOSCVLD_MASK (0x1000000U) 245 #define SCG_SOSCCSR_SOSCVLD_SHIFT (24U) 246 #define SCG_SOSCCSR_SOSCVLD_WIDTH (1U) 247 #define SCG_SOSCCSR_SOSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK) 248 249 #define SCG_SOSCCSR_SOSCSEL_MASK (0x2000000U) 250 #define SCG_SOSCCSR_SOSCSEL_SHIFT (25U) 251 #define SCG_SOSCCSR_SOSCSEL_WIDTH (1U) 252 #define SCG_SOSCCSR_SOSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSEL_SHIFT)) & SCG_SOSCCSR_SOSCSEL_MASK) 253 254 #define SCG_SOSCCSR_SOSCERR_MASK (0x4000000U) 255 #define SCG_SOSCCSR_SOSCERR_SHIFT (26U) 256 #define SCG_SOSCCSR_SOSCERR_WIDTH (1U) 257 #define SCG_SOSCCSR_SOSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERR_SHIFT)) & SCG_SOSCCSR_SOSCERR_MASK) 258 /*! @} */ 259 260 /*! @name SOSCDIV - System OSC Divide Register */ 261 /*! @{ */ 262 263 #define SCG_SOSCDIV_SOSCDIV1_MASK (0x7U) 264 #define SCG_SOSCDIV_SOSCDIV1_SHIFT (0U) 265 #define SCG_SOSCDIV_SOSCDIV1_WIDTH (3U) 266 #define SCG_SOSCDIV_SOSCDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV1_SHIFT)) & SCG_SOSCDIV_SOSCDIV1_MASK) 267 268 #define SCG_SOSCDIV_SOSCDIV2_MASK (0x700U) 269 #define SCG_SOSCDIV_SOSCDIV2_SHIFT (8U) 270 #define SCG_SOSCDIV_SOSCDIV2_WIDTH (3U) 271 #define SCG_SOSCDIV_SOSCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV2_SHIFT)) & SCG_SOSCDIV_SOSCDIV2_MASK) 272 /*! @} */ 273 274 /*! @name SOSCCFG - System Oscillator Configuration Register */ 275 /*! @{ */ 276 277 #define SCG_SOSCCFG_EREFS_MASK (0x4U) 278 #define SCG_SOSCCFG_EREFS_SHIFT (2U) 279 #define SCG_SOSCCFG_EREFS_WIDTH (1U) 280 #define SCG_SOSCCFG_EREFS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_EREFS_SHIFT)) & SCG_SOSCCFG_EREFS_MASK) 281 282 #define SCG_SOSCCFG_HGO_MASK (0x8U) 283 #define SCG_SOSCCFG_HGO_SHIFT (3U) 284 #define SCG_SOSCCFG_HGO_WIDTH (1U) 285 #define SCG_SOSCCFG_HGO(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_HGO_SHIFT)) & SCG_SOSCCFG_HGO_MASK) 286 287 #define SCG_SOSCCFG_RANGE_MASK (0x30U) 288 #define SCG_SOSCCFG_RANGE_SHIFT (4U) 289 #define SCG_SOSCCFG_RANGE_WIDTH (2U) 290 #define SCG_SOSCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_RANGE_SHIFT)) & SCG_SOSCCFG_RANGE_MASK) 291 /*! @} */ 292 293 /*! @name SIRCCSR - Slow IRC Control Status Register */ 294 /*! @{ */ 295 296 #define SCG_SIRCCSR_SIRCEN_MASK (0x1U) 297 #define SCG_SIRCCSR_SIRCEN_SHIFT (0U) 298 #define SCG_SIRCCSR_SIRCEN_WIDTH (1U) 299 #define SCG_SIRCCSR_SIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCEN_SHIFT)) & SCG_SIRCCSR_SIRCEN_MASK) 300 301 #define SCG_SIRCCSR_SIRCSTEN_MASK (0x2U) 302 #define SCG_SIRCCSR_SIRCSTEN_SHIFT (1U) 303 #define SCG_SIRCCSR_SIRCSTEN_WIDTH (1U) 304 #define SCG_SIRCCSR_SIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSTEN_SHIFT)) & SCG_SIRCCSR_SIRCSTEN_MASK) 305 306 #define SCG_SIRCCSR_SIRCLPEN_MASK (0x4U) 307 #define SCG_SIRCCSR_SIRCLPEN_SHIFT (2U) 308 #define SCG_SIRCCSR_SIRCLPEN_WIDTH (1U) 309 #define SCG_SIRCCSR_SIRCLPEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCLPEN_SHIFT)) & SCG_SIRCCSR_SIRCLPEN_MASK) 310 311 #define SCG_SIRCCSR_LK_MASK (0x800000U) 312 #define SCG_SIRCCSR_LK_SHIFT (23U) 313 #define SCG_SIRCCSR_LK_WIDTH (1U) 314 #define SCG_SIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LK_SHIFT)) & SCG_SIRCCSR_LK_MASK) 315 316 #define SCG_SIRCCSR_SIRCVLD_MASK (0x1000000U) 317 #define SCG_SIRCCSR_SIRCVLD_SHIFT (24U) 318 #define SCG_SIRCCSR_SIRCVLD_WIDTH (1U) 319 #define SCG_SIRCCSR_SIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK) 320 321 #define SCG_SIRCCSR_SIRCSEL_MASK (0x2000000U) 322 #define SCG_SIRCCSR_SIRCSEL_SHIFT (25U) 323 #define SCG_SIRCCSR_SIRCSEL_WIDTH (1U) 324 #define SCG_SIRCCSR_SIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSEL_SHIFT)) & SCG_SIRCCSR_SIRCSEL_MASK) 325 /*! @} */ 326 327 /*! @name SIRCDIV - Slow IRC Divide Register */ 328 /*! @{ */ 329 330 #define SCG_SIRCDIV_SIRCDIV1_MASK (0x7U) 331 #define SCG_SIRCDIV_SIRCDIV1_SHIFT (0U) 332 #define SCG_SIRCDIV_SIRCDIV1_WIDTH (3U) 333 #define SCG_SIRCDIV_SIRCDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV1_SHIFT)) & SCG_SIRCDIV_SIRCDIV1_MASK) 334 335 #define SCG_SIRCDIV_SIRCDIV2_MASK (0x700U) 336 #define SCG_SIRCDIV_SIRCDIV2_SHIFT (8U) 337 #define SCG_SIRCDIV_SIRCDIV2_WIDTH (3U) 338 #define SCG_SIRCDIV_SIRCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV2_SHIFT)) & SCG_SIRCDIV_SIRCDIV2_MASK) 339 /*! @} */ 340 341 /*! @name SIRCCFG - Slow IRC Configuration Register */ 342 /*! @{ */ 343 344 #define SCG_SIRCCFG_RANGE_MASK (0x1U) 345 #define SCG_SIRCCFG_RANGE_SHIFT (0U) 346 #define SCG_SIRCCFG_RANGE_WIDTH (1U) 347 #define SCG_SIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCFG_RANGE_SHIFT)) & SCG_SIRCCFG_RANGE_MASK) 348 /*! @} */ 349 350 /*! @name FIRCCSR - Fast IRC Control Status Register */ 351 /*! @{ */ 352 353 #define SCG_FIRCCSR_FIRCEN_MASK (0x1U) 354 #define SCG_FIRCCSR_FIRCEN_SHIFT (0U) 355 #define SCG_FIRCCSR_FIRCEN_WIDTH (1U) 356 #define SCG_FIRCCSR_FIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK) 357 358 #define SCG_FIRCCSR_FIRCREGOFF_MASK (0x8U) 359 #define SCG_FIRCCSR_FIRCREGOFF_SHIFT (3U) 360 #define SCG_FIRCCSR_FIRCREGOFF_WIDTH (1U) 361 #define SCG_FIRCCSR_FIRCREGOFF(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCREGOFF_SHIFT)) & SCG_FIRCCSR_FIRCREGOFF_MASK) 362 363 #define SCG_FIRCCSR_LK_MASK (0x800000U) 364 #define SCG_FIRCCSR_LK_SHIFT (23U) 365 #define SCG_FIRCCSR_LK_WIDTH (1U) 366 #define SCG_FIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_LK_SHIFT)) & SCG_FIRCCSR_LK_MASK) 367 368 #define SCG_FIRCCSR_FIRCVLD_MASK (0x1000000U) 369 #define SCG_FIRCCSR_FIRCVLD_SHIFT (24U) 370 #define SCG_FIRCCSR_FIRCVLD_WIDTH (1U) 371 #define SCG_FIRCCSR_FIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCVLD_SHIFT)) & SCG_FIRCCSR_FIRCVLD_MASK) 372 373 #define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U) 374 #define SCG_FIRCCSR_FIRCSEL_SHIFT (25U) 375 #define SCG_FIRCCSR_FIRCSEL_WIDTH (1U) 376 #define SCG_FIRCCSR_FIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK) 377 /*! @} */ 378 379 /*! @name FIRCDIV - Fast IRC Divide Register */ 380 /*! @{ */ 381 382 #define SCG_FIRCDIV_FIRCDIV1_MASK (0x7U) 383 #define SCG_FIRCDIV_FIRCDIV1_SHIFT (0U) 384 #define SCG_FIRCDIV_FIRCDIV1_WIDTH (3U) 385 #define SCG_FIRCDIV_FIRCDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV1_SHIFT)) & SCG_FIRCDIV_FIRCDIV1_MASK) 386 387 #define SCG_FIRCDIV_FIRCDIV2_MASK (0x700U) 388 #define SCG_FIRCDIV_FIRCDIV2_SHIFT (8U) 389 #define SCG_FIRCDIV_FIRCDIV2_WIDTH (3U) 390 #define SCG_FIRCDIV_FIRCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV2_SHIFT)) & SCG_FIRCDIV_FIRCDIV2_MASK) 391 /*! @} */ 392 393 /*! @name FIRCCFG - Fast IRC Configuration Register */ 394 /*! @{ */ 395 396 #define SCG_FIRCCFG_RANGE_MASK (0x3U) 397 #define SCG_FIRCCFG_RANGE_SHIFT (0U) 398 #define SCG_FIRCCFG_RANGE_WIDTH (2U) 399 #define SCG_FIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_RANGE_SHIFT)) & SCG_FIRCCFG_RANGE_MASK) 400 /*! @} */ 401 402 /*! 403 * @} 404 */ /* end of group SCG_Register_Masks */ 405 406 /*! 407 * @} 408 */ /* end of group SCG_Peripheral_Access_Layer */ 409 410 #endif /* #if !defined(S32K118_SCG_H_) */ 411
