1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K118_LPUART.h 10 * @version 1.1 11 * @date 2022-01-24 12 * @brief Peripheral Access Layer for S32K118_LPUART 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K118_LPUART_H_) /* Check if memory map has not been already included */ 58 #define S32K118_LPUART_H_ 59 60 #include "S32K118_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- LPUART Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer 68 * @{ 69 */ 70 71 /** LPUART - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ 74 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ 75 __IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */ 76 __IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */ 77 __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x10 */ 78 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */ 79 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */ 80 __IO uint32_t DATA; /**< LPUART Data Register, offset: 0x1C */ 81 __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x20 */ 82 __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x24 */ 83 __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */ 84 __IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x2C */ 85 } LPUART_Type, *LPUART_MemMapPtr; 86 87 /** Number of instances of the LPUART module. */ 88 #define LPUART_INSTANCE_COUNT (2u) 89 90 /* LPUART - Peripheral instance base addresses */ 91 /** Peripheral LPUART0 base address */ 92 #define IP_LPUART0_BASE (0x4006A000u) 93 /** Peripheral LPUART0 base pointer */ 94 #define IP_LPUART0 ((LPUART_Type *)IP_LPUART0_BASE) 95 /** Peripheral LPUART1 base address */ 96 #define IP_LPUART1_BASE (0x4006B000u) 97 /** Peripheral LPUART1 base pointer */ 98 #define IP_LPUART1 ((LPUART_Type *)IP_LPUART1_BASE) 99 /** Array initializer of LPUART peripheral base addresses */ 100 #define IP_LPUART_BASE_ADDRS { IP_LPUART0_BASE, IP_LPUART1_BASE } 101 /** Array initializer of LPUART peripheral base pointers */ 102 #define IP_LPUART_BASE_PTRS { IP_LPUART0, IP_LPUART1 } 103 104 /* ---------------------------------------------------------------------------- 105 -- LPUART Register Masks 106 ---------------------------------------------------------------------------- */ 107 108 /*! 109 * @addtogroup LPUART_Register_Masks LPUART Register Masks 110 * @{ 111 */ 112 113 /*! @name VERID - Version ID Register */ 114 /*! @{ */ 115 116 #define LPUART_VERID_FEATURE_MASK (0xFFFFU) 117 #define LPUART_VERID_FEATURE_SHIFT (0U) 118 #define LPUART_VERID_FEATURE_WIDTH (16U) 119 #define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) 120 121 #define LPUART_VERID_MINOR_MASK (0xFF0000U) 122 #define LPUART_VERID_MINOR_SHIFT (16U) 123 #define LPUART_VERID_MINOR_WIDTH (8U) 124 #define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) 125 126 #define LPUART_VERID_MAJOR_MASK (0xFF000000U) 127 #define LPUART_VERID_MAJOR_SHIFT (24U) 128 #define LPUART_VERID_MAJOR_WIDTH (8U) 129 #define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) 130 /*! @} */ 131 132 /*! @name PARAM - Parameter Register */ 133 /*! @{ */ 134 135 #define LPUART_PARAM_TXFIFO_MASK (0xFFU) 136 #define LPUART_PARAM_TXFIFO_SHIFT (0U) 137 #define LPUART_PARAM_TXFIFO_WIDTH (8U) 138 #define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) 139 140 #define LPUART_PARAM_RXFIFO_MASK (0xFF00U) 141 #define LPUART_PARAM_RXFIFO_SHIFT (8U) 142 #define LPUART_PARAM_RXFIFO_WIDTH (8U) 143 #define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) 144 /*! @} */ 145 146 /*! @name GLOBAL - LPUART Global Register */ 147 /*! @{ */ 148 149 #define LPUART_GLOBAL_RST_MASK (0x2U) 150 #define LPUART_GLOBAL_RST_SHIFT (1U) 151 #define LPUART_GLOBAL_RST_WIDTH (1U) 152 #define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) 153 /*! @} */ 154 155 /*! @name PINCFG - LPUART Pin Configuration Register */ 156 /*! @{ */ 157 158 #define LPUART_PINCFG_TRGSEL_MASK (0x3U) 159 #define LPUART_PINCFG_TRGSEL_SHIFT (0U) 160 #define LPUART_PINCFG_TRGSEL_WIDTH (2U) 161 #define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) 162 /*! @} */ 163 164 /*! @name BAUD - LPUART Baud Rate Register */ 165 /*! @{ */ 166 167 #define LPUART_BAUD_SBR_MASK (0x1FFFU) 168 #define LPUART_BAUD_SBR_SHIFT (0U) 169 #define LPUART_BAUD_SBR_WIDTH (13U) 170 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) 171 172 #define LPUART_BAUD_SBNS_MASK (0x2000U) 173 #define LPUART_BAUD_SBNS_SHIFT (13U) 174 #define LPUART_BAUD_SBNS_WIDTH (1U) 175 #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) 176 177 #define LPUART_BAUD_RXEDGIE_MASK (0x4000U) 178 #define LPUART_BAUD_RXEDGIE_SHIFT (14U) 179 #define LPUART_BAUD_RXEDGIE_WIDTH (1U) 180 #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) 181 182 #define LPUART_BAUD_LBKDIE_MASK (0x8000U) 183 #define LPUART_BAUD_LBKDIE_SHIFT (15U) 184 #define LPUART_BAUD_LBKDIE_WIDTH (1U) 185 #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) 186 187 #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) 188 #define LPUART_BAUD_RESYNCDIS_SHIFT (16U) 189 #define LPUART_BAUD_RESYNCDIS_WIDTH (1U) 190 #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) 191 192 #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) 193 #define LPUART_BAUD_BOTHEDGE_SHIFT (17U) 194 #define LPUART_BAUD_BOTHEDGE_WIDTH (1U) 195 #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) 196 197 #define LPUART_BAUD_MATCFG_MASK (0xC0000U) 198 #define LPUART_BAUD_MATCFG_SHIFT (18U) 199 #define LPUART_BAUD_MATCFG_WIDTH (2U) 200 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) 201 202 #define LPUART_BAUD_RIDMAE_MASK (0x100000U) 203 #define LPUART_BAUD_RIDMAE_SHIFT (20U) 204 #define LPUART_BAUD_RIDMAE_WIDTH (1U) 205 #define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) 206 207 #define LPUART_BAUD_RDMAE_MASK (0x200000U) 208 #define LPUART_BAUD_RDMAE_SHIFT (21U) 209 #define LPUART_BAUD_RDMAE_WIDTH (1U) 210 #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) 211 212 #define LPUART_BAUD_TDMAE_MASK (0x800000U) 213 #define LPUART_BAUD_TDMAE_SHIFT (23U) 214 #define LPUART_BAUD_TDMAE_WIDTH (1U) 215 #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) 216 217 #define LPUART_BAUD_OSR_MASK (0x1F000000U) 218 #define LPUART_BAUD_OSR_SHIFT (24U) 219 #define LPUART_BAUD_OSR_WIDTH (5U) 220 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) 221 222 #define LPUART_BAUD_M10_MASK (0x20000000U) 223 #define LPUART_BAUD_M10_SHIFT (29U) 224 #define LPUART_BAUD_M10_WIDTH (1U) 225 #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) 226 227 #define LPUART_BAUD_MAEN2_MASK (0x40000000U) 228 #define LPUART_BAUD_MAEN2_SHIFT (30U) 229 #define LPUART_BAUD_MAEN2_WIDTH (1U) 230 #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) 231 232 #define LPUART_BAUD_MAEN1_MASK (0x80000000U) 233 #define LPUART_BAUD_MAEN1_SHIFT (31U) 234 #define LPUART_BAUD_MAEN1_WIDTH (1U) 235 #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) 236 /*! @} */ 237 238 /*! @name STAT - LPUART Status Register */ 239 /*! @{ */ 240 241 #define LPUART_STAT_MA2F_MASK (0x4000U) 242 #define LPUART_STAT_MA2F_SHIFT (14U) 243 #define LPUART_STAT_MA2F_WIDTH (1U) 244 #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) 245 246 #define LPUART_STAT_MA1F_MASK (0x8000U) 247 #define LPUART_STAT_MA1F_SHIFT (15U) 248 #define LPUART_STAT_MA1F_WIDTH (1U) 249 #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) 250 251 #define LPUART_STAT_PF_MASK (0x10000U) 252 #define LPUART_STAT_PF_SHIFT (16U) 253 #define LPUART_STAT_PF_WIDTH (1U) 254 #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) 255 256 #define LPUART_STAT_FE_MASK (0x20000U) 257 #define LPUART_STAT_FE_SHIFT (17U) 258 #define LPUART_STAT_FE_WIDTH (1U) 259 #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) 260 261 #define LPUART_STAT_NF_MASK (0x40000U) 262 #define LPUART_STAT_NF_SHIFT (18U) 263 #define LPUART_STAT_NF_WIDTH (1U) 264 #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) 265 266 #define LPUART_STAT_OR_MASK (0x80000U) 267 #define LPUART_STAT_OR_SHIFT (19U) 268 #define LPUART_STAT_OR_WIDTH (1U) 269 #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) 270 271 #define LPUART_STAT_IDLE_MASK (0x100000U) 272 #define LPUART_STAT_IDLE_SHIFT (20U) 273 #define LPUART_STAT_IDLE_WIDTH (1U) 274 #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) 275 276 #define LPUART_STAT_RDRF_MASK (0x200000U) 277 #define LPUART_STAT_RDRF_SHIFT (21U) 278 #define LPUART_STAT_RDRF_WIDTH (1U) 279 #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) 280 281 #define LPUART_STAT_TC_MASK (0x400000U) 282 #define LPUART_STAT_TC_SHIFT (22U) 283 #define LPUART_STAT_TC_WIDTH (1U) 284 #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) 285 286 #define LPUART_STAT_TDRE_MASK (0x800000U) 287 #define LPUART_STAT_TDRE_SHIFT (23U) 288 #define LPUART_STAT_TDRE_WIDTH (1U) 289 #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) 290 291 #define LPUART_STAT_RAF_MASK (0x1000000U) 292 #define LPUART_STAT_RAF_SHIFT (24U) 293 #define LPUART_STAT_RAF_WIDTH (1U) 294 #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) 295 296 #define LPUART_STAT_LBKDE_MASK (0x2000000U) 297 #define LPUART_STAT_LBKDE_SHIFT (25U) 298 #define LPUART_STAT_LBKDE_WIDTH (1U) 299 #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) 300 301 #define LPUART_STAT_BRK13_MASK (0x4000000U) 302 #define LPUART_STAT_BRK13_SHIFT (26U) 303 #define LPUART_STAT_BRK13_WIDTH (1U) 304 #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) 305 306 #define LPUART_STAT_RWUID_MASK (0x8000000U) 307 #define LPUART_STAT_RWUID_SHIFT (27U) 308 #define LPUART_STAT_RWUID_WIDTH (1U) 309 #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) 310 311 #define LPUART_STAT_RXINV_MASK (0x10000000U) 312 #define LPUART_STAT_RXINV_SHIFT (28U) 313 #define LPUART_STAT_RXINV_WIDTH (1U) 314 #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) 315 316 #define LPUART_STAT_MSBF_MASK (0x20000000U) 317 #define LPUART_STAT_MSBF_SHIFT (29U) 318 #define LPUART_STAT_MSBF_WIDTH (1U) 319 #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) 320 321 #define LPUART_STAT_RXEDGIF_MASK (0x40000000U) 322 #define LPUART_STAT_RXEDGIF_SHIFT (30U) 323 #define LPUART_STAT_RXEDGIF_WIDTH (1U) 324 #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) 325 326 #define LPUART_STAT_LBKDIF_MASK (0x80000000U) 327 #define LPUART_STAT_LBKDIF_SHIFT (31U) 328 #define LPUART_STAT_LBKDIF_WIDTH (1U) 329 #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) 330 /*! @} */ 331 332 /*! @name CTRL - LPUART Control Register */ 333 /*! @{ */ 334 335 #define LPUART_CTRL_PT_MASK (0x1U) 336 #define LPUART_CTRL_PT_SHIFT (0U) 337 #define LPUART_CTRL_PT_WIDTH (1U) 338 #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) 339 340 #define LPUART_CTRL_PE_MASK (0x2U) 341 #define LPUART_CTRL_PE_SHIFT (1U) 342 #define LPUART_CTRL_PE_WIDTH (1U) 343 #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) 344 345 #define LPUART_CTRL_ILT_MASK (0x4U) 346 #define LPUART_CTRL_ILT_SHIFT (2U) 347 #define LPUART_CTRL_ILT_WIDTH (1U) 348 #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) 349 350 #define LPUART_CTRL_WAKE_MASK (0x8U) 351 #define LPUART_CTRL_WAKE_SHIFT (3U) 352 #define LPUART_CTRL_WAKE_WIDTH (1U) 353 #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) 354 355 #define LPUART_CTRL_M_MASK (0x10U) 356 #define LPUART_CTRL_M_SHIFT (4U) 357 #define LPUART_CTRL_M_WIDTH (1U) 358 #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) 359 360 #define LPUART_CTRL_RSRC_MASK (0x20U) 361 #define LPUART_CTRL_RSRC_SHIFT (5U) 362 #define LPUART_CTRL_RSRC_WIDTH (1U) 363 #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) 364 365 #define LPUART_CTRL_DOZEEN_MASK (0x40U) 366 #define LPUART_CTRL_DOZEEN_SHIFT (6U) 367 #define LPUART_CTRL_DOZEEN_WIDTH (1U) 368 #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) 369 370 #define LPUART_CTRL_LOOPS_MASK (0x80U) 371 #define LPUART_CTRL_LOOPS_SHIFT (7U) 372 #define LPUART_CTRL_LOOPS_WIDTH (1U) 373 #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) 374 375 #define LPUART_CTRL_IDLECFG_MASK (0x700U) 376 #define LPUART_CTRL_IDLECFG_SHIFT (8U) 377 #define LPUART_CTRL_IDLECFG_WIDTH (3U) 378 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) 379 380 #define LPUART_CTRL_M7_MASK (0x800U) 381 #define LPUART_CTRL_M7_SHIFT (11U) 382 #define LPUART_CTRL_M7_WIDTH (1U) 383 #define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) 384 385 #define LPUART_CTRL_MA2IE_MASK (0x4000U) 386 #define LPUART_CTRL_MA2IE_SHIFT (14U) 387 #define LPUART_CTRL_MA2IE_WIDTH (1U) 388 #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) 389 390 #define LPUART_CTRL_MA1IE_MASK (0x8000U) 391 #define LPUART_CTRL_MA1IE_SHIFT (15U) 392 #define LPUART_CTRL_MA1IE_WIDTH (1U) 393 #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) 394 395 #define LPUART_CTRL_SBK_MASK (0x10000U) 396 #define LPUART_CTRL_SBK_SHIFT (16U) 397 #define LPUART_CTRL_SBK_WIDTH (1U) 398 #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) 399 400 #define LPUART_CTRL_RWU_MASK (0x20000U) 401 #define LPUART_CTRL_RWU_SHIFT (17U) 402 #define LPUART_CTRL_RWU_WIDTH (1U) 403 #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) 404 405 #define LPUART_CTRL_RE_MASK (0x40000U) 406 #define LPUART_CTRL_RE_SHIFT (18U) 407 #define LPUART_CTRL_RE_WIDTH (1U) 408 #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) 409 410 #define LPUART_CTRL_TE_MASK (0x80000U) 411 #define LPUART_CTRL_TE_SHIFT (19U) 412 #define LPUART_CTRL_TE_WIDTH (1U) 413 #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) 414 415 #define LPUART_CTRL_ILIE_MASK (0x100000U) 416 #define LPUART_CTRL_ILIE_SHIFT (20U) 417 #define LPUART_CTRL_ILIE_WIDTH (1U) 418 #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) 419 420 #define LPUART_CTRL_RIE_MASK (0x200000U) 421 #define LPUART_CTRL_RIE_SHIFT (21U) 422 #define LPUART_CTRL_RIE_WIDTH (1U) 423 #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) 424 425 #define LPUART_CTRL_TCIE_MASK (0x400000U) 426 #define LPUART_CTRL_TCIE_SHIFT (22U) 427 #define LPUART_CTRL_TCIE_WIDTH (1U) 428 #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) 429 430 #define LPUART_CTRL_TIE_MASK (0x800000U) 431 #define LPUART_CTRL_TIE_SHIFT (23U) 432 #define LPUART_CTRL_TIE_WIDTH (1U) 433 #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) 434 435 #define LPUART_CTRL_PEIE_MASK (0x1000000U) 436 #define LPUART_CTRL_PEIE_SHIFT (24U) 437 #define LPUART_CTRL_PEIE_WIDTH (1U) 438 #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) 439 440 #define LPUART_CTRL_FEIE_MASK (0x2000000U) 441 #define LPUART_CTRL_FEIE_SHIFT (25U) 442 #define LPUART_CTRL_FEIE_WIDTH (1U) 443 #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) 444 445 #define LPUART_CTRL_NEIE_MASK (0x4000000U) 446 #define LPUART_CTRL_NEIE_SHIFT (26U) 447 #define LPUART_CTRL_NEIE_WIDTH (1U) 448 #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) 449 450 #define LPUART_CTRL_ORIE_MASK (0x8000000U) 451 #define LPUART_CTRL_ORIE_SHIFT (27U) 452 #define LPUART_CTRL_ORIE_WIDTH (1U) 453 #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) 454 455 #define LPUART_CTRL_TXINV_MASK (0x10000000U) 456 #define LPUART_CTRL_TXINV_SHIFT (28U) 457 #define LPUART_CTRL_TXINV_WIDTH (1U) 458 #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) 459 460 #define LPUART_CTRL_TXDIR_MASK (0x20000000U) 461 #define LPUART_CTRL_TXDIR_SHIFT (29U) 462 #define LPUART_CTRL_TXDIR_WIDTH (1U) 463 #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) 464 465 #define LPUART_CTRL_R9T8_MASK (0x40000000U) 466 #define LPUART_CTRL_R9T8_SHIFT (30U) 467 #define LPUART_CTRL_R9T8_WIDTH (1U) 468 #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) 469 470 #define LPUART_CTRL_R8T9_MASK (0x80000000U) 471 #define LPUART_CTRL_R8T9_SHIFT (31U) 472 #define LPUART_CTRL_R8T9_WIDTH (1U) 473 #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) 474 /*! @} */ 475 476 /*! @name DATA - LPUART Data Register */ 477 /*! @{ */ 478 479 #define LPUART_DATA_R0T0_MASK (0x1U) 480 #define LPUART_DATA_R0T0_SHIFT (0U) 481 #define LPUART_DATA_R0T0_WIDTH (1U) 482 #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) 483 484 #define LPUART_DATA_R1T1_MASK (0x2U) 485 #define LPUART_DATA_R1T1_SHIFT (1U) 486 #define LPUART_DATA_R1T1_WIDTH (1U) 487 #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) 488 489 #define LPUART_DATA_R2T2_MASK (0x4U) 490 #define LPUART_DATA_R2T2_SHIFT (2U) 491 #define LPUART_DATA_R2T2_WIDTH (1U) 492 #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) 493 494 #define LPUART_DATA_R3T3_MASK (0x8U) 495 #define LPUART_DATA_R3T3_SHIFT (3U) 496 #define LPUART_DATA_R3T3_WIDTH (1U) 497 #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) 498 499 #define LPUART_DATA_R4T4_MASK (0x10U) 500 #define LPUART_DATA_R4T4_SHIFT (4U) 501 #define LPUART_DATA_R4T4_WIDTH (1U) 502 #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) 503 504 #define LPUART_DATA_R5T5_MASK (0x20U) 505 #define LPUART_DATA_R5T5_SHIFT (5U) 506 #define LPUART_DATA_R5T5_WIDTH (1U) 507 #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) 508 509 #define LPUART_DATA_R6T6_MASK (0x40U) 510 #define LPUART_DATA_R6T6_SHIFT (6U) 511 #define LPUART_DATA_R6T6_WIDTH (1U) 512 #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) 513 514 #define LPUART_DATA_R7T7_MASK (0x80U) 515 #define LPUART_DATA_R7T7_SHIFT (7U) 516 #define LPUART_DATA_R7T7_WIDTH (1U) 517 #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) 518 519 #define LPUART_DATA_R8T8_MASK (0x100U) 520 #define LPUART_DATA_R8T8_SHIFT (8U) 521 #define LPUART_DATA_R8T8_WIDTH (1U) 522 #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) 523 524 #define LPUART_DATA_R9T9_MASK (0x200U) 525 #define LPUART_DATA_R9T9_SHIFT (9U) 526 #define LPUART_DATA_R9T9_WIDTH (1U) 527 #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) 528 529 #define LPUART_DATA_IDLINE_MASK (0x800U) 530 #define LPUART_DATA_IDLINE_SHIFT (11U) 531 #define LPUART_DATA_IDLINE_WIDTH (1U) 532 #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) 533 534 #define LPUART_DATA_RXEMPT_MASK (0x1000U) 535 #define LPUART_DATA_RXEMPT_SHIFT (12U) 536 #define LPUART_DATA_RXEMPT_WIDTH (1U) 537 #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) 538 539 #define LPUART_DATA_FRETSC_MASK (0x2000U) 540 #define LPUART_DATA_FRETSC_SHIFT (13U) 541 #define LPUART_DATA_FRETSC_WIDTH (1U) 542 #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) 543 544 #define LPUART_DATA_PARITYE_MASK (0x4000U) 545 #define LPUART_DATA_PARITYE_SHIFT (14U) 546 #define LPUART_DATA_PARITYE_WIDTH (1U) 547 #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) 548 549 #define LPUART_DATA_NOISY_MASK (0x8000U) 550 #define LPUART_DATA_NOISY_SHIFT (15U) 551 #define LPUART_DATA_NOISY_WIDTH (1U) 552 #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) 553 /*! @} */ 554 555 /*! @name MATCH - LPUART Match Address Register */ 556 /*! @{ */ 557 558 #define LPUART_MATCH_MA1_MASK (0x3FFU) 559 #define LPUART_MATCH_MA1_SHIFT (0U) 560 #define LPUART_MATCH_MA1_WIDTH (10U) 561 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) 562 563 #define LPUART_MATCH_MA2_MASK (0x3FF0000U) 564 #define LPUART_MATCH_MA2_SHIFT (16U) 565 #define LPUART_MATCH_MA2_WIDTH (10U) 566 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) 567 /*! @} */ 568 569 /*! @name MODIR - LPUART Modem IrDA Register */ 570 /*! @{ */ 571 572 #define LPUART_MODIR_TXCTSE_MASK (0x1U) 573 #define LPUART_MODIR_TXCTSE_SHIFT (0U) 574 #define LPUART_MODIR_TXCTSE_WIDTH (1U) 575 #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) 576 577 #define LPUART_MODIR_TXRTSE_MASK (0x2U) 578 #define LPUART_MODIR_TXRTSE_SHIFT (1U) 579 #define LPUART_MODIR_TXRTSE_WIDTH (1U) 580 #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) 581 582 #define LPUART_MODIR_TXRTSPOL_MASK (0x4U) 583 #define LPUART_MODIR_TXRTSPOL_SHIFT (2U) 584 #define LPUART_MODIR_TXRTSPOL_WIDTH (1U) 585 #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) 586 587 #define LPUART_MODIR_RXRTSE_MASK (0x8U) 588 #define LPUART_MODIR_RXRTSE_SHIFT (3U) 589 #define LPUART_MODIR_RXRTSE_WIDTH (1U) 590 #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) 591 592 #define LPUART_MODIR_TXCTSC_MASK (0x10U) 593 #define LPUART_MODIR_TXCTSC_SHIFT (4U) 594 #define LPUART_MODIR_TXCTSC_WIDTH (1U) 595 #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) 596 597 #define LPUART_MODIR_TXCTSSRC_MASK (0x20U) 598 #define LPUART_MODIR_TXCTSSRC_SHIFT (5U) 599 #define LPUART_MODIR_TXCTSSRC_WIDTH (1U) 600 #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) 601 602 #define LPUART_MODIR_RTSWATER_MASK (0x300U) 603 #define LPUART_MODIR_RTSWATER_SHIFT (8U) 604 #define LPUART_MODIR_RTSWATER_WIDTH (2U) 605 #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) 606 607 #define LPUART_MODIR_TNP_MASK (0x30000U) 608 #define LPUART_MODIR_TNP_SHIFT (16U) 609 #define LPUART_MODIR_TNP_WIDTH (2U) 610 #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) 611 612 #define LPUART_MODIR_IREN_MASK (0x40000U) 613 #define LPUART_MODIR_IREN_SHIFT (18U) 614 #define LPUART_MODIR_IREN_WIDTH (1U) 615 #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) 616 /*! @} */ 617 618 /*! @name FIFO - LPUART FIFO Register */ 619 /*! @{ */ 620 621 #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) 622 #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) 623 #define LPUART_FIFO_RXFIFOSIZE_WIDTH (3U) 624 #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) 625 626 #define LPUART_FIFO_RXFE_MASK (0x8U) 627 #define LPUART_FIFO_RXFE_SHIFT (3U) 628 #define LPUART_FIFO_RXFE_WIDTH (1U) 629 #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) 630 631 #define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) 632 #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) 633 #define LPUART_FIFO_TXFIFOSIZE_WIDTH (3U) 634 #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) 635 636 #define LPUART_FIFO_TXFE_MASK (0x80U) 637 #define LPUART_FIFO_TXFE_SHIFT (7U) 638 #define LPUART_FIFO_TXFE_WIDTH (1U) 639 #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) 640 641 #define LPUART_FIFO_RXUFE_MASK (0x100U) 642 #define LPUART_FIFO_RXUFE_SHIFT (8U) 643 #define LPUART_FIFO_RXUFE_WIDTH (1U) 644 #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) 645 646 #define LPUART_FIFO_TXOFE_MASK (0x200U) 647 #define LPUART_FIFO_TXOFE_SHIFT (9U) 648 #define LPUART_FIFO_TXOFE_WIDTH (1U) 649 #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) 650 651 #define LPUART_FIFO_RXIDEN_MASK (0x1C00U) 652 #define LPUART_FIFO_RXIDEN_SHIFT (10U) 653 #define LPUART_FIFO_RXIDEN_WIDTH (3U) 654 #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) 655 656 #define LPUART_FIFO_RXFLUSH_MASK (0x4000U) 657 #define LPUART_FIFO_RXFLUSH_SHIFT (14U) 658 #define LPUART_FIFO_RXFLUSH_WIDTH (1U) 659 #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) 660 661 #define LPUART_FIFO_TXFLUSH_MASK (0x8000U) 662 #define LPUART_FIFO_TXFLUSH_SHIFT (15U) 663 #define LPUART_FIFO_TXFLUSH_WIDTH (1U) 664 #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) 665 666 #define LPUART_FIFO_RXUF_MASK (0x10000U) 667 #define LPUART_FIFO_RXUF_SHIFT (16U) 668 #define LPUART_FIFO_RXUF_WIDTH (1U) 669 #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) 670 671 #define LPUART_FIFO_TXOF_MASK (0x20000U) 672 #define LPUART_FIFO_TXOF_SHIFT (17U) 673 #define LPUART_FIFO_TXOF_WIDTH (1U) 674 #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) 675 676 #define LPUART_FIFO_RXEMPT_MASK (0x400000U) 677 #define LPUART_FIFO_RXEMPT_SHIFT (22U) 678 #define LPUART_FIFO_RXEMPT_WIDTH (1U) 679 #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) 680 681 #define LPUART_FIFO_TXEMPT_MASK (0x800000U) 682 #define LPUART_FIFO_TXEMPT_SHIFT (23U) 683 #define LPUART_FIFO_TXEMPT_WIDTH (1U) 684 #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) 685 /*! @} */ 686 687 /*! @name WATER - LPUART Watermark Register */ 688 /*! @{ */ 689 690 #define LPUART_WATER_TXWATER_MASK (0x3U) 691 #define LPUART_WATER_TXWATER_SHIFT (0U) 692 #define LPUART_WATER_TXWATER_WIDTH (2U) 693 #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) 694 695 #define LPUART_WATER_TXCOUNT_MASK (0x700U) 696 #define LPUART_WATER_TXCOUNT_SHIFT (8U) 697 #define LPUART_WATER_TXCOUNT_WIDTH (3U) 698 #define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) 699 700 #define LPUART_WATER_RXWATER_MASK (0x30000U) 701 #define LPUART_WATER_RXWATER_SHIFT (16U) 702 #define LPUART_WATER_RXWATER_WIDTH (2U) 703 #define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) 704 705 #define LPUART_WATER_RXCOUNT_MASK (0x7000000U) 706 #define LPUART_WATER_RXCOUNT_SHIFT (24U) 707 #define LPUART_WATER_RXCOUNT_WIDTH (3U) 708 #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) 709 /*! @} */ 710 711 /*! 712 * @} 713 */ /* end of group LPUART_Register_Masks */ 714 715 /*! 716 * @} 717 */ /* end of group LPUART_Peripheral_Access_Layer */ 718 719 #endif /* #if !defined(S32K118_LPUART_H_) */ 720
