1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K118_DMA.h 10 * @version 1.1 11 * @date 2022-01-24 12 * @brief Peripheral Access Layer for S32K118_DMA 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K118_DMA_H_) /* Check if memory map has not been already included */ 58 #define S32K118_DMA_H_ 59 60 #include "S32K118_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- DMA Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer 68 * @{ 69 */ 70 71 /** DMA - Size of Registers Arrays */ 72 #define DMA_DCHPRI_COUNT 4u 73 #define DMA_TCD_COUNT 4u 74 75 /** DMA - Register Layout Typedef */ 76 typedef struct { 77 __IO uint32_t CR; /**< Control, offset: 0x0 */ 78 __I uint32_t ES; /**< Error Status, offset: 0x4 */ 79 uint8_t RESERVED_0[4]; 80 __IO uint32_t ERQ; /**< Enable Request, offset: 0xC */ 81 uint8_t RESERVED_1[4]; 82 __IO uint32_t EEI; /**< Enable Error Interrupt, offset: 0x14 */ 83 __O uint8_t CEEI; /**< Clear Enable Error Interrupt, offset: 0x18 */ 84 __O uint8_t SEEI; /**< Set Enable Error Interrupt, offset: 0x19 */ 85 __O uint8_t CERQ; /**< Clear Enable Request, offset: 0x1A */ 86 __O uint8_t SERQ; /**< Set Enable Request, offset: 0x1B */ 87 __O uint8_t CDNE; /**< Clear DONE Status Bit, offset: 0x1C */ 88 __O uint8_t SSRT; /**< Set START Bit, offset: 0x1D */ 89 __O uint8_t CERR; /**< Clear Error, offset: 0x1E */ 90 __O uint8_t CINT; /**< Clear Interrupt Request, offset: 0x1F */ 91 uint8_t RESERVED_2[4]; 92 __IO uint32_t INT; /**< Interrupt Request, offset: 0x24 */ 93 uint8_t RESERVED_3[4]; 94 __IO uint32_t ERR; /**< Error, offset: 0x2C */ 95 uint8_t RESERVED_4[4]; 96 __I uint32_t HRS; /**< Hardware Request Status, offset: 0x34 */ 97 uint8_t RESERVED_5[12]; 98 __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop, offset: 0x44 */ 99 uint8_t RESERVED_6[184]; 100 __IO uint8_t DCHPRI[DMA_DCHPRI_COUNT]; /**< Channel Priority, array offset: 0x100, array step: 0x1 */ 101 uint8_t RESERVED_7[3836]; 102 struct { /* offset: 0x1000, array step: 0x20 */ 103 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ 104 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ 105 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ 106 union { /* offset: 0x1008, array step: 0x20 */ 107 __IO uint32_t MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */ 108 __IO uint32_t MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ 109 __IO uint32_t MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */ 110 } NBYTES; 111 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ 112 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ 113 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ 114 union { /* offset: 0x1016, array step: 0x20 */ 115 __IO uint16_t ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ 116 __IO uint16_t ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ 117 } CITER; 118 __IO uint32_t DLASTSGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ 119 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ 120 union { /* offset: 0x101E, array step: 0x20 */ 121 __IO uint16_t ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ 122 __IO uint16_t ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ 123 } BITER; 124 } TCD[DMA_TCD_COUNT]; 125 } DMA_Type, *DMA_MemMapPtr; 126 127 /** Number of instances of the DMA module. */ 128 #define DMA_INSTANCE_COUNT (1u) 129 130 /* DMA - Peripheral instance base addresses */ 131 /** Peripheral DMA base address */ 132 #define IP_DMA_BASE (0x40008000u) 133 /** Peripheral DMA base pointer */ 134 #define IP_DMA ((DMA_Type *)IP_DMA_BASE) 135 /** Array initializer of DMA peripheral base addresses */ 136 #define IP_DMA_BASE_ADDRS { IP_DMA_BASE } 137 /** Array initializer of DMA peripheral base pointers */ 138 #define IP_DMA_BASE_PTRS { IP_DMA } 139 140 /* ---------------------------------------------------------------------------- 141 -- DMA Register Masks 142 ---------------------------------------------------------------------------- */ 143 144 /*! 145 * @addtogroup DMA_Register_Masks DMA Register Masks 146 * @{ 147 */ 148 149 /*! @name CR - Control */ 150 /*! @{ */ 151 152 #define DMA_CR_EDBG_MASK (0x2U) 153 #define DMA_CR_EDBG_SHIFT (1U) 154 #define DMA_CR_EDBG_WIDTH (1U) 155 #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) 156 157 #define DMA_CR_ERCA_MASK (0x4U) 158 #define DMA_CR_ERCA_SHIFT (2U) 159 #define DMA_CR_ERCA_WIDTH (1U) 160 #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) 161 162 #define DMA_CR_HOE_MASK (0x10U) 163 #define DMA_CR_HOE_SHIFT (4U) 164 #define DMA_CR_HOE_WIDTH (1U) 165 #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) 166 167 #define DMA_CR_HALT_MASK (0x20U) 168 #define DMA_CR_HALT_SHIFT (5U) 169 #define DMA_CR_HALT_WIDTH (1U) 170 #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) 171 172 #define DMA_CR_CLM_MASK (0x40U) 173 #define DMA_CR_CLM_SHIFT (6U) 174 #define DMA_CR_CLM_WIDTH (1U) 175 #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) 176 177 #define DMA_CR_EMLM_MASK (0x80U) 178 #define DMA_CR_EMLM_SHIFT (7U) 179 #define DMA_CR_EMLM_WIDTH (1U) 180 #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) 181 182 #define DMA_CR_ECX_MASK (0x10000U) 183 #define DMA_CR_ECX_SHIFT (16U) 184 #define DMA_CR_ECX_WIDTH (1U) 185 #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) 186 187 #define DMA_CR_CX_MASK (0x20000U) 188 #define DMA_CR_CX_SHIFT (17U) 189 #define DMA_CR_CX_WIDTH (1U) 190 #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) 191 192 #define DMA_CR_ACTIVE_MASK (0x80000000U) 193 #define DMA_CR_ACTIVE_SHIFT (31U) 194 #define DMA_CR_ACTIVE_WIDTH (1U) 195 #define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK) 196 /*! @} */ 197 198 /*! @name ES - Error Status */ 199 /*! @{ */ 200 201 #define DMA_ES_DBE_MASK (0x1U) 202 #define DMA_ES_DBE_SHIFT (0U) 203 #define DMA_ES_DBE_WIDTH (1U) 204 #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) 205 206 #define DMA_ES_SBE_MASK (0x2U) 207 #define DMA_ES_SBE_SHIFT (1U) 208 #define DMA_ES_SBE_WIDTH (1U) 209 #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) 210 211 #define DMA_ES_SGE_MASK (0x4U) 212 #define DMA_ES_SGE_SHIFT (2U) 213 #define DMA_ES_SGE_WIDTH (1U) 214 #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) 215 216 #define DMA_ES_NCE_MASK (0x8U) 217 #define DMA_ES_NCE_SHIFT (3U) 218 #define DMA_ES_NCE_WIDTH (1U) 219 #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) 220 221 #define DMA_ES_DOE_MASK (0x10U) 222 #define DMA_ES_DOE_SHIFT (4U) 223 #define DMA_ES_DOE_WIDTH (1U) 224 #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) 225 226 #define DMA_ES_DAE_MASK (0x20U) 227 #define DMA_ES_DAE_SHIFT (5U) 228 #define DMA_ES_DAE_WIDTH (1U) 229 #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) 230 231 #define DMA_ES_SOE_MASK (0x40U) 232 #define DMA_ES_SOE_SHIFT (6U) 233 #define DMA_ES_SOE_WIDTH (1U) 234 #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) 235 236 #define DMA_ES_SAE_MASK (0x80U) 237 #define DMA_ES_SAE_SHIFT (7U) 238 #define DMA_ES_SAE_WIDTH (1U) 239 #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) 240 241 #define DMA_ES_ERRCHN_MASK (0x300U) 242 #define DMA_ES_ERRCHN_SHIFT (8U) 243 #define DMA_ES_ERRCHN_WIDTH (2U) 244 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) 245 246 #define DMA_ES_CPE_MASK (0x4000U) 247 #define DMA_ES_CPE_SHIFT (14U) 248 #define DMA_ES_CPE_WIDTH (1U) 249 #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) 250 251 #define DMA_ES_ECX_MASK (0x10000U) 252 #define DMA_ES_ECX_SHIFT (16U) 253 #define DMA_ES_ECX_WIDTH (1U) 254 #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) 255 256 #define DMA_ES_VLD_MASK (0x80000000U) 257 #define DMA_ES_VLD_SHIFT (31U) 258 #define DMA_ES_VLD_WIDTH (1U) 259 #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) 260 /*! @} */ 261 262 /*! @name ERQ - Enable Request */ 263 /*! @{ */ 264 265 #define DMA_ERQ_ERQ0_MASK (0x1U) 266 #define DMA_ERQ_ERQ0_SHIFT (0U) 267 #define DMA_ERQ_ERQ0_WIDTH (1U) 268 #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) 269 270 #define DMA_ERQ_ERQ1_MASK (0x2U) 271 #define DMA_ERQ_ERQ1_SHIFT (1U) 272 #define DMA_ERQ_ERQ1_WIDTH (1U) 273 #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) 274 275 #define DMA_ERQ_ERQ2_MASK (0x4U) 276 #define DMA_ERQ_ERQ2_SHIFT (2U) 277 #define DMA_ERQ_ERQ2_WIDTH (1U) 278 #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) 279 280 #define DMA_ERQ_ERQ3_MASK (0x8U) 281 #define DMA_ERQ_ERQ3_SHIFT (3U) 282 #define DMA_ERQ_ERQ3_WIDTH (1U) 283 #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) 284 /*! @} */ 285 286 /*! @name EEI - Enable Error Interrupt */ 287 /*! @{ */ 288 289 #define DMA_EEI_EEI0_MASK (0x1U) 290 #define DMA_EEI_EEI0_SHIFT (0U) 291 #define DMA_EEI_EEI0_WIDTH (1U) 292 #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) 293 294 #define DMA_EEI_EEI1_MASK (0x2U) 295 #define DMA_EEI_EEI1_SHIFT (1U) 296 #define DMA_EEI_EEI1_WIDTH (1U) 297 #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) 298 299 #define DMA_EEI_EEI2_MASK (0x4U) 300 #define DMA_EEI_EEI2_SHIFT (2U) 301 #define DMA_EEI_EEI2_WIDTH (1U) 302 #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) 303 304 #define DMA_EEI_EEI3_MASK (0x8U) 305 #define DMA_EEI_EEI3_SHIFT (3U) 306 #define DMA_EEI_EEI3_WIDTH (1U) 307 #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) 308 /*! @} */ 309 310 /*! @name CEEI - Clear Enable Error Interrupt */ 311 /*! @{ */ 312 313 #define DMA_CEEI_CEEI_MASK (0x3U) 314 #define DMA_CEEI_CEEI_SHIFT (0U) 315 #define DMA_CEEI_CEEI_WIDTH (2U) 316 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) 317 318 #define DMA_CEEI_CAEE_MASK (0x40U) 319 #define DMA_CEEI_CAEE_SHIFT (6U) 320 #define DMA_CEEI_CAEE_WIDTH (1U) 321 #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) 322 323 #define DMA_CEEI_NOP_MASK (0x80U) 324 #define DMA_CEEI_NOP_SHIFT (7U) 325 #define DMA_CEEI_NOP_WIDTH (1U) 326 #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) 327 /*! @} */ 328 329 /*! @name SEEI - Set Enable Error Interrupt */ 330 /*! @{ */ 331 332 #define DMA_SEEI_SEEI_MASK (0x3U) 333 #define DMA_SEEI_SEEI_SHIFT (0U) 334 #define DMA_SEEI_SEEI_WIDTH (2U) 335 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) 336 337 #define DMA_SEEI_SAEE_MASK (0x40U) 338 #define DMA_SEEI_SAEE_SHIFT (6U) 339 #define DMA_SEEI_SAEE_WIDTH (1U) 340 #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) 341 342 #define DMA_SEEI_NOP_MASK (0x80U) 343 #define DMA_SEEI_NOP_SHIFT (7U) 344 #define DMA_SEEI_NOP_WIDTH (1U) 345 #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) 346 /*! @} */ 347 348 /*! @name CERQ - Clear Enable Request */ 349 /*! @{ */ 350 351 #define DMA_CERQ_CERQ_MASK (0x3U) 352 #define DMA_CERQ_CERQ_SHIFT (0U) 353 #define DMA_CERQ_CERQ_WIDTH (2U) 354 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) 355 356 #define DMA_CERQ_CAER_MASK (0x40U) 357 #define DMA_CERQ_CAER_SHIFT (6U) 358 #define DMA_CERQ_CAER_WIDTH (1U) 359 #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) 360 361 #define DMA_CERQ_NOP_MASK (0x80U) 362 #define DMA_CERQ_NOP_SHIFT (7U) 363 #define DMA_CERQ_NOP_WIDTH (1U) 364 #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) 365 /*! @} */ 366 367 /*! @name SERQ - Set Enable Request */ 368 /*! @{ */ 369 370 #define DMA_SERQ_SERQ_MASK (0x3U) 371 #define DMA_SERQ_SERQ_SHIFT (0U) 372 #define DMA_SERQ_SERQ_WIDTH (2U) 373 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) 374 375 #define DMA_SERQ_SAER_MASK (0x40U) 376 #define DMA_SERQ_SAER_SHIFT (6U) 377 #define DMA_SERQ_SAER_WIDTH (1U) 378 #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) 379 380 #define DMA_SERQ_NOP_MASK (0x80U) 381 #define DMA_SERQ_NOP_SHIFT (7U) 382 #define DMA_SERQ_NOP_WIDTH (1U) 383 #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) 384 /*! @} */ 385 386 /*! @name CDNE - Clear DONE Status Bit */ 387 /*! @{ */ 388 389 #define DMA_CDNE_CDNE_MASK (0x3U) 390 #define DMA_CDNE_CDNE_SHIFT (0U) 391 #define DMA_CDNE_CDNE_WIDTH (2U) 392 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) 393 394 #define DMA_CDNE_CADN_MASK (0x40U) 395 #define DMA_CDNE_CADN_SHIFT (6U) 396 #define DMA_CDNE_CADN_WIDTH (1U) 397 #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) 398 399 #define DMA_CDNE_NOP_MASK (0x80U) 400 #define DMA_CDNE_NOP_SHIFT (7U) 401 #define DMA_CDNE_NOP_WIDTH (1U) 402 #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) 403 /*! @} */ 404 405 /*! @name SSRT - Set START Bit */ 406 /*! @{ */ 407 408 #define DMA_SSRT_SSRT_MASK (0x3U) 409 #define DMA_SSRT_SSRT_SHIFT (0U) 410 #define DMA_SSRT_SSRT_WIDTH (2U) 411 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) 412 413 #define DMA_SSRT_SAST_MASK (0x40U) 414 #define DMA_SSRT_SAST_SHIFT (6U) 415 #define DMA_SSRT_SAST_WIDTH (1U) 416 #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) 417 418 #define DMA_SSRT_NOP_MASK (0x80U) 419 #define DMA_SSRT_NOP_SHIFT (7U) 420 #define DMA_SSRT_NOP_WIDTH (1U) 421 #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) 422 /*! @} */ 423 424 /*! @name CERR - Clear Error */ 425 /*! @{ */ 426 427 #define DMA_CERR_CERR_MASK (0x3U) 428 #define DMA_CERR_CERR_SHIFT (0U) 429 #define DMA_CERR_CERR_WIDTH (2U) 430 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) 431 432 #define DMA_CERR_CAEI_MASK (0x40U) 433 #define DMA_CERR_CAEI_SHIFT (6U) 434 #define DMA_CERR_CAEI_WIDTH (1U) 435 #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) 436 437 #define DMA_CERR_NOP_MASK (0x80U) 438 #define DMA_CERR_NOP_SHIFT (7U) 439 #define DMA_CERR_NOP_WIDTH (1U) 440 #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) 441 /*! @} */ 442 443 /*! @name CINT - Clear Interrupt Request */ 444 /*! @{ */ 445 446 #define DMA_CINT_CINT_MASK (0x3U) 447 #define DMA_CINT_CINT_SHIFT (0U) 448 #define DMA_CINT_CINT_WIDTH (2U) 449 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) 450 451 #define DMA_CINT_CAIR_MASK (0x40U) 452 #define DMA_CINT_CAIR_SHIFT (6U) 453 #define DMA_CINT_CAIR_WIDTH (1U) 454 #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) 455 456 #define DMA_CINT_NOP_MASK (0x80U) 457 #define DMA_CINT_NOP_SHIFT (7U) 458 #define DMA_CINT_NOP_WIDTH (1U) 459 #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) 460 /*! @} */ 461 462 /*! @name INT - Interrupt Request */ 463 /*! @{ */ 464 465 #define DMA_INT_INT0_MASK (0x1U) 466 #define DMA_INT_INT0_SHIFT (0U) 467 #define DMA_INT_INT0_WIDTH (1U) 468 #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) 469 470 #define DMA_INT_INT1_MASK (0x2U) 471 #define DMA_INT_INT1_SHIFT (1U) 472 #define DMA_INT_INT1_WIDTH (1U) 473 #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) 474 475 #define DMA_INT_INT2_MASK (0x4U) 476 #define DMA_INT_INT2_SHIFT (2U) 477 #define DMA_INT_INT2_WIDTH (1U) 478 #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) 479 480 #define DMA_INT_INT3_MASK (0x8U) 481 #define DMA_INT_INT3_SHIFT (3U) 482 #define DMA_INT_INT3_WIDTH (1U) 483 #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) 484 /*! @} */ 485 486 /*! @name ERR - Error */ 487 /*! @{ */ 488 489 #define DMA_ERR_ERR0_MASK (0x1U) 490 #define DMA_ERR_ERR0_SHIFT (0U) 491 #define DMA_ERR_ERR0_WIDTH (1U) 492 #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) 493 494 #define DMA_ERR_ERR1_MASK (0x2U) 495 #define DMA_ERR_ERR1_SHIFT (1U) 496 #define DMA_ERR_ERR1_WIDTH (1U) 497 #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) 498 499 #define DMA_ERR_ERR2_MASK (0x4U) 500 #define DMA_ERR_ERR2_SHIFT (2U) 501 #define DMA_ERR_ERR2_WIDTH (1U) 502 #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) 503 504 #define DMA_ERR_ERR3_MASK (0x8U) 505 #define DMA_ERR_ERR3_SHIFT (3U) 506 #define DMA_ERR_ERR3_WIDTH (1U) 507 #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) 508 /*! @} */ 509 510 /*! @name HRS - Hardware Request Status */ 511 /*! @{ */ 512 513 #define DMA_HRS_HRS0_MASK (0x1U) 514 #define DMA_HRS_HRS0_SHIFT (0U) 515 #define DMA_HRS_HRS0_WIDTH (1U) 516 #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) 517 518 #define DMA_HRS_HRS1_MASK (0x2U) 519 #define DMA_HRS_HRS1_SHIFT (1U) 520 #define DMA_HRS_HRS1_WIDTH (1U) 521 #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) 522 523 #define DMA_HRS_HRS2_MASK (0x4U) 524 #define DMA_HRS_HRS2_SHIFT (2U) 525 #define DMA_HRS_HRS2_WIDTH (1U) 526 #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) 527 528 #define DMA_HRS_HRS3_MASK (0x8U) 529 #define DMA_HRS_HRS3_SHIFT (3U) 530 #define DMA_HRS_HRS3_WIDTH (1U) 531 #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) 532 /*! @} */ 533 534 /*! @name EARS - Enable Asynchronous Request in Stop */ 535 /*! @{ */ 536 537 #define DMA_EARS_EDREQ_0_MASK (0x1U) 538 #define DMA_EARS_EDREQ_0_SHIFT (0U) 539 #define DMA_EARS_EDREQ_0_WIDTH (1U) 540 #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) 541 542 #define DMA_EARS_EDREQ_1_MASK (0x2U) 543 #define DMA_EARS_EDREQ_1_SHIFT (1U) 544 #define DMA_EARS_EDREQ_1_WIDTH (1U) 545 #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) 546 547 #define DMA_EARS_EDREQ_2_MASK (0x4U) 548 #define DMA_EARS_EDREQ_2_SHIFT (2U) 549 #define DMA_EARS_EDREQ_2_WIDTH (1U) 550 #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) 551 552 #define DMA_EARS_EDREQ_3_MASK (0x8U) 553 #define DMA_EARS_EDREQ_3_SHIFT (3U) 554 #define DMA_EARS_EDREQ_3_WIDTH (1U) 555 #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) 556 /*! @} */ 557 558 /*! @name DCHPRI - Channel Priority */ 559 /*! @{ */ 560 561 #define DMA_DCHPRI_CHPRI_MASK (0x3U) 562 #define DMA_DCHPRI_CHPRI_SHIFT (0U) 563 #define DMA_DCHPRI_CHPRI_WIDTH (2U) 564 #define DMA_DCHPRI_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI_CHPRI_SHIFT)) & DMA_DCHPRI_CHPRI_MASK) 565 566 #define DMA_DCHPRI_DPA_MASK (0x40U) 567 #define DMA_DCHPRI_DPA_SHIFT (6U) 568 #define DMA_DCHPRI_DPA_WIDTH (1U) 569 #define DMA_DCHPRI_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI_DPA_SHIFT)) & DMA_DCHPRI_DPA_MASK) 570 571 #define DMA_DCHPRI_ECP_MASK (0x80U) 572 #define DMA_DCHPRI_ECP_SHIFT (7U) 573 #define DMA_DCHPRI_ECP_WIDTH (1U) 574 #define DMA_DCHPRI_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI_ECP_SHIFT)) & DMA_DCHPRI_ECP_MASK) 575 /*! @} */ 576 577 /*! @name TCD_SADDR - TCD Source Address */ 578 /*! @{ */ 579 580 #define DMA_TCD_SADDR_SADDR_MASK (0xFFFFFFFFU) 581 #define DMA_TCD_SADDR_SADDR_SHIFT (0U) 582 #define DMA_TCD_SADDR_SADDR_WIDTH (32U) 583 #define DMA_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK) 584 /*! @} */ 585 586 /*! @name TCD_SOFF - TCD Signed Source Address Offset */ 587 /*! @{ */ 588 589 #define DMA_TCD_SOFF_SOFF_MASK (0xFFFFU) 590 #define DMA_TCD_SOFF_SOFF_SHIFT (0U) 591 #define DMA_TCD_SOFF_SOFF_WIDTH (16U) 592 #define DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK) 593 /*! @} */ 594 595 /*! @name TCD_ATTR - TCD Transfer Attributes */ 596 /*! @{ */ 597 598 #define DMA_TCD_ATTR_DSIZE_MASK (0x7U) 599 #define DMA_TCD_ATTR_DSIZE_SHIFT (0U) 600 #define DMA_TCD_ATTR_DSIZE_WIDTH (3U) 601 #define DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK) 602 603 #define DMA_TCD_ATTR_DMOD_MASK (0xF8U) 604 #define DMA_TCD_ATTR_DMOD_SHIFT (3U) 605 #define DMA_TCD_ATTR_DMOD_WIDTH (5U) 606 #define DMA_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK) 607 608 #define DMA_TCD_ATTR_SSIZE_MASK (0x700U) 609 #define DMA_TCD_ATTR_SSIZE_SHIFT (8U) 610 #define DMA_TCD_ATTR_SSIZE_WIDTH (3U) 611 #define DMA_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK) 612 613 #define DMA_TCD_ATTR_SMOD_MASK (0xF800U) 614 #define DMA_TCD_ATTR_SMOD_SHIFT (11U) 615 #define DMA_TCD_ATTR_SMOD_WIDTH (5U) 616 #define DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK) 617 /*! @} */ 618 619 /*! @name TCD_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */ 620 /*! @{ */ 621 622 #define DMA_TCD_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) 623 #define DMA_TCD_NBYTES_MLNO_NBYTES_SHIFT (0U) 624 #define DMA_TCD_NBYTES_MLNO_NBYTES_WIDTH (32U) 625 #define DMA_TCD_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLNO_NBYTES_MASK) 626 /*! @} */ 627 628 /*! @name TCD_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */ 629 /*! @{ */ 630 631 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 632 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 633 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 634 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK) 635 636 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 637 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 638 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 639 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK) 640 641 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 642 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 643 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 644 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK) 645 /*! @} */ 646 647 /*! @name TCD_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */ 648 /*! @{ */ 649 650 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 651 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 652 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 653 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK) 654 655 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 656 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 657 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 658 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK) 659 660 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 661 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 662 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 663 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK) 664 665 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 666 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 667 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 668 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK) 669 /*! @} */ 670 671 /*! @name TCD_SLAST - TCD Last Source Address Adjustment */ 672 /*! @{ */ 673 674 #define DMA_TCD_SLAST_SLAST_MASK (0xFFFFFFFFU) 675 #define DMA_TCD_SLAST_SLAST_SHIFT (0U) 676 #define DMA_TCD_SLAST_SLAST_WIDTH (32U) 677 #define DMA_TCD_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SLAST_SHIFT)) & DMA_TCD_SLAST_SLAST_MASK) 678 /*! @} */ 679 680 /*! @name TCD_DADDR - TCD Destination Address */ 681 /*! @{ */ 682 683 #define DMA_TCD_DADDR_DADDR_MASK (0xFFFFFFFFU) 684 #define DMA_TCD_DADDR_DADDR_SHIFT (0U) 685 #define DMA_TCD_DADDR_DADDR_WIDTH (32U) 686 #define DMA_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK) 687 /*! @} */ 688 689 /*! @name TCD_DOFF - TCD Signed Destination Address Offset */ 690 /*! @{ */ 691 692 #define DMA_TCD_DOFF_DOFF_MASK (0xFFFFU) 693 #define DMA_TCD_DOFF_DOFF_SHIFT (0U) 694 #define DMA_TCD_DOFF_DOFF_WIDTH (16U) 695 #define DMA_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK) 696 /*! @} */ 697 698 /*! @name TCD_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ 699 /*! @{ */ 700 701 #define DMA_TCD_CITER_ELINKNO_CITER_MASK (0x7FFFU) 702 #define DMA_TCD_CITER_ELINKNO_CITER_SHIFT (0U) 703 #define DMA_TCD_CITER_ELINKNO_CITER_WIDTH (15U) 704 #define DMA_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK) 705 706 #define DMA_TCD_CITER_ELINKNO_ELINK_MASK (0x8000U) 707 #define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT (15U) 708 #define DMA_TCD_CITER_ELINKNO_ELINK_WIDTH (1U) 709 #define DMA_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK) 710 /*! @} */ 711 712 /*! @name TCD_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ 713 /*! @{ */ 714 715 #define DMA_TCD_CITER_ELINKYES_CITER_MASK (0x1FFU) 716 #define DMA_TCD_CITER_ELINKYES_CITER_SHIFT (0U) 717 #define DMA_TCD_CITER_ELINKYES_CITER_WIDTH (9U) 718 #define DMA_TCD_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK) 719 720 #define DMA_TCD_CITER_ELINKYES_LINKCH_MASK (0x600U) 721 #define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT (9U) 722 #define DMA_TCD_CITER_ELINKYES_LINKCH_WIDTH (2U) 723 #define DMA_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK) 724 725 #define DMA_TCD_CITER_ELINKYES_ELINK_MASK (0x8000U) 726 #define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT (15U) 727 #define DMA_TCD_CITER_ELINKYES_ELINK_WIDTH (1U) 728 #define DMA_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK) 729 /*! @} */ 730 731 /*! @name TCD_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ 732 /*! @{ */ 733 734 #define DMA_TCD_DLASTSGA_DLASTSGA_MASK (0xFFFFFFFFU) 735 #define DMA_TCD_DLASTSGA_DLASTSGA_SHIFT (0U) 736 #define DMA_TCD_DLASTSGA_DLASTSGA_WIDTH (32U) 737 #define DMA_TCD_DLASTSGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLASTSGA_DLASTSGA_SHIFT)) & DMA_TCD_DLASTSGA_DLASTSGA_MASK) 738 /*! @} */ 739 740 /*! @name TCD_CSR - TCD Control and Status */ 741 /*! @{ */ 742 743 #define DMA_TCD_CSR_START_MASK (0x1U) 744 #define DMA_TCD_CSR_START_SHIFT (0U) 745 #define DMA_TCD_CSR_START_WIDTH (1U) 746 #define DMA_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK) 747 748 #define DMA_TCD_CSR_INTMAJOR_MASK (0x2U) 749 #define DMA_TCD_CSR_INTMAJOR_SHIFT (1U) 750 #define DMA_TCD_CSR_INTMAJOR_WIDTH (1U) 751 #define DMA_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK) 752 753 #define DMA_TCD_CSR_INTHALF_MASK (0x4U) 754 #define DMA_TCD_CSR_INTHALF_SHIFT (2U) 755 #define DMA_TCD_CSR_INTHALF_WIDTH (1U) 756 #define DMA_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK) 757 758 #define DMA_TCD_CSR_DREQ_MASK (0x8U) 759 #define DMA_TCD_CSR_DREQ_SHIFT (3U) 760 #define DMA_TCD_CSR_DREQ_WIDTH (1U) 761 #define DMA_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK) 762 763 #define DMA_TCD_CSR_ESG_MASK (0x10U) 764 #define DMA_TCD_CSR_ESG_SHIFT (4U) 765 #define DMA_TCD_CSR_ESG_WIDTH (1U) 766 #define DMA_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK) 767 768 #define DMA_TCD_CSR_MAJORELINK_MASK (0x20U) 769 #define DMA_TCD_CSR_MAJORELINK_SHIFT (5U) 770 #define DMA_TCD_CSR_MAJORELINK_WIDTH (1U) 771 #define DMA_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK) 772 773 #define DMA_TCD_CSR_ACTIVE_MASK (0x40U) 774 #define DMA_TCD_CSR_ACTIVE_SHIFT (6U) 775 #define DMA_TCD_CSR_ACTIVE_WIDTH (1U) 776 #define DMA_TCD_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ACTIVE_SHIFT)) & DMA_TCD_CSR_ACTIVE_MASK) 777 778 #define DMA_TCD_CSR_DONE_MASK (0x80U) 779 #define DMA_TCD_CSR_DONE_SHIFT (7U) 780 #define DMA_TCD_CSR_DONE_WIDTH (1U) 781 #define DMA_TCD_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DONE_SHIFT)) & DMA_TCD_CSR_DONE_MASK) 782 783 #define DMA_TCD_CSR_MAJORLINKCH_MASK (0x300U) 784 #define DMA_TCD_CSR_MAJORLINKCH_SHIFT (8U) 785 #define DMA_TCD_CSR_MAJORLINKCH_WIDTH (2U) 786 #define DMA_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK) 787 788 #define DMA_TCD_CSR_BWC_MASK (0xC000U) 789 #define DMA_TCD_CSR_BWC_SHIFT (14U) 790 #define DMA_TCD_CSR_BWC_WIDTH (2U) 791 #define DMA_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK) 792 /*! @} */ 793 794 /*! @name TCD_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ 795 /*! @{ */ 796 797 #define DMA_TCD_BITER_ELINKNO_BITER_MASK (0x7FFFU) 798 #define DMA_TCD_BITER_ELINKNO_BITER_SHIFT (0U) 799 #define DMA_TCD_BITER_ELINKNO_BITER_WIDTH (15U) 800 #define DMA_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK) 801 802 #define DMA_TCD_BITER_ELINKNO_ELINK_MASK (0x8000U) 803 #define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT (15U) 804 #define DMA_TCD_BITER_ELINKNO_ELINK_WIDTH (1U) 805 #define DMA_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK) 806 /*! @} */ 807 808 /*! @name TCD_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ 809 /*! @{ */ 810 811 #define DMA_TCD_BITER_ELINKYES_BITER_MASK (0x1FFU) 812 #define DMA_TCD_BITER_ELINKYES_BITER_SHIFT (0U) 813 #define DMA_TCD_BITER_ELINKYES_BITER_WIDTH (9U) 814 #define DMA_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK) 815 816 #define DMA_TCD_BITER_ELINKYES_LINKCH_MASK (0x600U) 817 #define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT (9U) 818 #define DMA_TCD_BITER_ELINKYES_LINKCH_WIDTH (2U) 819 #define DMA_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK) 820 821 #define DMA_TCD_BITER_ELINKYES_ELINK_MASK (0x8000U) 822 #define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT (15U) 823 #define DMA_TCD_BITER_ELINKYES_ELINK_WIDTH (1U) 824 #define DMA_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK) 825 /*! @} */ 826 827 /*! 828 * @} 829 */ /* end of group DMA_Register_Masks */ 830 831 /*! 832 * @} 833 */ /* end of group DMA_Peripheral_Access_Layer */ 834 835 #endif /* #if !defined(S32K118_DMA_H_) */ 836
