1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K116_SIM.h 10 * @version 1.1 11 * @date 2022-01-21 12 * @brief Peripheral Access Layer for S32K116_SIM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K116_SIM_H_) /* Check if memory map has not been already included */ 58 #define S32K116_SIM_H_ 59 60 #include "S32K116_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SIM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SIM - Register Layout Typedef */ 72 typedef struct { 73 uint8_t RESERVED_0[4]; 74 __IO uint32_t CHIPCTL; /**< Chip Control register, offset: 0x4 */ 75 uint8_t RESERVED_1[4]; 76 __IO uint32_t FTMOPT0; /**< FTM Option Register 0, offset: 0xC */ 77 __IO uint32_t LPOCLKS; /**< LPO Clock Select Register, offset: 0x10 */ 78 uint8_t RESERVED_2[4]; 79 __IO uint32_t ADCOPT; /**< ADC Options Register, offset: 0x18 */ 80 __IO uint32_t FTMOPT1; /**< FTM Option Register 1, offset: 0x1C */ 81 __IO uint32_t MISCTRL0; /**< Miscellaneous control register 0, offset: 0x20 */ 82 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x24 */ 83 uint8_t RESERVED_3[24]; 84 __IO uint32_t PLATCGC; /**< Platform Clock Gating Control Register, offset: 0x40 */ 85 uint8_t RESERVED_4[8]; 86 __I uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x4C */ 87 uint8_t RESERVED_5[4]; 88 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x54 */ 89 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x58 */ 90 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x5C */ 91 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x60 */ 92 uint8_t RESERVED_6[8]; 93 __IO uint32_t MISCTRL1; /**< Miscellaneous Control register 1, offset: 0x6C */ 94 } SIM_Type, *SIM_MemMapPtr; 95 96 /** Number of instances of the SIM module. */ 97 #define SIM_INSTANCE_COUNT (1u) 98 99 /* SIM - Peripheral instance base addresses */ 100 /** Peripheral SIM base address */ 101 #define IP_SIM_BASE (0x40048000u) 102 /** Peripheral SIM base pointer */ 103 #define IP_SIM ((SIM_Type *)IP_SIM_BASE) 104 /** Array initializer of SIM peripheral base addresses */ 105 #define IP_SIM_BASE_ADDRS { IP_SIM_BASE } 106 /** Array initializer of SIM peripheral base pointers */ 107 #define IP_SIM_BASE_PTRS { IP_SIM } 108 109 /* ---------------------------------------------------------------------------- 110 -- SIM Register Masks 111 ---------------------------------------------------------------------------- */ 112 113 /*! 114 * @addtogroup SIM_Register_Masks SIM Register Masks 115 * @{ 116 */ 117 118 /*! @name CHIPCTL - Chip Control register */ 119 /*! @{ */ 120 121 #define SIM_CHIPCTL_CLKOUTSEL_MASK (0xF0U) 122 #define SIM_CHIPCTL_CLKOUTSEL_SHIFT (4U) 123 #define SIM_CHIPCTL_CLKOUTSEL_WIDTH (4U) 124 #define SIM_CHIPCTL_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_CLKOUTSEL_SHIFT)) & SIM_CHIPCTL_CLKOUTSEL_MASK) 125 126 #define SIM_CHIPCTL_CLKOUTDIV_MASK (0x700U) 127 #define SIM_CHIPCTL_CLKOUTDIV_SHIFT (8U) 128 #define SIM_CHIPCTL_CLKOUTDIV_WIDTH (3U) 129 #define SIM_CHIPCTL_CLKOUTDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_CLKOUTDIV_SHIFT)) & SIM_CHIPCTL_CLKOUTDIV_MASK) 130 131 #define SIM_CHIPCTL_CLKOUTEN_MASK (0x800U) 132 #define SIM_CHIPCTL_CLKOUTEN_SHIFT (11U) 133 #define SIM_CHIPCTL_CLKOUTEN_WIDTH (1U) 134 #define SIM_CHIPCTL_CLKOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_CLKOUTEN_SHIFT)) & SIM_CHIPCTL_CLKOUTEN_MASK) 135 136 #define SIM_CHIPCTL_ADC_SUPPLY_MASK (0x70000U) 137 #define SIM_CHIPCTL_ADC_SUPPLY_SHIFT (16U) 138 #define SIM_CHIPCTL_ADC_SUPPLY_WIDTH (3U) 139 #define SIM_CHIPCTL_ADC_SUPPLY(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_ADC_SUPPLY_SHIFT)) & SIM_CHIPCTL_ADC_SUPPLY_MASK) 140 141 #define SIM_CHIPCTL_ADC_SUPPLYEN_MASK (0x80000U) 142 #define SIM_CHIPCTL_ADC_SUPPLYEN_SHIFT (19U) 143 #define SIM_CHIPCTL_ADC_SUPPLYEN_WIDTH (1U) 144 #define SIM_CHIPCTL_ADC_SUPPLYEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_ADC_SUPPLYEN_SHIFT)) & SIM_CHIPCTL_ADC_SUPPLYEN_MASK) 145 146 #define SIM_CHIPCTL_SRAMU_RETEN_MASK (0x100000U) 147 #define SIM_CHIPCTL_SRAMU_RETEN_SHIFT (20U) 148 #define SIM_CHIPCTL_SRAMU_RETEN_WIDTH (1U) 149 #define SIM_CHIPCTL_SRAMU_RETEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_SRAMU_RETEN_SHIFT)) & SIM_CHIPCTL_SRAMU_RETEN_MASK) 150 151 #define SIM_CHIPCTL_SRAML_RETEN_MASK (0x200000U) 152 #define SIM_CHIPCTL_SRAML_RETEN_SHIFT (21U) 153 #define SIM_CHIPCTL_SRAML_RETEN_WIDTH (1U) 154 #define SIM_CHIPCTL_SRAML_RETEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_SRAML_RETEN_SHIFT)) & SIM_CHIPCTL_SRAML_RETEN_MASK) 155 /*! @} */ 156 157 /*! @name FTMOPT0 - FTM Option Register 0 */ 158 /*! @{ */ 159 160 #define SIM_FTMOPT0_FTM0FLTxSEL_MASK (0x7U) 161 #define SIM_FTMOPT0_FTM0FLTxSEL_SHIFT (0U) 162 #define SIM_FTMOPT0_FTM0FLTxSEL_WIDTH (3U) 163 #define SIM_FTMOPT0_FTM0FLTxSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT0_FTM0FLTxSEL_SHIFT)) & SIM_FTMOPT0_FTM0FLTxSEL_MASK) 164 165 #define SIM_FTMOPT0_FTM1FLTxSEL_MASK (0x70U) 166 #define SIM_FTMOPT0_FTM1FLTxSEL_SHIFT (4U) 167 #define SIM_FTMOPT0_FTM1FLTxSEL_WIDTH (3U) 168 #define SIM_FTMOPT0_FTM1FLTxSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT0_FTM1FLTxSEL_SHIFT)) & SIM_FTMOPT0_FTM1FLTxSEL_MASK) 169 170 #define SIM_FTMOPT0_FTM0CLKSEL_MASK (0x3000000U) 171 #define SIM_FTMOPT0_FTM0CLKSEL_SHIFT (24U) 172 #define SIM_FTMOPT0_FTM0CLKSEL_WIDTH (2U) 173 #define SIM_FTMOPT0_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT0_FTM0CLKSEL_SHIFT)) & SIM_FTMOPT0_FTM0CLKSEL_MASK) 174 175 #define SIM_FTMOPT0_FTM1CLKSEL_MASK (0xC000000U) 176 #define SIM_FTMOPT0_FTM1CLKSEL_SHIFT (26U) 177 #define SIM_FTMOPT0_FTM1CLKSEL_WIDTH (2U) 178 #define SIM_FTMOPT0_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT0_FTM1CLKSEL_SHIFT)) & SIM_FTMOPT0_FTM1CLKSEL_MASK) 179 /*! @} */ 180 181 /*! @name LPOCLKS - LPO Clock Select Register */ 182 /*! @{ */ 183 184 #define SIM_LPOCLKS_LPO1KCLKEN_MASK (0x1U) 185 #define SIM_LPOCLKS_LPO1KCLKEN_SHIFT (0U) 186 #define SIM_LPOCLKS_LPO1KCLKEN_WIDTH (1U) 187 #define SIM_LPOCLKS_LPO1KCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPOCLKS_LPO1KCLKEN_SHIFT)) & SIM_LPOCLKS_LPO1KCLKEN_MASK) 188 189 #define SIM_LPOCLKS_LPO32KCLKEN_MASK (0x2U) 190 #define SIM_LPOCLKS_LPO32KCLKEN_SHIFT (1U) 191 #define SIM_LPOCLKS_LPO32KCLKEN_WIDTH (1U) 192 #define SIM_LPOCLKS_LPO32KCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPOCLKS_LPO32KCLKEN_SHIFT)) & SIM_LPOCLKS_LPO32KCLKEN_MASK) 193 194 #define SIM_LPOCLKS_LPOCLKSEL_MASK (0xCU) 195 #define SIM_LPOCLKS_LPOCLKSEL_SHIFT (2U) 196 #define SIM_LPOCLKS_LPOCLKSEL_WIDTH (2U) 197 #define SIM_LPOCLKS_LPOCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPOCLKS_LPOCLKSEL_SHIFT)) & SIM_LPOCLKS_LPOCLKSEL_MASK) 198 199 #define SIM_LPOCLKS_RTCCLKSEL_MASK (0x30U) 200 #define SIM_LPOCLKS_RTCCLKSEL_SHIFT (4U) 201 #define SIM_LPOCLKS_RTCCLKSEL_WIDTH (2U) 202 #define SIM_LPOCLKS_RTCCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPOCLKS_RTCCLKSEL_SHIFT)) & SIM_LPOCLKS_RTCCLKSEL_MASK) 203 /*! @} */ 204 205 /*! @name ADCOPT - ADC Options Register */ 206 /*! @{ */ 207 208 #define SIM_ADCOPT_ADC0TRGSEL_MASK (0x1U) 209 #define SIM_ADCOPT_ADC0TRGSEL_SHIFT (0U) 210 #define SIM_ADCOPT_ADC0TRGSEL_WIDTH (1U) 211 #define SIM_ADCOPT_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC0TRGSEL_SHIFT)) & SIM_ADCOPT_ADC0TRGSEL_MASK) 212 213 #define SIM_ADCOPT_ADC0SWPRETRG_MASK (0xEU) 214 #define SIM_ADCOPT_ADC0SWPRETRG_SHIFT (1U) 215 #define SIM_ADCOPT_ADC0SWPRETRG_WIDTH (3U) 216 #define SIM_ADCOPT_ADC0SWPRETRG(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC0SWPRETRG_SHIFT)) & SIM_ADCOPT_ADC0SWPRETRG_MASK) 217 218 #define SIM_ADCOPT_ADC0PRETRGSEL_MASK (0x30U) 219 #define SIM_ADCOPT_ADC0PRETRGSEL_SHIFT (4U) 220 #define SIM_ADCOPT_ADC0PRETRGSEL_WIDTH (2U) 221 #define SIM_ADCOPT_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC0PRETRGSEL_SHIFT)) & SIM_ADCOPT_ADC0PRETRGSEL_MASK) 222 /*! @} */ 223 224 /*! @name FTMOPT1 - FTM Option Register 1 */ 225 /*! @{ */ 226 227 #define SIM_FTMOPT1_FTM0SYNCBIT_MASK (0x1U) 228 #define SIM_FTMOPT1_FTM0SYNCBIT_SHIFT (0U) 229 #define SIM_FTMOPT1_FTM0SYNCBIT_WIDTH (1U) 230 #define SIM_FTMOPT1_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM0SYNCBIT_SHIFT)) & SIM_FTMOPT1_FTM0SYNCBIT_MASK) 231 232 #define SIM_FTMOPT1_FTM1SYNCBIT_MASK (0x2U) 233 #define SIM_FTMOPT1_FTM1SYNCBIT_SHIFT (1U) 234 #define SIM_FTMOPT1_FTM1SYNCBIT_WIDTH (1U) 235 #define SIM_FTMOPT1_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM1SYNCBIT_SHIFT)) & SIM_FTMOPT1_FTM1SYNCBIT_MASK) 236 237 #define SIM_FTMOPT1_FTM1CH0SEL_MASK (0x30U) 238 #define SIM_FTMOPT1_FTM1CH0SEL_SHIFT (4U) 239 #define SIM_FTMOPT1_FTM1CH0SEL_WIDTH (2U) 240 #define SIM_FTMOPT1_FTM1CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM1CH0SEL_SHIFT)) & SIM_FTMOPT1_FTM1CH0SEL_MASK) 241 242 #define SIM_FTMOPT1_FTMGLDOK_MASK (0x8000U) 243 #define SIM_FTMOPT1_FTMGLDOK_SHIFT (15U) 244 #define SIM_FTMOPT1_FTMGLDOK_WIDTH (1U) 245 #define SIM_FTMOPT1_FTMGLDOK(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTMGLDOK_SHIFT)) & SIM_FTMOPT1_FTMGLDOK_MASK) 246 247 #define SIM_FTMOPT1_FTM0_OUTSEL_MASK (0xFF0000U) 248 #define SIM_FTMOPT1_FTM0_OUTSEL_SHIFT (16U) 249 #define SIM_FTMOPT1_FTM0_OUTSEL_WIDTH (8U) 250 #define SIM_FTMOPT1_FTM0_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM0_OUTSEL_SHIFT)) & SIM_FTMOPT1_FTM0_OUTSEL_MASK) 251 /*! @} */ 252 253 /*! @name MISCTRL0 - Miscellaneous control register 0 */ 254 /*! @{ */ 255 256 #define SIM_MISCTRL0_STOP1_MONITOR_MASK (0x200U) 257 #define SIM_MISCTRL0_STOP1_MONITOR_SHIFT (9U) 258 #define SIM_MISCTRL0_STOP1_MONITOR_WIDTH (1U) 259 #define SIM_MISCTRL0_STOP1_MONITOR(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_STOP1_MONITOR_SHIFT)) & SIM_MISCTRL0_STOP1_MONITOR_MASK) 260 261 #define SIM_MISCTRL0_STOP2_MONITOR_MASK (0x400U) 262 #define SIM_MISCTRL0_STOP2_MONITOR_SHIFT (10U) 263 #define SIM_MISCTRL0_STOP2_MONITOR_WIDTH (1U) 264 #define SIM_MISCTRL0_STOP2_MONITOR(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_STOP2_MONITOR_SHIFT)) & SIM_MISCTRL0_STOP2_MONITOR_MASK) 265 266 #define SIM_MISCTRL0_FTM0_OBE_CTRL_MASK (0x10000U) 267 #define SIM_MISCTRL0_FTM0_OBE_CTRL_SHIFT (16U) 268 #define SIM_MISCTRL0_FTM0_OBE_CTRL_WIDTH (1U) 269 #define SIM_MISCTRL0_FTM0_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_FTM0_OBE_CTRL_SHIFT)) & SIM_MISCTRL0_FTM0_OBE_CTRL_MASK) 270 271 #define SIM_MISCTRL0_FTM1_OBE_CTRL_MASK (0x20000U) 272 #define SIM_MISCTRL0_FTM1_OBE_CTRL_SHIFT (17U) 273 #define SIM_MISCTRL0_FTM1_OBE_CTRL_WIDTH (1U) 274 #define SIM_MISCTRL0_FTM1_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_FTM1_OBE_CTRL_SHIFT)) & SIM_MISCTRL0_FTM1_OBE_CTRL_MASK) 275 276 #define SIM_MISCTRL0_FTM2_OBE_CTRL_MASK (0x40000U) 277 #define SIM_MISCTRL0_FTM2_OBE_CTRL_SHIFT (18U) 278 #define SIM_MISCTRL0_FTM2_OBE_CTRL_WIDTH (1U) 279 #define SIM_MISCTRL0_FTM2_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_FTM2_OBE_CTRL_SHIFT)) & SIM_MISCTRL0_FTM2_OBE_CTRL_MASK) 280 281 #define SIM_MISCTRL0_FTM3_OBE_CTRL_MASK (0x80000U) 282 #define SIM_MISCTRL0_FTM3_OBE_CTRL_SHIFT (19U) 283 #define SIM_MISCTRL0_FTM3_OBE_CTRL_WIDTH (1U) 284 #define SIM_MISCTRL0_FTM3_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_FTM3_OBE_CTRL_SHIFT)) & SIM_MISCTRL0_FTM3_OBE_CTRL_MASK) 285 /*! @} */ 286 287 /*! @name SDID - System Device Identification Register */ 288 /*! @{ */ 289 290 #define SIM_SDID_FEATURES_MASK (0xFFU) 291 #define SIM_SDID_FEATURES_SHIFT (0U) 292 #define SIM_SDID_FEATURES_WIDTH (8U) 293 #define SIM_SDID_FEATURES(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FEATURES_SHIFT)) & SIM_SDID_FEATURES_MASK) 294 295 #define SIM_SDID_PACKAGE_MASK (0xF00U) 296 #define SIM_SDID_PACKAGE_SHIFT (8U) 297 #define SIM_SDID_PACKAGE_WIDTH (4U) 298 #define SIM_SDID_PACKAGE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PACKAGE_SHIFT)) & SIM_SDID_PACKAGE_MASK) 299 300 #define SIM_SDID_REVID_MASK (0xF000U) 301 #define SIM_SDID_REVID_SHIFT (12U) 302 #define SIM_SDID_REVID_WIDTH (4U) 303 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) 304 305 #define SIM_SDID_RAMSIZE_MASK (0xF0000U) 306 #define SIM_SDID_RAMSIZE_SHIFT (16U) 307 #define SIM_SDID_RAMSIZE_WIDTH (4U) 308 #define SIM_SDID_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_RAMSIZE_SHIFT)) & SIM_SDID_RAMSIZE_MASK) 309 310 #define SIM_SDID_DERIVATE_MASK (0xF00000U) 311 #define SIM_SDID_DERIVATE_SHIFT (20U) 312 #define SIM_SDID_DERIVATE_WIDTH (4U) 313 #define SIM_SDID_DERIVATE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DERIVATE_SHIFT)) & SIM_SDID_DERIVATE_MASK) 314 315 #define SIM_SDID_SUBSERIES_MASK (0xF000000U) 316 #define SIM_SDID_SUBSERIES_SHIFT (24U) 317 #define SIM_SDID_SUBSERIES_WIDTH (4U) 318 #define SIM_SDID_SUBSERIES(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBSERIES_SHIFT)) & SIM_SDID_SUBSERIES_MASK) 319 320 #define SIM_SDID_GENERATION_MASK (0xF0000000U) 321 #define SIM_SDID_GENERATION_SHIFT (28U) 322 #define SIM_SDID_GENERATION_WIDTH (4U) 323 #define SIM_SDID_GENERATION(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_GENERATION_SHIFT)) & SIM_SDID_GENERATION_MASK) 324 /*! @} */ 325 326 /*! @name PLATCGC - Platform Clock Gating Control Register */ 327 /*! @{ */ 328 329 #define SIM_PLATCGC_CGCMSCM_MASK (0x1U) 330 #define SIM_PLATCGC_CGCMSCM_SHIFT (0U) 331 #define SIM_PLATCGC_CGCMSCM_WIDTH (1U) 332 #define SIM_PLATCGC_CGCMSCM(x) (((uint32_t)(((uint32_t)(x)) << SIM_PLATCGC_CGCMSCM_SHIFT)) & SIM_PLATCGC_CGCMSCM_MASK) 333 334 #define SIM_PLATCGC_CGCMPU_MASK (0x2U) 335 #define SIM_PLATCGC_CGCMPU_SHIFT (1U) 336 #define SIM_PLATCGC_CGCMPU_WIDTH (1U) 337 #define SIM_PLATCGC_CGCMPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_PLATCGC_CGCMPU_SHIFT)) & SIM_PLATCGC_CGCMPU_MASK) 338 339 #define SIM_PLATCGC_CGCDMA_MASK (0x4U) 340 #define SIM_PLATCGC_CGCDMA_SHIFT (2U) 341 #define SIM_PLATCGC_CGCDMA_WIDTH (1U) 342 #define SIM_PLATCGC_CGCDMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_PLATCGC_CGCDMA_SHIFT)) & SIM_PLATCGC_CGCDMA_MASK) 343 344 #define SIM_PLATCGC_CGCERM_MASK (0x8U) 345 #define SIM_PLATCGC_CGCERM_SHIFT (3U) 346 #define SIM_PLATCGC_CGCERM_WIDTH (1U) 347 #define SIM_PLATCGC_CGCERM(x) (((uint32_t)(((uint32_t)(x)) << SIM_PLATCGC_CGCERM_SHIFT)) & SIM_PLATCGC_CGCERM_MASK) 348 349 #define SIM_PLATCGC_CGCEIM_MASK (0x10U) 350 #define SIM_PLATCGC_CGCEIM_SHIFT (4U) 351 #define SIM_PLATCGC_CGCEIM_WIDTH (1U) 352 #define SIM_PLATCGC_CGCEIM(x) (((uint32_t)(((uint32_t)(x)) << SIM_PLATCGC_CGCEIM_SHIFT)) & SIM_PLATCGC_CGCEIM_MASK) 353 354 #define SIM_PLATCGC_CGCGPIO_MASK (0x20U) 355 #define SIM_PLATCGC_CGCGPIO_SHIFT (5U) 356 #define SIM_PLATCGC_CGCGPIO_WIDTH (1U) 357 #define SIM_PLATCGC_CGCGPIO(x) (((uint32_t)(((uint32_t)(x)) << SIM_PLATCGC_CGCGPIO_SHIFT)) & SIM_PLATCGC_CGCGPIO_MASK) 358 /*! @} */ 359 360 /*! @name FCFG1 - Flash Configuration Register 1 */ 361 /*! @{ */ 362 363 #define SIM_FCFG1_DEPART_MASK (0xF000U) 364 #define SIM_FCFG1_DEPART_SHIFT (12U) 365 #define SIM_FCFG1_DEPART_WIDTH (4U) 366 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK) 367 368 #define SIM_FCFG1_EEERAMSIZE_MASK (0xF0000U) 369 #define SIM_FCFG1_EEERAMSIZE_SHIFT (16U) 370 #define SIM_FCFG1_EEERAMSIZE_WIDTH (4U) 371 #define SIM_FCFG1_EEERAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EEERAMSIZE_SHIFT)) & SIM_FCFG1_EEERAMSIZE_MASK) 372 /*! @} */ 373 374 /*! @name UIDH - Unique Identification Register High */ 375 /*! @{ */ 376 377 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) 378 #define SIM_UIDH_UID127_96_SHIFT (0U) 379 #define SIM_UIDH_UID127_96_WIDTH (32U) 380 #define SIM_UIDH_UID127_96(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK) 381 /*! @} */ 382 383 /*! @name UIDMH - Unique Identification Register Mid-High */ 384 /*! @{ */ 385 386 #define SIM_UIDMH_UID95_64_MASK (0xFFFFFFFFU) 387 #define SIM_UIDMH_UID95_64_SHIFT (0U) 388 #define SIM_UIDMH_UID95_64_WIDTH (32U) 389 #define SIM_UIDMH_UID95_64(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID95_64_SHIFT)) & SIM_UIDMH_UID95_64_MASK) 390 /*! @} */ 391 392 /*! @name UIDML - Unique Identification Register Mid Low */ 393 /*! @{ */ 394 395 #define SIM_UIDML_UID63_32_MASK (0xFFFFFFFFU) 396 #define SIM_UIDML_UID63_32_SHIFT (0U) 397 #define SIM_UIDML_UID63_32_WIDTH (32U) 398 #define SIM_UIDML_UID63_32(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID63_32_SHIFT)) & SIM_UIDML_UID63_32_MASK) 399 /*! @} */ 400 401 /*! @name UIDL - Unique Identification Register Low */ 402 /*! @{ */ 403 404 #define SIM_UIDL_UID31_0_MASK (0xFFFFFFFFU) 405 #define SIM_UIDL_UID31_0_SHIFT (0U) 406 #define SIM_UIDL_UID31_0_WIDTH (32U) 407 #define SIM_UIDL_UID31_0(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID31_0_SHIFT)) & SIM_UIDL_UID31_0_MASK) 408 /*! @} */ 409 410 /*! @name MISCTRL1 - Miscellaneous Control register 1 */ 411 /*! @{ */ 412 413 #define SIM_MISCTRL1_SW_TRG_MASK (0x1U) 414 #define SIM_MISCTRL1_SW_TRG_SHIFT (0U) 415 #define SIM_MISCTRL1_SW_TRG_WIDTH (1U) 416 #define SIM_MISCTRL1_SW_TRG(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SW_TRG_SHIFT)) & SIM_MISCTRL1_SW_TRG_MASK) 417 /*! @} */ 418 419 /*! 420 * @} 421 */ /* end of group SIM_Register_Masks */ 422 423 /*! 424 * @} 425 */ /* end of group SIM_Peripheral_Access_Layer */ 426 427 #endif /* #if !defined(S32K116_SIM_H_) */ 428
