1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K116_LPSPI.h 10 * @version 1.1 11 * @date 2022-01-21 12 * @brief Peripheral Access Layer for S32K116_LPSPI 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K116_LPSPI_H_) /* Check if memory map has not been already included */ 58 #define S32K116_LPSPI_H_ 59 60 #include "S32K116_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- LPSPI Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer 68 * @{ 69 */ 70 71 /** LPSPI - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ 74 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ 75 uint8_t RESERVED_0[8]; 76 __IO uint32_t CR; /**< Control Register, offset: 0x10 */ 77 __IO uint32_t SR; /**< Status Register, offset: 0x14 */ 78 __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x18 */ 79 __IO uint32_t DER; /**< DMA Enable Register, offset: 0x1C */ 80 __IO uint32_t CFGR0; /**< Configuration Register 0, offset: 0x20 */ 81 __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ 82 uint8_t RESERVED_1[8]; 83 __IO uint32_t DMR0; /**< Data Match Register 0, offset: 0x30 */ 84 __IO uint32_t DMR1; /**< Data Match Register 1, offset: 0x34 */ 85 uint8_t RESERVED_2[8]; 86 __IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ 87 uint8_t RESERVED_3[20]; 88 __IO uint32_t FCR; /**< The FIFO Control register contains the RXWATER and TXWATER control fields., offset: 0x58 */ 89 __I uint32_t FSR; /**< FIFO Status Register, offset: 0x5C */ 90 __IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */ 91 __O uint32_t TDR; /**< Transmit Data Register, offset: 0x64 */ 92 uint8_t RESERVED_4[8]; 93 __I uint32_t RSR; /**< Receive Status Register, offset: 0x70 */ 94 __I uint32_t RDR; /**< Receive Data Register, offset: 0x74 */ 95 } LPSPI_Type, *LPSPI_MemMapPtr; 96 97 /** Number of instances of the LPSPI module. */ 98 #define LPSPI_INSTANCE_COUNT (1u) 99 100 /* LPSPI - Peripheral instance base addresses */ 101 /** Peripheral LPSPI0 base address */ 102 #define IP_LPSPI0_BASE (0x4002C000u) 103 /** Peripheral LPSPI0 base pointer */ 104 #define IP_LPSPI0 ((LPSPI_Type *)IP_LPSPI0_BASE) 105 /** Array initializer of LPSPI peripheral base addresses */ 106 #define IP_LPSPI_BASE_ADDRS { IP_LPSPI0_BASE } 107 /** Array initializer of LPSPI peripheral base pointers */ 108 #define IP_LPSPI_BASE_PTRS { IP_LPSPI0 } 109 110 /* ---------------------------------------------------------------------------- 111 -- LPSPI Register Masks 112 ---------------------------------------------------------------------------- */ 113 114 /*! 115 * @addtogroup LPSPI_Register_Masks LPSPI Register Masks 116 * @{ 117 */ 118 119 /*! @name VERID - Version ID Register */ 120 /*! @{ */ 121 122 #define LPSPI_VERID_FEATURE_MASK (0xFFFFU) 123 #define LPSPI_VERID_FEATURE_SHIFT (0U) 124 #define LPSPI_VERID_FEATURE_WIDTH (16U) 125 #define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) 126 127 #define LPSPI_VERID_MINOR_MASK (0xFF0000U) 128 #define LPSPI_VERID_MINOR_SHIFT (16U) 129 #define LPSPI_VERID_MINOR_WIDTH (8U) 130 #define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) 131 132 #define LPSPI_VERID_MAJOR_MASK (0xFF000000U) 133 #define LPSPI_VERID_MAJOR_SHIFT (24U) 134 #define LPSPI_VERID_MAJOR_WIDTH (8U) 135 #define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) 136 /*! @} */ 137 138 /*! @name PARAM - Parameter Register */ 139 /*! @{ */ 140 141 #define LPSPI_PARAM_TXFIFO_MASK (0xFFU) 142 #define LPSPI_PARAM_TXFIFO_SHIFT (0U) 143 #define LPSPI_PARAM_TXFIFO_WIDTH (8U) 144 #define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) 145 146 #define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) 147 #define LPSPI_PARAM_RXFIFO_SHIFT (8U) 148 #define LPSPI_PARAM_RXFIFO_WIDTH (8U) 149 #define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) 150 /*! @} */ 151 152 /*! @name CR - Control Register */ 153 /*! @{ */ 154 155 #define LPSPI_CR_MEN_MASK (0x1U) 156 #define LPSPI_CR_MEN_SHIFT (0U) 157 #define LPSPI_CR_MEN_WIDTH (1U) 158 #define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) 159 160 #define LPSPI_CR_RST_MASK (0x2U) 161 #define LPSPI_CR_RST_SHIFT (1U) 162 #define LPSPI_CR_RST_WIDTH (1U) 163 #define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) 164 165 #define LPSPI_CR_DOZEN_MASK (0x4U) 166 #define LPSPI_CR_DOZEN_SHIFT (2U) 167 #define LPSPI_CR_DOZEN_WIDTH (1U) 168 #define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK) 169 170 #define LPSPI_CR_DBGEN_MASK (0x8U) 171 #define LPSPI_CR_DBGEN_SHIFT (3U) 172 #define LPSPI_CR_DBGEN_WIDTH (1U) 173 #define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) 174 175 #define LPSPI_CR_RTF_MASK (0x100U) 176 #define LPSPI_CR_RTF_SHIFT (8U) 177 #define LPSPI_CR_RTF_WIDTH (1U) 178 #define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) 179 180 #define LPSPI_CR_RRF_MASK (0x200U) 181 #define LPSPI_CR_RRF_SHIFT (9U) 182 #define LPSPI_CR_RRF_WIDTH (1U) 183 #define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) 184 /*! @} */ 185 186 /*! @name SR - Status Register */ 187 /*! @{ */ 188 189 #define LPSPI_SR_TDF_MASK (0x1U) 190 #define LPSPI_SR_TDF_SHIFT (0U) 191 #define LPSPI_SR_TDF_WIDTH (1U) 192 #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) 193 194 #define LPSPI_SR_RDF_MASK (0x2U) 195 #define LPSPI_SR_RDF_SHIFT (1U) 196 #define LPSPI_SR_RDF_WIDTH (1U) 197 #define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) 198 199 #define LPSPI_SR_WCF_MASK (0x100U) 200 #define LPSPI_SR_WCF_SHIFT (8U) 201 #define LPSPI_SR_WCF_WIDTH (1U) 202 #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) 203 204 #define LPSPI_SR_FCF_MASK (0x200U) 205 #define LPSPI_SR_FCF_SHIFT (9U) 206 #define LPSPI_SR_FCF_WIDTH (1U) 207 #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) 208 209 #define LPSPI_SR_TCF_MASK (0x400U) 210 #define LPSPI_SR_TCF_SHIFT (10U) 211 #define LPSPI_SR_TCF_WIDTH (1U) 212 #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) 213 214 #define LPSPI_SR_TEF_MASK (0x800U) 215 #define LPSPI_SR_TEF_SHIFT (11U) 216 #define LPSPI_SR_TEF_WIDTH (1U) 217 #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) 218 219 #define LPSPI_SR_REF_MASK (0x1000U) 220 #define LPSPI_SR_REF_SHIFT (12U) 221 #define LPSPI_SR_REF_WIDTH (1U) 222 #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) 223 224 #define LPSPI_SR_DMF_MASK (0x2000U) 225 #define LPSPI_SR_DMF_SHIFT (13U) 226 #define LPSPI_SR_DMF_WIDTH (1U) 227 #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) 228 229 #define LPSPI_SR_MBF_MASK (0x1000000U) 230 #define LPSPI_SR_MBF_SHIFT (24U) 231 #define LPSPI_SR_MBF_WIDTH (1U) 232 #define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) 233 /*! @} */ 234 235 /*! @name IER - Interrupt Enable Register */ 236 /*! @{ */ 237 238 #define LPSPI_IER_TDIE_MASK (0x1U) 239 #define LPSPI_IER_TDIE_SHIFT (0U) 240 #define LPSPI_IER_TDIE_WIDTH (1U) 241 #define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) 242 243 #define LPSPI_IER_RDIE_MASK (0x2U) 244 #define LPSPI_IER_RDIE_SHIFT (1U) 245 #define LPSPI_IER_RDIE_WIDTH (1U) 246 #define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) 247 248 #define LPSPI_IER_WCIE_MASK (0x100U) 249 #define LPSPI_IER_WCIE_SHIFT (8U) 250 #define LPSPI_IER_WCIE_WIDTH (1U) 251 #define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) 252 253 #define LPSPI_IER_FCIE_MASK (0x200U) 254 #define LPSPI_IER_FCIE_SHIFT (9U) 255 #define LPSPI_IER_FCIE_WIDTH (1U) 256 #define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) 257 258 #define LPSPI_IER_TCIE_MASK (0x400U) 259 #define LPSPI_IER_TCIE_SHIFT (10U) 260 #define LPSPI_IER_TCIE_WIDTH (1U) 261 #define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) 262 263 #define LPSPI_IER_TEIE_MASK (0x800U) 264 #define LPSPI_IER_TEIE_SHIFT (11U) 265 #define LPSPI_IER_TEIE_WIDTH (1U) 266 #define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) 267 268 #define LPSPI_IER_REIE_MASK (0x1000U) 269 #define LPSPI_IER_REIE_SHIFT (12U) 270 #define LPSPI_IER_REIE_WIDTH (1U) 271 #define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) 272 273 #define LPSPI_IER_DMIE_MASK (0x2000U) 274 #define LPSPI_IER_DMIE_SHIFT (13U) 275 #define LPSPI_IER_DMIE_WIDTH (1U) 276 #define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) 277 /*! @} */ 278 279 /*! @name DER - DMA Enable Register */ 280 /*! @{ */ 281 282 #define LPSPI_DER_TDDE_MASK (0x1U) 283 #define LPSPI_DER_TDDE_SHIFT (0U) 284 #define LPSPI_DER_TDDE_WIDTH (1U) 285 #define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) 286 287 #define LPSPI_DER_RDDE_MASK (0x2U) 288 #define LPSPI_DER_RDDE_SHIFT (1U) 289 #define LPSPI_DER_RDDE_WIDTH (1U) 290 #define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) 291 /*! @} */ 292 293 /*! @name CFGR0 - Configuration Register 0 */ 294 /*! @{ */ 295 296 #define LPSPI_CFGR0_HREN_MASK (0x1U) 297 #define LPSPI_CFGR0_HREN_SHIFT (0U) 298 #define LPSPI_CFGR0_HREN_WIDTH (1U) 299 #define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) 300 301 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) 302 #define LPSPI_CFGR0_HRPOL_SHIFT (1U) 303 #define LPSPI_CFGR0_HRPOL_WIDTH (1U) 304 #define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) 305 306 #define LPSPI_CFGR0_HRSEL_MASK (0x4U) 307 #define LPSPI_CFGR0_HRSEL_SHIFT (2U) 308 #define LPSPI_CFGR0_HRSEL_WIDTH (1U) 309 #define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) 310 311 #define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) 312 #define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) 313 #define LPSPI_CFGR0_CIRFIFO_WIDTH (1U) 314 #define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) 315 316 #define LPSPI_CFGR0_RDMO_MASK (0x200U) 317 #define LPSPI_CFGR0_RDMO_SHIFT (9U) 318 #define LPSPI_CFGR0_RDMO_WIDTH (1U) 319 #define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) 320 /*! @} */ 321 322 /*! @name CFGR1 - Configuration Register 1 */ 323 /*! @{ */ 324 325 #define LPSPI_CFGR1_MASTER_MASK (0x1U) 326 #define LPSPI_CFGR1_MASTER_SHIFT (0U) 327 #define LPSPI_CFGR1_MASTER_WIDTH (1U) 328 #define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) 329 330 #define LPSPI_CFGR1_SAMPLE_MASK (0x2U) 331 #define LPSPI_CFGR1_SAMPLE_SHIFT (1U) 332 #define LPSPI_CFGR1_SAMPLE_WIDTH (1U) 333 #define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) 334 335 #define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) 336 #define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) 337 #define LPSPI_CFGR1_AUTOPCS_WIDTH (1U) 338 #define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) 339 340 #define LPSPI_CFGR1_NOSTALL_MASK (0x8U) 341 #define LPSPI_CFGR1_NOSTALL_SHIFT (3U) 342 #define LPSPI_CFGR1_NOSTALL_WIDTH (1U) 343 #define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) 344 345 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) 346 #define LPSPI_CFGR1_PCSPOL_SHIFT (8U) 347 #define LPSPI_CFGR1_PCSPOL_WIDTH (4U) 348 #define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) 349 350 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) 351 #define LPSPI_CFGR1_MATCFG_SHIFT (16U) 352 #define LPSPI_CFGR1_MATCFG_WIDTH (3U) 353 #define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) 354 355 #define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) 356 #define LPSPI_CFGR1_PINCFG_SHIFT (24U) 357 #define LPSPI_CFGR1_PINCFG_WIDTH (2U) 358 #define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) 359 360 #define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) 361 #define LPSPI_CFGR1_OUTCFG_SHIFT (26U) 362 #define LPSPI_CFGR1_OUTCFG_WIDTH (1U) 363 #define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) 364 365 #define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) 366 #define LPSPI_CFGR1_PCSCFG_SHIFT (27U) 367 #define LPSPI_CFGR1_PCSCFG_WIDTH (1U) 368 #define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) 369 /*! @} */ 370 371 /*! @name DMR0 - Data Match Register 0 */ 372 /*! @{ */ 373 374 #define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) 375 #define LPSPI_DMR0_MATCH0_SHIFT (0U) 376 #define LPSPI_DMR0_MATCH0_WIDTH (32U) 377 #define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) 378 /*! @} */ 379 380 /*! @name DMR1 - Data Match Register 1 */ 381 /*! @{ */ 382 383 #define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) 384 #define LPSPI_DMR1_MATCH1_SHIFT (0U) 385 #define LPSPI_DMR1_MATCH1_WIDTH (32U) 386 #define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) 387 /*! @} */ 388 389 /*! @name CCR - Clock Configuration Register */ 390 /*! @{ */ 391 392 #define LPSPI_CCR_SCKDIV_MASK (0xFFU) 393 #define LPSPI_CCR_SCKDIV_SHIFT (0U) 394 #define LPSPI_CCR_SCKDIV_WIDTH (8U) 395 #define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) 396 397 #define LPSPI_CCR_DBT_MASK (0xFF00U) 398 #define LPSPI_CCR_DBT_SHIFT (8U) 399 #define LPSPI_CCR_DBT_WIDTH (8U) 400 #define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) 401 402 #define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) 403 #define LPSPI_CCR_PCSSCK_SHIFT (16U) 404 #define LPSPI_CCR_PCSSCK_WIDTH (8U) 405 #define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) 406 407 #define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) 408 #define LPSPI_CCR_SCKPCS_SHIFT (24U) 409 #define LPSPI_CCR_SCKPCS_WIDTH (8U) 410 #define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) 411 /*! @} */ 412 413 /*! @name FCR - The FIFO Control register contains the RXWATER and TXWATER control fields. */ 414 /*! @{ */ 415 416 #define LPSPI_FCR_TXWATER_MASK (0x3U) 417 #define LPSPI_FCR_TXWATER_SHIFT (0U) 418 #define LPSPI_FCR_TXWATER_WIDTH (2U) 419 #define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) 420 421 #define LPSPI_FCR_RXWATER_MASK (0x30000U) 422 #define LPSPI_FCR_RXWATER_SHIFT (16U) 423 #define LPSPI_FCR_RXWATER_WIDTH (2U) 424 #define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) 425 /*! @} */ 426 427 /*! @name FSR - FIFO Status Register */ 428 /*! @{ */ 429 430 #define LPSPI_FSR_TXCOUNT_MASK (0x7U) 431 #define LPSPI_FSR_TXCOUNT_SHIFT (0U) 432 #define LPSPI_FSR_TXCOUNT_WIDTH (3U) 433 #define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) 434 435 #define LPSPI_FSR_RXCOUNT_MASK (0x70000U) 436 #define LPSPI_FSR_RXCOUNT_SHIFT (16U) 437 #define LPSPI_FSR_RXCOUNT_WIDTH (3U) 438 #define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) 439 /*! @} */ 440 441 /*! @name TCR - Transmit Command Register */ 442 /*! @{ */ 443 444 #define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) 445 #define LPSPI_TCR_FRAMESZ_SHIFT (0U) 446 #define LPSPI_TCR_FRAMESZ_WIDTH (12U) 447 #define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) 448 449 #define LPSPI_TCR_WIDTH_MASK (0x30000U) 450 #define LPSPI_TCR_WIDTH_SHIFT (16U) 451 #define LPSPI_TCR_WIDTH_WIDTH (2U) 452 #define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) 453 454 #define LPSPI_TCR_TXMSK_MASK (0x40000U) 455 #define LPSPI_TCR_TXMSK_SHIFT (18U) 456 #define LPSPI_TCR_TXMSK_WIDTH (1U) 457 #define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) 458 459 #define LPSPI_TCR_RXMSK_MASK (0x80000U) 460 #define LPSPI_TCR_RXMSK_SHIFT (19U) 461 #define LPSPI_TCR_RXMSK_WIDTH (1U) 462 #define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) 463 464 #define LPSPI_TCR_CONTC_MASK (0x100000U) 465 #define LPSPI_TCR_CONTC_SHIFT (20U) 466 #define LPSPI_TCR_CONTC_WIDTH (1U) 467 #define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) 468 469 #define LPSPI_TCR_CONT_MASK (0x200000U) 470 #define LPSPI_TCR_CONT_SHIFT (21U) 471 #define LPSPI_TCR_CONT_WIDTH (1U) 472 #define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) 473 474 #define LPSPI_TCR_BYSW_MASK (0x400000U) 475 #define LPSPI_TCR_BYSW_SHIFT (22U) 476 #define LPSPI_TCR_BYSW_WIDTH (1U) 477 #define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) 478 479 #define LPSPI_TCR_LSBF_MASK (0x800000U) 480 #define LPSPI_TCR_LSBF_SHIFT (23U) 481 #define LPSPI_TCR_LSBF_WIDTH (1U) 482 #define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) 483 484 #define LPSPI_TCR_PCS_MASK (0x3000000U) 485 #define LPSPI_TCR_PCS_SHIFT (24U) 486 #define LPSPI_TCR_PCS_WIDTH (2U) 487 #define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) 488 489 #define LPSPI_TCR_PRESCALE_MASK (0x38000000U) 490 #define LPSPI_TCR_PRESCALE_SHIFT (27U) 491 #define LPSPI_TCR_PRESCALE_WIDTH (3U) 492 #define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) 493 494 #define LPSPI_TCR_CPHA_MASK (0x40000000U) 495 #define LPSPI_TCR_CPHA_SHIFT (30U) 496 #define LPSPI_TCR_CPHA_WIDTH (1U) 497 #define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) 498 499 #define LPSPI_TCR_CPOL_MASK (0x80000000U) 500 #define LPSPI_TCR_CPOL_SHIFT (31U) 501 #define LPSPI_TCR_CPOL_WIDTH (1U) 502 #define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) 503 /*! @} */ 504 505 /*! @name TDR - Transmit Data Register */ 506 /*! @{ */ 507 508 #define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) 509 #define LPSPI_TDR_DATA_SHIFT (0U) 510 #define LPSPI_TDR_DATA_WIDTH (32U) 511 #define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) 512 /*! @} */ 513 514 /*! @name RSR - Receive Status Register */ 515 /*! @{ */ 516 517 #define LPSPI_RSR_SOF_MASK (0x1U) 518 #define LPSPI_RSR_SOF_SHIFT (0U) 519 #define LPSPI_RSR_SOF_WIDTH (1U) 520 #define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) 521 522 #define LPSPI_RSR_RXEMPTY_MASK (0x2U) 523 #define LPSPI_RSR_RXEMPTY_SHIFT (1U) 524 #define LPSPI_RSR_RXEMPTY_WIDTH (1U) 525 #define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) 526 /*! @} */ 527 528 /*! @name RDR - Receive Data Register */ 529 /*! @{ */ 530 531 #define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) 532 #define LPSPI_RDR_DATA_SHIFT (0U) 533 #define LPSPI_RDR_DATA_WIDTH (32U) 534 #define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) 535 /*! @} */ 536 537 /*! 538 * @} 539 */ /* end of group LPSPI_Register_Masks */ 540 541 /*! 542 * @} 543 */ /* end of group LPSPI_Peripheral_Access_Layer */ 544 545 #endif /* #if !defined(S32K116_LPSPI_H_) */ 546
