1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K116_LPI2C.h 10 * @version 1.1 11 * @date 2022-01-21 12 * @brief Peripheral Access Layer for S32K116_LPI2C 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K116_LPI2C_H_) /* Check if memory map has not been already included */ 58 #define S32K116_LPI2C_H_ 59 60 #include "S32K116_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- LPI2C Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer 68 * @{ 69 */ 70 71 /** LPI2C - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ 74 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ 75 uint8_t RESERVED_0[8]; 76 __IO uint32_t MCR; /**< Master Control Register, offset: 0x10 */ 77 __IO uint32_t MSR; /**< Master Status Register, offset: 0x14 */ 78 __IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x18 */ 79 __IO uint32_t MDER; /**< Master DMA Enable Register, offset: 0x1C */ 80 __IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */ 81 __IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */ 82 __IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */ 83 __IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */ 84 uint8_t RESERVED_1[16]; 85 __IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */ 86 uint8_t RESERVED_2[4]; 87 __IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */ 88 uint8_t RESERVED_3[4]; 89 __IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */ 90 uint8_t RESERVED_4[4]; 91 __IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */ 92 __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ 93 __O uint32_t MTDR; /**< Master Transmit Data Register, offset: 0x60 */ 94 uint8_t RESERVED_5[12]; 95 __I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */ 96 uint8_t RESERVED_6[156]; 97 __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ 98 __IO uint32_t SSR; /**< Slave Status Register, offset: 0x114 */ 99 __IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */ 100 __IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */ 101 uint8_t RESERVED_7[4]; 102 __IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */ 103 __IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */ 104 uint8_t RESERVED_8[20]; 105 __IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */ 106 uint8_t RESERVED_9[12]; 107 __I uint32_t SASR; /**< Slave Address Status Register, offset: 0x150 */ 108 __IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */ 109 uint8_t RESERVED_10[8]; 110 __O uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */ 111 uint8_t RESERVED_11[12]; 112 __I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */ 113 } LPI2C_Type, *LPI2C_MemMapPtr; 114 115 /** Number of instances of the LPI2C module. */ 116 #define LPI2C_INSTANCE_COUNT (1u) 117 118 /* LPI2C - Peripheral instance base addresses */ 119 /** Peripheral LPI2C0 base address */ 120 #define IP_LPI2C0_BASE (0x40066000u) 121 /** Peripheral LPI2C0 base pointer */ 122 #define IP_LPI2C0 ((LPI2C_Type *)IP_LPI2C0_BASE) 123 /** Array initializer of LPI2C peripheral base addresses */ 124 #define IP_LPI2C_BASE_ADDRS { IP_LPI2C0_BASE } 125 /** Array initializer of LPI2C peripheral base pointers */ 126 #define IP_LPI2C_BASE_PTRS { IP_LPI2C0 } 127 128 /* ---------------------------------------------------------------------------- 129 -- LPI2C Register Masks 130 ---------------------------------------------------------------------------- */ 131 132 /*! 133 * @addtogroup LPI2C_Register_Masks LPI2C Register Masks 134 * @{ 135 */ 136 137 /*! @name VERID - Version ID Register */ 138 /*! @{ */ 139 140 #define LPI2C_VERID_FEATURE_MASK (0xFFFFU) 141 #define LPI2C_VERID_FEATURE_SHIFT (0U) 142 #define LPI2C_VERID_FEATURE_WIDTH (16U) 143 #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) 144 145 #define LPI2C_VERID_MINOR_MASK (0xFF0000U) 146 #define LPI2C_VERID_MINOR_SHIFT (16U) 147 #define LPI2C_VERID_MINOR_WIDTH (8U) 148 #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) 149 150 #define LPI2C_VERID_MAJOR_MASK (0xFF000000U) 151 #define LPI2C_VERID_MAJOR_SHIFT (24U) 152 #define LPI2C_VERID_MAJOR_WIDTH (8U) 153 #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) 154 /*! @} */ 155 156 /*! @name PARAM - Parameter Register */ 157 /*! @{ */ 158 159 #define LPI2C_PARAM_MTXFIFO_MASK (0xFU) 160 #define LPI2C_PARAM_MTXFIFO_SHIFT (0U) 161 #define LPI2C_PARAM_MTXFIFO_WIDTH (4U) 162 #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) 163 164 #define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) 165 #define LPI2C_PARAM_MRXFIFO_SHIFT (8U) 166 #define LPI2C_PARAM_MRXFIFO_WIDTH (4U) 167 #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) 168 /*! @} */ 169 170 /*! @name MCR - Master Control Register */ 171 /*! @{ */ 172 173 #define LPI2C_MCR_MEN_MASK (0x1U) 174 #define LPI2C_MCR_MEN_SHIFT (0U) 175 #define LPI2C_MCR_MEN_WIDTH (1U) 176 #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) 177 178 #define LPI2C_MCR_RST_MASK (0x2U) 179 #define LPI2C_MCR_RST_SHIFT (1U) 180 #define LPI2C_MCR_RST_WIDTH (1U) 181 #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) 182 183 #define LPI2C_MCR_DOZEN_MASK (0x4U) 184 #define LPI2C_MCR_DOZEN_SHIFT (2U) 185 #define LPI2C_MCR_DOZEN_WIDTH (1U) 186 #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) 187 188 #define LPI2C_MCR_DBGEN_MASK (0x8U) 189 #define LPI2C_MCR_DBGEN_SHIFT (3U) 190 #define LPI2C_MCR_DBGEN_WIDTH (1U) 191 #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) 192 193 #define LPI2C_MCR_RTF_MASK (0x100U) 194 #define LPI2C_MCR_RTF_SHIFT (8U) 195 #define LPI2C_MCR_RTF_WIDTH (1U) 196 #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) 197 198 #define LPI2C_MCR_RRF_MASK (0x200U) 199 #define LPI2C_MCR_RRF_SHIFT (9U) 200 #define LPI2C_MCR_RRF_WIDTH (1U) 201 #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) 202 /*! @} */ 203 204 /*! @name MSR - Master Status Register */ 205 /*! @{ */ 206 207 #define LPI2C_MSR_TDF_MASK (0x1U) 208 #define LPI2C_MSR_TDF_SHIFT (0U) 209 #define LPI2C_MSR_TDF_WIDTH (1U) 210 #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) 211 212 #define LPI2C_MSR_RDF_MASK (0x2U) 213 #define LPI2C_MSR_RDF_SHIFT (1U) 214 #define LPI2C_MSR_RDF_WIDTH (1U) 215 #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) 216 217 #define LPI2C_MSR_EPF_MASK (0x100U) 218 #define LPI2C_MSR_EPF_SHIFT (8U) 219 #define LPI2C_MSR_EPF_WIDTH (1U) 220 #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) 221 222 #define LPI2C_MSR_SDF_MASK (0x200U) 223 #define LPI2C_MSR_SDF_SHIFT (9U) 224 #define LPI2C_MSR_SDF_WIDTH (1U) 225 #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) 226 227 #define LPI2C_MSR_NDF_MASK (0x400U) 228 #define LPI2C_MSR_NDF_SHIFT (10U) 229 #define LPI2C_MSR_NDF_WIDTH (1U) 230 #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) 231 232 #define LPI2C_MSR_ALF_MASK (0x800U) 233 #define LPI2C_MSR_ALF_SHIFT (11U) 234 #define LPI2C_MSR_ALF_WIDTH (1U) 235 #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) 236 237 #define LPI2C_MSR_FEF_MASK (0x1000U) 238 #define LPI2C_MSR_FEF_SHIFT (12U) 239 #define LPI2C_MSR_FEF_WIDTH (1U) 240 #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) 241 242 #define LPI2C_MSR_PLTF_MASK (0x2000U) 243 #define LPI2C_MSR_PLTF_SHIFT (13U) 244 #define LPI2C_MSR_PLTF_WIDTH (1U) 245 #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) 246 247 #define LPI2C_MSR_DMF_MASK (0x4000U) 248 #define LPI2C_MSR_DMF_SHIFT (14U) 249 #define LPI2C_MSR_DMF_WIDTH (1U) 250 #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) 251 252 #define LPI2C_MSR_MBF_MASK (0x1000000U) 253 #define LPI2C_MSR_MBF_SHIFT (24U) 254 #define LPI2C_MSR_MBF_WIDTH (1U) 255 #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) 256 257 #define LPI2C_MSR_BBF_MASK (0x2000000U) 258 #define LPI2C_MSR_BBF_SHIFT (25U) 259 #define LPI2C_MSR_BBF_WIDTH (1U) 260 #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) 261 /*! @} */ 262 263 /*! @name MIER - Master Interrupt Enable Register */ 264 /*! @{ */ 265 266 #define LPI2C_MIER_TDIE_MASK (0x1U) 267 #define LPI2C_MIER_TDIE_SHIFT (0U) 268 #define LPI2C_MIER_TDIE_WIDTH (1U) 269 #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) 270 271 #define LPI2C_MIER_RDIE_MASK (0x2U) 272 #define LPI2C_MIER_RDIE_SHIFT (1U) 273 #define LPI2C_MIER_RDIE_WIDTH (1U) 274 #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) 275 276 #define LPI2C_MIER_EPIE_MASK (0x100U) 277 #define LPI2C_MIER_EPIE_SHIFT (8U) 278 #define LPI2C_MIER_EPIE_WIDTH (1U) 279 #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) 280 281 #define LPI2C_MIER_SDIE_MASK (0x200U) 282 #define LPI2C_MIER_SDIE_SHIFT (9U) 283 #define LPI2C_MIER_SDIE_WIDTH (1U) 284 #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) 285 286 #define LPI2C_MIER_NDIE_MASK (0x400U) 287 #define LPI2C_MIER_NDIE_SHIFT (10U) 288 #define LPI2C_MIER_NDIE_WIDTH (1U) 289 #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) 290 291 #define LPI2C_MIER_ALIE_MASK (0x800U) 292 #define LPI2C_MIER_ALIE_SHIFT (11U) 293 #define LPI2C_MIER_ALIE_WIDTH (1U) 294 #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) 295 296 #define LPI2C_MIER_FEIE_MASK (0x1000U) 297 #define LPI2C_MIER_FEIE_SHIFT (12U) 298 #define LPI2C_MIER_FEIE_WIDTH (1U) 299 #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) 300 301 #define LPI2C_MIER_PLTIE_MASK (0x2000U) 302 #define LPI2C_MIER_PLTIE_SHIFT (13U) 303 #define LPI2C_MIER_PLTIE_WIDTH (1U) 304 #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) 305 306 #define LPI2C_MIER_DMIE_MASK (0x4000U) 307 #define LPI2C_MIER_DMIE_SHIFT (14U) 308 #define LPI2C_MIER_DMIE_WIDTH (1U) 309 #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) 310 /*! @} */ 311 312 /*! @name MDER - Master DMA Enable Register */ 313 /*! @{ */ 314 315 #define LPI2C_MDER_TDDE_MASK (0x1U) 316 #define LPI2C_MDER_TDDE_SHIFT (0U) 317 #define LPI2C_MDER_TDDE_WIDTH (1U) 318 #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) 319 320 #define LPI2C_MDER_RDDE_MASK (0x2U) 321 #define LPI2C_MDER_RDDE_SHIFT (1U) 322 #define LPI2C_MDER_RDDE_WIDTH (1U) 323 #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) 324 /*! @} */ 325 326 /*! @name MCFGR0 - Master Configuration Register 0 */ 327 /*! @{ */ 328 329 #define LPI2C_MCFGR0_HREN_MASK (0x1U) 330 #define LPI2C_MCFGR0_HREN_SHIFT (0U) 331 #define LPI2C_MCFGR0_HREN_WIDTH (1U) 332 #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) 333 334 #define LPI2C_MCFGR0_HRPOL_MASK (0x2U) 335 #define LPI2C_MCFGR0_HRPOL_SHIFT (1U) 336 #define LPI2C_MCFGR0_HRPOL_WIDTH (1U) 337 #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) 338 339 #define LPI2C_MCFGR0_HRSEL_MASK (0x4U) 340 #define LPI2C_MCFGR0_HRSEL_SHIFT (2U) 341 #define LPI2C_MCFGR0_HRSEL_WIDTH (1U) 342 #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) 343 344 #define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) 345 #define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) 346 #define LPI2C_MCFGR0_CIRFIFO_WIDTH (1U) 347 #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) 348 349 #define LPI2C_MCFGR0_RDMO_MASK (0x200U) 350 #define LPI2C_MCFGR0_RDMO_SHIFT (9U) 351 #define LPI2C_MCFGR0_RDMO_WIDTH (1U) 352 #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) 353 /*! @} */ 354 355 /*! @name MCFGR1 - Master Configuration Register 1 */ 356 /*! @{ */ 357 358 #define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) 359 #define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) 360 #define LPI2C_MCFGR1_PRESCALE_WIDTH (3U) 361 #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) 362 363 #define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) 364 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) 365 #define LPI2C_MCFGR1_AUTOSTOP_WIDTH (1U) 366 #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) 367 368 #define LPI2C_MCFGR1_IGNACK_MASK (0x200U) 369 #define LPI2C_MCFGR1_IGNACK_SHIFT (9U) 370 #define LPI2C_MCFGR1_IGNACK_WIDTH (1U) 371 #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) 372 373 #define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) 374 #define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) 375 #define LPI2C_MCFGR1_TIMECFG_WIDTH (1U) 376 #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) 377 378 #define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) 379 #define LPI2C_MCFGR1_MATCFG_SHIFT (16U) 380 #define LPI2C_MCFGR1_MATCFG_WIDTH (3U) 381 #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) 382 383 #define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) 384 #define LPI2C_MCFGR1_PINCFG_SHIFT (24U) 385 #define LPI2C_MCFGR1_PINCFG_WIDTH (3U) 386 #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) 387 /*! @} */ 388 389 /*! @name MCFGR2 - Master Configuration Register 2 */ 390 /*! @{ */ 391 392 #define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) 393 #define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) 394 #define LPI2C_MCFGR2_BUSIDLE_WIDTH (12U) 395 #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) 396 397 #define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) 398 #define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) 399 #define LPI2C_MCFGR2_FILTSCL_WIDTH (4U) 400 #define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) 401 402 #define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) 403 #define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) 404 #define LPI2C_MCFGR2_FILTSDA_WIDTH (4U) 405 #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) 406 /*! @} */ 407 408 /*! @name MCFGR3 - Master Configuration Register 3 */ 409 /*! @{ */ 410 411 #define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) 412 #define LPI2C_MCFGR3_PINLOW_SHIFT (8U) 413 #define LPI2C_MCFGR3_PINLOW_WIDTH (12U) 414 #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) 415 /*! @} */ 416 417 /*! @name MDMR - Master Data Match Register */ 418 /*! @{ */ 419 420 #define LPI2C_MDMR_MATCH0_MASK (0xFFU) 421 #define LPI2C_MDMR_MATCH0_SHIFT (0U) 422 #define LPI2C_MDMR_MATCH0_WIDTH (8U) 423 #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) 424 425 #define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) 426 #define LPI2C_MDMR_MATCH1_SHIFT (16U) 427 #define LPI2C_MDMR_MATCH1_WIDTH (8U) 428 #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) 429 /*! @} */ 430 431 /*! @name MCCR0 - Master Clock Configuration Register 0 */ 432 /*! @{ */ 433 434 #define LPI2C_MCCR0_CLKLO_MASK (0x3FU) 435 #define LPI2C_MCCR0_CLKLO_SHIFT (0U) 436 #define LPI2C_MCCR0_CLKLO_WIDTH (6U) 437 #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) 438 439 #define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) 440 #define LPI2C_MCCR0_CLKHI_SHIFT (8U) 441 #define LPI2C_MCCR0_CLKHI_WIDTH (6U) 442 #define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) 443 444 #define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) 445 #define LPI2C_MCCR0_SETHOLD_SHIFT (16U) 446 #define LPI2C_MCCR0_SETHOLD_WIDTH (6U) 447 #define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) 448 449 #define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) 450 #define LPI2C_MCCR0_DATAVD_SHIFT (24U) 451 #define LPI2C_MCCR0_DATAVD_WIDTH (6U) 452 #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) 453 /*! @} */ 454 455 /*! @name MCCR1 - Master Clock Configuration Register 1 */ 456 /*! @{ */ 457 458 #define LPI2C_MCCR1_CLKLO_MASK (0x3FU) 459 #define LPI2C_MCCR1_CLKLO_SHIFT (0U) 460 #define LPI2C_MCCR1_CLKLO_WIDTH (6U) 461 #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) 462 463 #define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) 464 #define LPI2C_MCCR1_CLKHI_SHIFT (8U) 465 #define LPI2C_MCCR1_CLKHI_WIDTH (6U) 466 #define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) 467 468 #define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) 469 #define LPI2C_MCCR1_SETHOLD_SHIFT (16U) 470 #define LPI2C_MCCR1_SETHOLD_WIDTH (6U) 471 #define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) 472 473 #define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) 474 #define LPI2C_MCCR1_DATAVD_SHIFT (24U) 475 #define LPI2C_MCCR1_DATAVD_WIDTH (6U) 476 #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) 477 /*! @} */ 478 479 /*! @name MFCR - Master FIFO Control Register */ 480 /*! @{ */ 481 482 #define LPI2C_MFCR_TXWATER_MASK (0x3U) 483 #define LPI2C_MFCR_TXWATER_SHIFT (0U) 484 #define LPI2C_MFCR_TXWATER_WIDTH (2U) 485 #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) 486 487 #define LPI2C_MFCR_RXWATER_MASK (0x30000U) 488 #define LPI2C_MFCR_RXWATER_SHIFT (16U) 489 #define LPI2C_MFCR_RXWATER_WIDTH (2U) 490 #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) 491 /*! @} */ 492 493 /*! @name MFSR - Master FIFO Status Register */ 494 /*! @{ */ 495 496 #define LPI2C_MFSR_TXCOUNT_MASK (0x7U) 497 #define LPI2C_MFSR_TXCOUNT_SHIFT (0U) 498 #define LPI2C_MFSR_TXCOUNT_WIDTH (3U) 499 #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) 500 501 #define LPI2C_MFSR_RXCOUNT_MASK (0x70000U) 502 #define LPI2C_MFSR_RXCOUNT_SHIFT (16U) 503 #define LPI2C_MFSR_RXCOUNT_WIDTH (3U) 504 #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) 505 /*! @} */ 506 507 /*! @name MTDR - Master Transmit Data Register */ 508 /*! @{ */ 509 510 #define LPI2C_MTDR_DATA_MASK (0xFFU) 511 #define LPI2C_MTDR_DATA_SHIFT (0U) 512 #define LPI2C_MTDR_DATA_WIDTH (8U) 513 #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) 514 515 #define LPI2C_MTDR_CMD_MASK (0x700U) 516 #define LPI2C_MTDR_CMD_SHIFT (8U) 517 #define LPI2C_MTDR_CMD_WIDTH (3U) 518 #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) 519 /*! @} */ 520 521 /*! @name MRDR - Master Receive Data Register */ 522 /*! @{ */ 523 524 #define LPI2C_MRDR_DATA_MASK (0xFFU) 525 #define LPI2C_MRDR_DATA_SHIFT (0U) 526 #define LPI2C_MRDR_DATA_WIDTH (8U) 527 #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) 528 529 #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) 530 #define LPI2C_MRDR_RXEMPTY_SHIFT (14U) 531 #define LPI2C_MRDR_RXEMPTY_WIDTH (1U) 532 #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) 533 /*! @} */ 534 535 /*! @name SCR - Slave Control Register */ 536 /*! @{ */ 537 538 #define LPI2C_SCR_SEN_MASK (0x1U) 539 #define LPI2C_SCR_SEN_SHIFT (0U) 540 #define LPI2C_SCR_SEN_WIDTH (1U) 541 #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) 542 543 #define LPI2C_SCR_RST_MASK (0x2U) 544 #define LPI2C_SCR_RST_SHIFT (1U) 545 #define LPI2C_SCR_RST_WIDTH (1U) 546 #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) 547 548 #define LPI2C_SCR_FILTEN_MASK (0x10U) 549 #define LPI2C_SCR_FILTEN_SHIFT (4U) 550 #define LPI2C_SCR_FILTEN_WIDTH (1U) 551 #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) 552 553 #define LPI2C_SCR_FILTDZ_MASK (0x20U) 554 #define LPI2C_SCR_FILTDZ_SHIFT (5U) 555 #define LPI2C_SCR_FILTDZ_WIDTH (1U) 556 #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) 557 558 #define LPI2C_SCR_RTF_MASK (0x100U) 559 #define LPI2C_SCR_RTF_SHIFT (8U) 560 #define LPI2C_SCR_RTF_WIDTH (1U) 561 #define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) 562 563 #define LPI2C_SCR_RRF_MASK (0x200U) 564 #define LPI2C_SCR_RRF_SHIFT (9U) 565 #define LPI2C_SCR_RRF_WIDTH (1U) 566 #define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) 567 /*! @} */ 568 569 /*! @name SSR - Slave Status Register */ 570 /*! @{ */ 571 572 #define LPI2C_SSR_TDF_MASK (0x1U) 573 #define LPI2C_SSR_TDF_SHIFT (0U) 574 #define LPI2C_SSR_TDF_WIDTH (1U) 575 #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) 576 577 #define LPI2C_SSR_RDF_MASK (0x2U) 578 #define LPI2C_SSR_RDF_SHIFT (1U) 579 #define LPI2C_SSR_RDF_WIDTH (1U) 580 #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) 581 582 #define LPI2C_SSR_AVF_MASK (0x4U) 583 #define LPI2C_SSR_AVF_SHIFT (2U) 584 #define LPI2C_SSR_AVF_WIDTH (1U) 585 #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) 586 587 #define LPI2C_SSR_TAF_MASK (0x8U) 588 #define LPI2C_SSR_TAF_SHIFT (3U) 589 #define LPI2C_SSR_TAF_WIDTH (1U) 590 #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) 591 592 #define LPI2C_SSR_RSF_MASK (0x100U) 593 #define LPI2C_SSR_RSF_SHIFT (8U) 594 #define LPI2C_SSR_RSF_WIDTH (1U) 595 #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) 596 597 #define LPI2C_SSR_SDF_MASK (0x200U) 598 #define LPI2C_SSR_SDF_SHIFT (9U) 599 #define LPI2C_SSR_SDF_WIDTH (1U) 600 #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) 601 602 #define LPI2C_SSR_BEF_MASK (0x400U) 603 #define LPI2C_SSR_BEF_SHIFT (10U) 604 #define LPI2C_SSR_BEF_WIDTH (1U) 605 #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) 606 607 #define LPI2C_SSR_FEF_MASK (0x800U) 608 #define LPI2C_SSR_FEF_SHIFT (11U) 609 #define LPI2C_SSR_FEF_WIDTH (1U) 610 #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) 611 612 #define LPI2C_SSR_AM0F_MASK (0x1000U) 613 #define LPI2C_SSR_AM0F_SHIFT (12U) 614 #define LPI2C_SSR_AM0F_WIDTH (1U) 615 #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) 616 617 #define LPI2C_SSR_AM1F_MASK (0x2000U) 618 #define LPI2C_SSR_AM1F_SHIFT (13U) 619 #define LPI2C_SSR_AM1F_WIDTH (1U) 620 #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) 621 622 #define LPI2C_SSR_GCF_MASK (0x4000U) 623 #define LPI2C_SSR_GCF_SHIFT (14U) 624 #define LPI2C_SSR_GCF_WIDTH (1U) 625 #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) 626 627 #define LPI2C_SSR_SARF_MASK (0x8000U) 628 #define LPI2C_SSR_SARF_SHIFT (15U) 629 #define LPI2C_SSR_SARF_WIDTH (1U) 630 #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) 631 632 #define LPI2C_SSR_SBF_MASK (0x1000000U) 633 #define LPI2C_SSR_SBF_SHIFT (24U) 634 #define LPI2C_SSR_SBF_WIDTH (1U) 635 #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) 636 637 #define LPI2C_SSR_BBF_MASK (0x2000000U) 638 #define LPI2C_SSR_BBF_SHIFT (25U) 639 #define LPI2C_SSR_BBF_WIDTH (1U) 640 #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) 641 /*! @} */ 642 643 /*! @name SIER - Slave Interrupt Enable Register */ 644 /*! @{ */ 645 646 #define LPI2C_SIER_TDIE_MASK (0x1U) 647 #define LPI2C_SIER_TDIE_SHIFT (0U) 648 #define LPI2C_SIER_TDIE_WIDTH (1U) 649 #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) 650 651 #define LPI2C_SIER_RDIE_MASK (0x2U) 652 #define LPI2C_SIER_RDIE_SHIFT (1U) 653 #define LPI2C_SIER_RDIE_WIDTH (1U) 654 #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) 655 656 #define LPI2C_SIER_AVIE_MASK (0x4U) 657 #define LPI2C_SIER_AVIE_SHIFT (2U) 658 #define LPI2C_SIER_AVIE_WIDTH (1U) 659 #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) 660 661 #define LPI2C_SIER_TAIE_MASK (0x8U) 662 #define LPI2C_SIER_TAIE_SHIFT (3U) 663 #define LPI2C_SIER_TAIE_WIDTH (1U) 664 #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) 665 666 #define LPI2C_SIER_RSIE_MASK (0x100U) 667 #define LPI2C_SIER_RSIE_SHIFT (8U) 668 #define LPI2C_SIER_RSIE_WIDTH (1U) 669 #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) 670 671 #define LPI2C_SIER_SDIE_MASK (0x200U) 672 #define LPI2C_SIER_SDIE_SHIFT (9U) 673 #define LPI2C_SIER_SDIE_WIDTH (1U) 674 #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) 675 676 #define LPI2C_SIER_BEIE_MASK (0x400U) 677 #define LPI2C_SIER_BEIE_SHIFT (10U) 678 #define LPI2C_SIER_BEIE_WIDTH (1U) 679 #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) 680 681 #define LPI2C_SIER_FEIE_MASK (0x800U) 682 #define LPI2C_SIER_FEIE_SHIFT (11U) 683 #define LPI2C_SIER_FEIE_WIDTH (1U) 684 #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) 685 686 #define LPI2C_SIER_AM0IE_MASK (0x1000U) 687 #define LPI2C_SIER_AM0IE_SHIFT (12U) 688 #define LPI2C_SIER_AM0IE_WIDTH (1U) 689 #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) 690 691 #define LPI2C_SIER_AM1F_MASK (0x2000U) 692 #define LPI2C_SIER_AM1F_SHIFT (13U) 693 #define LPI2C_SIER_AM1F_WIDTH (1U) 694 #define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK) 695 696 #define LPI2C_SIER_GCIE_MASK (0x4000U) 697 #define LPI2C_SIER_GCIE_SHIFT (14U) 698 #define LPI2C_SIER_GCIE_WIDTH (1U) 699 #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) 700 701 #define LPI2C_SIER_SARIE_MASK (0x8000U) 702 #define LPI2C_SIER_SARIE_SHIFT (15U) 703 #define LPI2C_SIER_SARIE_WIDTH (1U) 704 #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) 705 /*! @} */ 706 707 /*! @name SDER - Slave DMA Enable Register */ 708 /*! @{ */ 709 710 #define LPI2C_SDER_TDDE_MASK (0x1U) 711 #define LPI2C_SDER_TDDE_SHIFT (0U) 712 #define LPI2C_SDER_TDDE_WIDTH (1U) 713 #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) 714 715 #define LPI2C_SDER_RDDE_MASK (0x2U) 716 #define LPI2C_SDER_RDDE_SHIFT (1U) 717 #define LPI2C_SDER_RDDE_WIDTH (1U) 718 #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) 719 720 #define LPI2C_SDER_AVDE_MASK (0x4U) 721 #define LPI2C_SDER_AVDE_SHIFT (2U) 722 #define LPI2C_SDER_AVDE_WIDTH (1U) 723 #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) 724 /*! @} */ 725 726 /*! @name SCFGR1 - Slave Configuration Register 1 */ 727 /*! @{ */ 728 729 #define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) 730 #define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) 731 #define LPI2C_SCFGR1_ADRSTALL_WIDTH (1U) 732 #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) 733 734 #define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) 735 #define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) 736 #define LPI2C_SCFGR1_RXSTALL_WIDTH (1U) 737 #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) 738 739 #define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) 740 #define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) 741 #define LPI2C_SCFGR1_TXDSTALL_WIDTH (1U) 742 #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) 743 744 #define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) 745 #define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) 746 #define LPI2C_SCFGR1_ACKSTALL_WIDTH (1U) 747 #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) 748 749 #define LPI2C_SCFGR1_GCEN_MASK (0x100U) 750 #define LPI2C_SCFGR1_GCEN_SHIFT (8U) 751 #define LPI2C_SCFGR1_GCEN_WIDTH (1U) 752 #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) 753 754 #define LPI2C_SCFGR1_SAEN_MASK (0x200U) 755 #define LPI2C_SCFGR1_SAEN_SHIFT (9U) 756 #define LPI2C_SCFGR1_SAEN_WIDTH (1U) 757 #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) 758 759 #define LPI2C_SCFGR1_TXCFG_MASK (0x400U) 760 #define LPI2C_SCFGR1_TXCFG_SHIFT (10U) 761 #define LPI2C_SCFGR1_TXCFG_WIDTH (1U) 762 #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) 763 764 #define LPI2C_SCFGR1_RXCFG_MASK (0x800U) 765 #define LPI2C_SCFGR1_RXCFG_SHIFT (11U) 766 #define LPI2C_SCFGR1_RXCFG_WIDTH (1U) 767 #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) 768 769 #define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) 770 #define LPI2C_SCFGR1_IGNACK_SHIFT (12U) 771 #define LPI2C_SCFGR1_IGNACK_WIDTH (1U) 772 #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) 773 774 #define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) 775 #define LPI2C_SCFGR1_HSMEN_SHIFT (13U) 776 #define LPI2C_SCFGR1_HSMEN_WIDTH (1U) 777 #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) 778 779 #define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) 780 #define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) 781 #define LPI2C_SCFGR1_ADDRCFG_WIDTH (3U) 782 #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) 783 /*! @} */ 784 785 /*! @name SCFGR2 - Slave Configuration Register 2 */ 786 /*! @{ */ 787 788 #define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) 789 #define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) 790 #define LPI2C_SCFGR2_CLKHOLD_WIDTH (4U) 791 #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) 792 793 #define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) 794 #define LPI2C_SCFGR2_DATAVD_SHIFT (8U) 795 #define LPI2C_SCFGR2_DATAVD_WIDTH (6U) 796 #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) 797 798 #define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) 799 #define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) 800 #define LPI2C_SCFGR2_FILTSCL_WIDTH (4U) 801 #define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) 802 803 #define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) 804 #define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) 805 #define LPI2C_SCFGR2_FILTSDA_WIDTH (4U) 806 #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) 807 /*! @} */ 808 809 /*! @name SAMR - Slave Address Match Register */ 810 /*! @{ */ 811 812 #define LPI2C_SAMR_ADDR0_MASK (0x7FEU) 813 #define LPI2C_SAMR_ADDR0_SHIFT (1U) 814 #define LPI2C_SAMR_ADDR0_WIDTH (10U) 815 #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) 816 817 #define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) 818 #define LPI2C_SAMR_ADDR1_SHIFT (17U) 819 #define LPI2C_SAMR_ADDR1_WIDTH (10U) 820 #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) 821 /*! @} */ 822 823 /*! @name SASR - Slave Address Status Register */ 824 /*! @{ */ 825 826 #define LPI2C_SASR_RADDR_MASK (0x7FFU) 827 #define LPI2C_SASR_RADDR_SHIFT (0U) 828 #define LPI2C_SASR_RADDR_WIDTH (11U) 829 #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) 830 831 #define LPI2C_SASR_ANV_MASK (0x4000U) 832 #define LPI2C_SASR_ANV_SHIFT (14U) 833 #define LPI2C_SASR_ANV_WIDTH (1U) 834 #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) 835 /*! @} */ 836 837 /*! @name STAR - Slave Transmit ACK Register */ 838 /*! @{ */ 839 840 #define LPI2C_STAR_TXNACK_MASK (0x1U) 841 #define LPI2C_STAR_TXNACK_SHIFT (0U) 842 #define LPI2C_STAR_TXNACK_WIDTH (1U) 843 #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) 844 /*! @} */ 845 846 /*! @name STDR - Slave Transmit Data Register */ 847 /*! @{ */ 848 849 #define LPI2C_STDR_DATA_MASK (0xFFU) 850 #define LPI2C_STDR_DATA_SHIFT (0U) 851 #define LPI2C_STDR_DATA_WIDTH (8U) 852 #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) 853 /*! @} */ 854 855 /*! @name SRDR - Slave Receive Data Register */ 856 /*! @{ */ 857 858 #define LPI2C_SRDR_DATA_MASK (0xFFU) 859 #define LPI2C_SRDR_DATA_SHIFT (0U) 860 #define LPI2C_SRDR_DATA_WIDTH (8U) 861 #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) 862 863 #define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) 864 #define LPI2C_SRDR_RXEMPTY_SHIFT (14U) 865 #define LPI2C_SRDR_RXEMPTY_WIDTH (1U) 866 #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) 867 868 #define LPI2C_SRDR_SOF_MASK (0x8000U) 869 #define LPI2C_SRDR_SOF_SHIFT (15U) 870 #define LPI2C_SRDR_SOF_WIDTH (1U) 871 #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) 872 /*! @} */ 873 874 /*! 875 * @} 876 */ /* end of group LPI2C_Register_Masks */ 877 878 /*! 879 * @} 880 */ /* end of group LPI2C_Peripheral_Access_Layer */ 881 882 #endif /* #if !defined(S32K116_LPI2C_H_) */ 883
