1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K116_LMEM.h 10 * @version 1.0 11 * @date 2021-02-26 12 * @brief Peripheral Access Layer for S32K116_LMEM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K116_LMEM_H_) /* Check if memory map has not been already included */ 58 #define S32K116_LMEM_H_ 59 60 #include "S32K116_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- LMEM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** LMEM - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t PCCCR; /**< Cache control register, offset: 0x0 */ 74 __IO uint32_t PCCLCR; /**< Cache line control register, offset: 0x4 */ 75 __IO uint32_t PCCSAR; /**< Cache search address register, offset: 0x8 */ 76 __IO uint32_t PCCCVR; /**< Cache read/write value register, offset: 0xC */ 77 uint8_t RESERVED_0[16]; 78 __IO uint32_t PCCRMR; /**< Cache regions mode register, offset: 0x20 */ 79 } LMEM_Type, *LMEM_MemMapPtr; 80 81 /** Number of instances of the LMEM module. */ 82 #define LMEM_INSTANCE_COUNT (1u) 83 84 /* LMEM - Peripheral instance base addresses */ 85 /** Peripheral LMEM base address */ 86 #define IP_LMEM_BASE (0xE0082000u) 87 /** Peripheral LMEM base pointer */ 88 #define IP_LMEM ((LMEM_Type *)IP_LMEM_BASE) 89 /** Array initializer of LMEM peripheral base addresses */ 90 #define IP_LMEM_BASE_ADDRS { IP_LMEM_BASE } 91 /** Array initializer of LMEM peripheral base pointers */ 92 #define IP_LMEM_BASE_PTRS { IP_LMEM } 93 94 /* ---------------------------------------------------------------------------- 95 -- LMEM Register Masks 96 ---------------------------------------------------------------------------- */ 97 98 /*! 99 * @addtogroup LMEM_Register_Masks LMEM Register Masks 100 * @{ 101 */ 102 103 /*! @name PCCCR - Cache control register */ 104 /*! @{ */ 105 106 #define LMEM_PCCCR_ENCACHE_MASK (0x1U) 107 #define LMEM_PCCCR_ENCACHE_SHIFT (0U) 108 #define LMEM_PCCCR_ENCACHE_WIDTH (1U) 109 #define LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK) 110 111 #define LMEM_PCCCR_PCCR2_MASK (0x4U) 112 #define LMEM_PCCCR_PCCR2_SHIFT (2U) 113 #define LMEM_PCCCR_PCCR2_WIDTH (1U) 114 #define LMEM_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK) 115 116 #define LMEM_PCCCR_PCCR3_MASK (0x8U) 117 #define LMEM_PCCCR_PCCR3_SHIFT (3U) 118 #define LMEM_PCCCR_PCCR3_WIDTH (1U) 119 #define LMEM_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK) 120 121 #define LMEM_PCCCR_INVW0_MASK (0x1000000U) 122 #define LMEM_PCCCR_INVW0_SHIFT (24U) 123 #define LMEM_PCCCR_INVW0_WIDTH (1U) 124 #define LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK) 125 126 #define LMEM_PCCCR_PUSHW0_MASK (0x2000000U) 127 #define LMEM_PCCCR_PUSHW0_SHIFT (25U) 128 #define LMEM_PCCCR_PUSHW0_WIDTH (1U) 129 #define LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK) 130 131 #define LMEM_PCCCR_INVW1_MASK (0x4000000U) 132 #define LMEM_PCCCR_INVW1_SHIFT (26U) 133 #define LMEM_PCCCR_INVW1_WIDTH (1U) 134 #define LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK) 135 136 #define LMEM_PCCCR_PUSHW1_MASK (0x8000000U) 137 #define LMEM_PCCCR_PUSHW1_SHIFT (27U) 138 #define LMEM_PCCCR_PUSHW1_WIDTH (1U) 139 #define LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK) 140 141 #define LMEM_PCCCR_GO_MASK (0x80000000U) 142 #define LMEM_PCCCR_GO_SHIFT (31U) 143 #define LMEM_PCCCR_GO_WIDTH (1U) 144 #define LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK) 145 /*! @} */ 146 147 /*! @name PCCLCR - Cache line control register */ 148 /*! @{ */ 149 150 #define LMEM_PCCLCR_LGO_MASK (0x1U) 151 #define LMEM_PCCLCR_LGO_SHIFT (0U) 152 #define LMEM_PCCLCR_LGO_WIDTH (1U) 153 #define LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK) 154 155 #define LMEM_PCCLCR_CACHEADDR_MASK (0x3FFCU) 156 #define LMEM_PCCLCR_CACHEADDR_SHIFT (2U) 157 #define LMEM_PCCLCR_CACHEADDR_WIDTH (12U) 158 #define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK) 159 160 #define LMEM_PCCLCR_WSEL_MASK (0x4000U) 161 #define LMEM_PCCLCR_WSEL_SHIFT (14U) 162 #define LMEM_PCCLCR_WSEL_WIDTH (1U) 163 #define LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK) 164 165 #define LMEM_PCCLCR_TDSEL_MASK (0x10000U) 166 #define LMEM_PCCLCR_TDSEL_SHIFT (16U) 167 #define LMEM_PCCLCR_TDSEL_WIDTH (1U) 168 #define LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK) 169 170 #define LMEM_PCCLCR_LCIVB_MASK (0x100000U) 171 #define LMEM_PCCLCR_LCIVB_SHIFT (20U) 172 #define LMEM_PCCLCR_LCIVB_WIDTH (1U) 173 #define LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK) 174 175 #define LMEM_PCCLCR_LCIMB_MASK (0x200000U) 176 #define LMEM_PCCLCR_LCIMB_SHIFT (21U) 177 #define LMEM_PCCLCR_LCIMB_WIDTH (1U) 178 #define LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK) 179 180 #define LMEM_PCCLCR_LCWAY_MASK (0x400000U) 181 #define LMEM_PCCLCR_LCWAY_SHIFT (22U) 182 #define LMEM_PCCLCR_LCWAY_WIDTH (1U) 183 #define LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK) 184 185 #define LMEM_PCCLCR_LCMD_MASK (0x3000000U) 186 #define LMEM_PCCLCR_LCMD_SHIFT (24U) 187 #define LMEM_PCCLCR_LCMD_WIDTH (2U) 188 #define LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK) 189 190 #define LMEM_PCCLCR_LADSEL_MASK (0x4000000U) 191 #define LMEM_PCCLCR_LADSEL_SHIFT (26U) 192 #define LMEM_PCCLCR_LADSEL_WIDTH (1U) 193 #define LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK) 194 195 #define LMEM_PCCLCR_LACC_MASK (0x8000000U) 196 #define LMEM_PCCLCR_LACC_SHIFT (27U) 197 #define LMEM_PCCLCR_LACC_WIDTH (1U) 198 #define LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK) 199 /*! @} */ 200 201 /*! @name PCCSAR - Cache search address register */ 202 /*! @{ */ 203 204 #define LMEM_PCCSAR_LGO_MASK (0x1U) 205 #define LMEM_PCCSAR_LGO_SHIFT (0U) 206 #define LMEM_PCCSAR_LGO_WIDTH (1U) 207 #define LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK) 208 209 #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU) 210 #define LMEM_PCCSAR_PHYADDR_SHIFT (2U) 211 #define LMEM_PCCSAR_PHYADDR_WIDTH (30U) 212 #define LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK) 213 /*! @} */ 214 215 /*! @name PCCCVR - Cache read/write value register */ 216 /*! @{ */ 217 218 #define LMEM_PCCCVR_DATA_MASK (0xFFFFFFFFU) 219 #define LMEM_PCCCVR_DATA_SHIFT (0U) 220 #define LMEM_PCCCVR_DATA_WIDTH (32U) 221 #define LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK) 222 /*! @} */ 223 224 /*! @name PCCRMR - Cache regions mode register */ 225 /*! @{ */ 226 227 #define LMEM_PCCRMR_R15_MASK (0x3U) 228 #define LMEM_PCCRMR_R15_SHIFT (0U) 229 #define LMEM_PCCRMR_R15_WIDTH (2U) 230 #define LMEM_PCCRMR_R15(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R15_SHIFT)) & LMEM_PCCRMR_R15_MASK) 231 232 #define LMEM_PCCRMR_R14_MASK (0xCU) 233 #define LMEM_PCCRMR_R14_SHIFT (2U) 234 #define LMEM_PCCRMR_R14_WIDTH (2U) 235 #define LMEM_PCCRMR_R14(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R14_SHIFT)) & LMEM_PCCRMR_R14_MASK) 236 237 #define LMEM_PCCRMR_R13_MASK (0x30U) 238 #define LMEM_PCCRMR_R13_SHIFT (4U) 239 #define LMEM_PCCRMR_R13_WIDTH (2U) 240 #define LMEM_PCCRMR_R13(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R13_SHIFT)) & LMEM_PCCRMR_R13_MASK) 241 242 #define LMEM_PCCRMR_R12_MASK (0xC0U) 243 #define LMEM_PCCRMR_R12_SHIFT (6U) 244 #define LMEM_PCCRMR_R12_WIDTH (2U) 245 #define LMEM_PCCRMR_R12(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R12_SHIFT)) & LMEM_PCCRMR_R12_MASK) 246 247 #define LMEM_PCCRMR_R11_MASK (0x300U) 248 #define LMEM_PCCRMR_R11_SHIFT (8U) 249 #define LMEM_PCCRMR_R11_WIDTH (2U) 250 #define LMEM_PCCRMR_R11(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R11_SHIFT)) & LMEM_PCCRMR_R11_MASK) 251 252 #define LMEM_PCCRMR_R10_MASK (0xC00U) 253 #define LMEM_PCCRMR_R10_SHIFT (10U) 254 #define LMEM_PCCRMR_R10_WIDTH (2U) 255 #define LMEM_PCCRMR_R10(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R10_SHIFT)) & LMEM_PCCRMR_R10_MASK) 256 257 #define LMEM_PCCRMR_R9_MASK (0x3000U) 258 #define LMEM_PCCRMR_R9_SHIFT (12U) 259 #define LMEM_PCCRMR_R9_WIDTH (2U) 260 #define LMEM_PCCRMR_R9(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R9_SHIFT)) & LMEM_PCCRMR_R9_MASK) 261 262 #define LMEM_PCCRMR_R8_MASK (0xC000U) 263 #define LMEM_PCCRMR_R8_SHIFT (14U) 264 #define LMEM_PCCRMR_R8_WIDTH (2U) 265 #define LMEM_PCCRMR_R8(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R8_SHIFT)) & LMEM_PCCRMR_R8_MASK) 266 267 #define LMEM_PCCRMR_R7_MASK (0x30000U) 268 #define LMEM_PCCRMR_R7_SHIFT (16U) 269 #define LMEM_PCCRMR_R7_WIDTH (2U) 270 #define LMEM_PCCRMR_R7(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R7_SHIFT)) & LMEM_PCCRMR_R7_MASK) 271 272 #define LMEM_PCCRMR_R6_MASK (0xC0000U) 273 #define LMEM_PCCRMR_R6_SHIFT (18U) 274 #define LMEM_PCCRMR_R6_WIDTH (2U) 275 #define LMEM_PCCRMR_R6(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R6_SHIFT)) & LMEM_PCCRMR_R6_MASK) 276 277 #define LMEM_PCCRMR_R5_MASK (0x300000U) 278 #define LMEM_PCCRMR_R5_SHIFT (20U) 279 #define LMEM_PCCRMR_R5_WIDTH (2U) 280 #define LMEM_PCCRMR_R5(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R5_SHIFT)) & LMEM_PCCRMR_R5_MASK) 281 282 #define LMEM_PCCRMR_R4_MASK (0xC00000U) 283 #define LMEM_PCCRMR_R4_SHIFT (22U) 284 #define LMEM_PCCRMR_R4_WIDTH (2U) 285 #define LMEM_PCCRMR_R4(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R4_SHIFT)) & LMEM_PCCRMR_R4_MASK) 286 287 #define LMEM_PCCRMR_R3_MASK (0x3000000U) 288 #define LMEM_PCCRMR_R3_SHIFT (24U) 289 #define LMEM_PCCRMR_R3_WIDTH (2U) 290 #define LMEM_PCCRMR_R3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R3_SHIFT)) & LMEM_PCCRMR_R3_MASK) 291 292 #define LMEM_PCCRMR_R2_MASK (0xC000000U) 293 #define LMEM_PCCRMR_R2_SHIFT (26U) 294 #define LMEM_PCCRMR_R2_WIDTH (2U) 295 #define LMEM_PCCRMR_R2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R2_SHIFT)) & LMEM_PCCRMR_R2_MASK) 296 297 #define LMEM_PCCRMR_R1_MASK (0x30000000U) 298 #define LMEM_PCCRMR_R1_SHIFT (28U) 299 #define LMEM_PCCRMR_R1_WIDTH (2U) 300 #define LMEM_PCCRMR_R1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R1_SHIFT)) & LMEM_PCCRMR_R1_MASK) 301 302 #define LMEM_PCCRMR_R0_MASK (0xC0000000U) 303 #define LMEM_PCCRMR_R0_SHIFT (30U) 304 #define LMEM_PCCRMR_R0_WIDTH (2U) 305 #define LMEM_PCCRMR_R0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R0_SHIFT)) & LMEM_PCCRMR_R0_MASK) 306 /*! @} */ 307 308 /*! 309 * @} 310 */ /* end of group LMEM_Register_Masks */ 311 312 /*! 313 * @} 314 */ /* end of group LMEM_Peripheral_Access_Layer */ 315 316 #endif /* #if !defined(S32K116_LMEM_H_) */ 317
