1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K116_FLEXCAN.h 10 * @version 1.1 11 * @date 2022-01-21 12 * @brief Peripheral Access Layer for S32K116_FLEXCAN 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K116_FLEXCAN_H_) /* Check if memory map has not been already included */ 58 #define S32K116_FLEXCAN_H_ 59 60 #include "S32K116_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- FLEXCAN Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CAN_Peripheral_Access_Layer FLEXCAN Peripheral Access Layer 68 * @{ 69 */ 70 71 /** FLEXCAN - Size of Registers Arrays */ 72 #define CAN_RAMn_COUNT 128u 73 #define CAN_RXIMR_COUNT 32u 74 #define CAN_WMB_COUNT 4u 75 76 /** FLEXCAN - Register Layout Typedef */ 77 typedef struct { 78 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ 79 __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */ 80 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */ 81 uint8_t RESERVED_0[4]; 82 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ 83 __IO uint32_t RX14MASK; /**< Rx 14 Mask Register, offset: 0x14 */ 84 __IO uint32_t RX15MASK; /**< Rx 15 Mask Register, offset: 0x18 */ 85 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ 86 __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */ 87 uint8_t RESERVED_1[4]; 88 __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ 89 uint8_t RESERVED_2[4]; 90 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */ 91 __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ 92 __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */ 93 uint8_t RESERVED_3[8]; 94 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ 95 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */ 96 __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ 97 __IO uint32_t CBT; /**< CAN Bit Timing Register, offset: 0x50 */ 98 uint8_t RESERVED_4[44]; 99 struct { /* offset: 0x80, array step: 0x10 */ 100 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 95 CS Register, array offset: 0x80, array step: 0x10 */ 101 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 95 ID Register, array offset: 0x84, array step: 0x10 */ 102 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 95 WORD0 Register, array offset: 0x88, array step: 0x10 */ 103 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 95 WORD1 Register, array offset: 0x8C, array step: 0x10 */ 104 } MB[32]; 105 uint8_t RESERVED_5[1536]; 106 __IO uint32_t RXIMR[CAN_RXIMR_COUNT]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ 107 uint8_t RESERVED_6[512]; 108 __IO uint32_t CTRL1_PN; /**< Pretended Networking Control 1 Register, offset: 0xB00 */ 109 __IO uint32_t CTRL2_PN; /**< Pretended Networking Control 2 Register, offset: 0xB04 */ 110 __IO uint32_t WU_MTC; /**< Pretended Networking Wake Up Match Register, offset: 0xB08 */ 111 __IO uint32_t FLT_ID1; /**< Pretended Networking ID Filter 1 Register, offset: 0xB0C */ 112 __IO uint32_t FLT_DLC; /**< Pretended Networking DLC Filter Register, offset: 0xB10 */ 113 __IO uint32_t PL1_LO; /**< Pretended Networking Payload Low Filter 1 Register, offset: 0xB14 */ 114 __IO uint32_t PL1_HI; /**< Pretended Networking Payload High Filter 1 Register, offset: 0xB18 */ 115 __IO uint32_t FLT_ID2_IDMASK; /**< Pretended Networking ID Filter 2 Register / ID Mask Register, offset: 0xB1C */ 116 __IO uint32_t PL2_PLMASK_LO; /**< Pretended Networking Payload Low Filter 2 Register / Payload Low Mask register, offset: 0xB20 */ 117 __IO uint32_t PL2_PLMASK_HI; /**< Pretended Networking Payload High Filter 2 low order bits / Payload High Mask register, offset: 0xB24 */ 118 uint8_t RESERVED_7[24]; 119 struct { /* offset: 0xB40, array step: 0x10 */ 120 __I uint32_t WMBn_CS; /**< Wake Up Message Buffer register for C/S, array offset: 0xB40, array step: 0x10 */ 121 __I uint32_t WMBn_ID; /**< Wake Up Message Buffer Register for ID, array offset: 0xB44, array step: 0x10 */ 122 __I uint32_t WMBn_D03; /**< Wake Up Message Buffer Register for Data 0-3, array offset: 0xB48, array step: 0x10 */ 123 __I uint32_t WMBn_D47; /**< Wake Up Message Buffer Register Data 4-7, array offset: 0xB4C, array step: 0x10 */ 124 } WMB[CAN_WMB_COUNT]; 125 uint8_t RESERVED_8[128]; 126 __IO uint32_t FDCTRL; /**< CAN FD Control Register, offset: 0xC00 */ 127 __IO uint32_t FDCBT; /**< CAN FD Bit Timing Register, offset: 0xC04 */ 128 __I uint32_t FDCRC; /**< CAN FD CRC Register, offset: 0xC08 */ 129 } CAN_Type, *CAN_MemMapPtr; 130 131 /** Number of instances of the FLEXCAN module. */ 132 #define CAN_INSTANCE_COUNT (1u) 133 134 /* FLEXCAN - Peripheral instance base addresses */ 135 /** Peripheral FLEXCAN0 base address */ 136 #define IP_FLEXCAN0_BASE (0x40024000u) 137 /** Peripheral FLEXCAN0 base pointer */ 138 #define IP_FLEXCAN0 ((CAN_Type *)IP_FLEXCAN0_BASE) 139 /** Array initializer of FLEXCAN peripheral base addresses */ 140 #define IP_FLEXCAN_BASE_ADDRS { IP_FLEXCAN0_BASE } 141 /** Array initializer of FLEXCAN peripheral base pointers */ 142 #define IP_FLEXCAN_BASE_PTRS { IP_FLEXCAN0 } 143 144 /* ---------------------------------------------------------------------------- 145 -- FLEXCAN Register Masks 146 ---------------------------------------------------------------------------- */ 147 148 /*! 149 * @addtogroup CAN_Register_Masks FLEXCAN Register Masks 150 * @{ 151 */ 152 153 /*! @name MCR - Module Configuration Register */ 154 /*! @{ */ 155 156 #define CAN_MCR_MAXMB_MASK (0x7FU) 157 #define CAN_MCR_MAXMB_SHIFT (0U) 158 #define CAN_MCR_MAXMB_WIDTH (7U) 159 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) 160 161 #define CAN_MCR_IDAM_MASK (0x300U) 162 #define CAN_MCR_IDAM_SHIFT (8U) 163 #define CAN_MCR_IDAM_WIDTH (2U) 164 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) 165 166 #define CAN_MCR_FDEN_MASK (0x800U) 167 #define CAN_MCR_FDEN_SHIFT (11U) 168 #define CAN_MCR_FDEN_WIDTH (1U) 169 #define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK) 170 171 #define CAN_MCR_AEN_MASK (0x1000U) 172 #define CAN_MCR_AEN_SHIFT (12U) 173 #define CAN_MCR_AEN_WIDTH (1U) 174 #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) 175 176 #define CAN_MCR_LPRIOEN_MASK (0x2000U) 177 #define CAN_MCR_LPRIOEN_SHIFT (13U) 178 #define CAN_MCR_LPRIOEN_WIDTH (1U) 179 #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) 180 181 #define CAN_MCR_PNET_EN_MASK (0x4000U) 182 #define CAN_MCR_PNET_EN_SHIFT (14U) 183 #define CAN_MCR_PNET_EN_WIDTH (1U) 184 #define CAN_MCR_PNET_EN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_PNET_EN_SHIFT)) & CAN_MCR_PNET_EN_MASK) 185 186 #define CAN_MCR_DMA_MASK (0x8000U) 187 #define CAN_MCR_DMA_SHIFT (15U) 188 #define CAN_MCR_DMA_WIDTH (1U) 189 #define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK) 190 191 #define CAN_MCR_IRMQ_MASK (0x10000U) 192 #define CAN_MCR_IRMQ_SHIFT (16U) 193 #define CAN_MCR_IRMQ_WIDTH (1U) 194 #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) 195 196 #define CAN_MCR_SRXDIS_MASK (0x20000U) 197 #define CAN_MCR_SRXDIS_SHIFT (17U) 198 #define CAN_MCR_SRXDIS_WIDTH (1U) 199 #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) 200 201 #define CAN_MCR_DOZE_MASK (0x40000U) 202 #define CAN_MCR_DOZE_SHIFT (18U) 203 #define CAN_MCR_DOZE_WIDTH (1U) 204 #define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK) 205 206 #define CAN_MCR_WAKSRC_MASK (0x80000U) /* Reserved */ 207 #define CAN_MCR_WAKSRC_SHIFT (19U) 208 #define CAN_MCR_WAKSRC_WIDTH (1U) 209 #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) 210 211 #define CAN_MCR_LPMACK_MASK (0x100000U) 212 #define CAN_MCR_LPMACK_SHIFT (20U) 213 #define CAN_MCR_LPMACK_WIDTH (1U) 214 #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) 215 216 #define CAN_MCR_WRNEN_MASK (0x200000U) 217 #define CAN_MCR_WRNEN_SHIFT (21U) 218 #define CAN_MCR_WRNEN_WIDTH (1U) 219 #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) 220 221 #define CAN_MCR_SLFWAK_MASK (0x400000U) /* Reserved */ 222 #define CAN_MCR_SLFWAK_SHIFT (22U) 223 #define CAN_MCR_SLFWAK_WIDTH (1U) 224 #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) 225 226 #define CAN_MCR_SUPV_MASK (0x800000U) 227 #define CAN_MCR_SUPV_SHIFT (23U) 228 #define CAN_MCR_SUPV_WIDTH (1U) 229 #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) 230 231 #define CAN_MCR_FRZACK_MASK (0x1000000U) 232 #define CAN_MCR_FRZACK_SHIFT (24U) 233 #define CAN_MCR_FRZACK_WIDTH (1U) 234 #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) 235 236 #define CAN_MCR_SOFTRST_MASK (0x2000000U) 237 #define CAN_MCR_SOFTRST_SHIFT (25U) 238 #define CAN_MCR_SOFTRST_WIDTH (1U) 239 #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) 240 241 #define CAN_MCR_WAKMSK_MASK (0x4000000U) /* Reserved */ 242 #define CAN_MCR_WAKMSK_SHIFT (26U) 243 #define CAN_MCR_WAKMSK_WIDTH (1U) 244 #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) 245 246 #define CAN_MCR_NOTRDY_MASK (0x8000000U) 247 #define CAN_MCR_NOTRDY_SHIFT (27U) 248 #define CAN_MCR_NOTRDY_WIDTH (1U) 249 #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) 250 251 #define CAN_MCR_HALT_MASK (0x10000000U) 252 #define CAN_MCR_HALT_SHIFT (28U) 253 #define CAN_MCR_HALT_WIDTH (1U) 254 #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) 255 256 #define CAN_MCR_RFEN_MASK (0x20000000U) 257 #define CAN_MCR_RFEN_SHIFT (29U) 258 #define CAN_MCR_RFEN_WIDTH (1U) 259 #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) 260 261 #define CAN_MCR_FRZ_MASK (0x40000000U) 262 #define CAN_MCR_FRZ_SHIFT (30U) 263 #define CAN_MCR_FRZ_WIDTH (1U) 264 #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) 265 266 #define CAN_MCR_MDIS_MASK (0x80000000U) 267 #define CAN_MCR_MDIS_SHIFT (31U) 268 #define CAN_MCR_MDIS_WIDTH (1U) 269 #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) 270 /*! @} */ 271 272 /*! @name CTRL1 - Control 1 Register */ 273 /*! @{ */ 274 275 #define CAN_CTRL1_PROPSEG_MASK (0x7U) 276 #define CAN_CTRL1_PROPSEG_SHIFT (0U) 277 #define CAN_CTRL1_PROPSEG_WIDTH (3U) 278 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) 279 280 #define CAN_CTRL1_LOM_MASK (0x8U) 281 #define CAN_CTRL1_LOM_SHIFT (3U) 282 #define CAN_CTRL1_LOM_WIDTH (1U) 283 #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) 284 285 #define CAN_CTRL1_LBUF_MASK (0x10U) 286 #define CAN_CTRL1_LBUF_SHIFT (4U) 287 #define CAN_CTRL1_LBUF_WIDTH (1U) 288 #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) 289 290 #define CAN_CTRL1_TSYN_MASK (0x20U) 291 #define CAN_CTRL1_TSYN_SHIFT (5U) 292 #define CAN_CTRL1_TSYN_WIDTH (1U) 293 #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) 294 295 #define CAN_CTRL1_BOFFREC_MASK (0x40U) 296 #define CAN_CTRL1_BOFFREC_SHIFT (6U) 297 #define CAN_CTRL1_BOFFREC_WIDTH (1U) 298 #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) 299 300 #define CAN_CTRL1_SMP_MASK (0x80U) 301 #define CAN_CTRL1_SMP_SHIFT (7U) 302 #define CAN_CTRL1_SMP_WIDTH (1U) 303 #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) 304 305 #define CAN_CTRL1_RWRNMSK_MASK (0x400U) 306 #define CAN_CTRL1_RWRNMSK_SHIFT (10U) 307 #define CAN_CTRL1_RWRNMSK_WIDTH (1U) 308 #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) 309 310 #define CAN_CTRL1_TWRNMSK_MASK (0x800U) 311 #define CAN_CTRL1_TWRNMSK_SHIFT (11U) 312 #define CAN_CTRL1_TWRNMSK_WIDTH (1U) 313 #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) 314 315 #define CAN_CTRL1_LPB_MASK (0x1000U) 316 #define CAN_CTRL1_LPB_SHIFT (12U) 317 #define CAN_CTRL1_LPB_WIDTH (1U) 318 #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) 319 320 #define CAN_CTRL1_CLKSRC_MASK (0x2000U) 321 #define CAN_CTRL1_CLKSRC_SHIFT (13U) 322 #define CAN_CTRL1_CLKSRC_WIDTH (1U) 323 #define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK) 324 325 #define CAN_CTRL1_ERRMSK_MASK (0x4000U) 326 #define CAN_CTRL1_ERRMSK_SHIFT (14U) 327 #define CAN_CTRL1_ERRMSK_WIDTH (1U) 328 #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) 329 330 #define CAN_CTRL1_BOFFMSK_MASK (0x8000U) 331 #define CAN_CTRL1_BOFFMSK_SHIFT (15U) 332 #define CAN_CTRL1_BOFFMSK_WIDTH (1U) 333 #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) 334 335 #define CAN_CTRL1_PSEG2_MASK (0x70000U) 336 #define CAN_CTRL1_PSEG2_SHIFT (16U) 337 #define CAN_CTRL1_PSEG2_WIDTH (3U) 338 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) 339 340 #define CAN_CTRL1_PSEG1_MASK (0x380000U) 341 #define CAN_CTRL1_PSEG1_SHIFT (19U) 342 #define CAN_CTRL1_PSEG1_WIDTH (3U) 343 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) 344 345 #define CAN_CTRL1_RJW_MASK (0xC00000U) 346 #define CAN_CTRL1_RJW_SHIFT (22U) 347 #define CAN_CTRL1_RJW_WIDTH (2U) 348 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) 349 350 #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) 351 #define CAN_CTRL1_PRESDIV_SHIFT (24U) 352 #define CAN_CTRL1_PRESDIV_WIDTH (8U) 353 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) 354 /*! @} */ 355 356 /*! @name TIMER - Free Running Timer */ 357 /*! @{ */ 358 359 #define CAN_TIMER_TIMER_MASK (0xFFFFU) 360 #define CAN_TIMER_TIMER_SHIFT (0U) 361 #define CAN_TIMER_TIMER_WIDTH (16U) 362 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) 363 /*! @} */ 364 365 /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ 366 /*! @{ */ 367 368 #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) 369 #define CAN_RXMGMASK_MG_SHIFT (0U) 370 #define CAN_RXMGMASK_MG_WIDTH (32U) 371 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) 372 /*! @} */ 373 374 /*! @name RX14MASK - Rx 14 Mask Register */ 375 /*! @{ */ 376 377 #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) 378 #define CAN_RX14MASK_RX14M_SHIFT (0U) 379 #define CAN_RX14MASK_RX14M_WIDTH (32U) 380 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) 381 /*! @} */ 382 383 /*! @name RX15MASK - Rx 15 Mask Register */ 384 /*! @{ */ 385 386 #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) 387 #define CAN_RX15MASK_RX15M_SHIFT (0U) 388 #define CAN_RX15MASK_RX15M_WIDTH (32U) 389 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) 390 /*! @} */ 391 392 /*! @name ECR - Error Counter */ 393 /*! @{ */ 394 395 #define CAN_ECR_TXERRCNT_MASK (0xFFU) 396 #define CAN_ECR_TXERRCNT_SHIFT (0U) 397 #define CAN_ECR_TXERRCNT_WIDTH (8U) 398 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) 399 400 #define CAN_ECR_RXERRCNT_MASK (0xFF00U) 401 #define CAN_ECR_RXERRCNT_SHIFT (8U) 402 #define CAN_ECR_RXERRCNT_WIDTH (8U) 403 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) 404 405 #define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U) 406 #define CAN_ECR_TXERRCNT_FAST_SHIFT (16U) 407 #define CAN_ECR_TXERRCNT_FAST_WIDTH (8U) 408 #define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK) 409 410 #define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U) 411 #define CAN_ECR_RXERRCNT_FAST_SHIFT (24U) 412 #define CAN_ECR_RXERRCNT_FAST_WIDTH (8U) 413 #define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK) 414 /*! @} */ 415 416 /*! @name ESR1 - Error and Status 1 Register */ 417 /*! @{ */ 418 419 #define CAN_ESR1_WAKINT_MASK (0x1U) /* Reserved */ 420 #define CAN_ESR1_WAKINT_SHIFT (0U) 421 #define CAN_ESR1_WAKINT_WIDTH (1U) 422 #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) 423 424 #define CAN_ESR1_ERRINT_MASK (0x2U) 425 #define CAN_ESR1_ERRINT_SHIFT (1U) 426 #define CAN_ESR1_ERRINT_WIDTH (1U) 427 #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) 428 429 #define CAN_ESR1_BOFFINT_MASK (0x4U) 430 #define CAN_ESR1_BOFFINT_SHIFT (2U) 431 #define CAN_ESR1_BOFFINT_WIDTH (1U) 432 #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) 433 434 #define CAN_ESR1_RX_MASK (0x8U) 435 #define CAN_ESR1_RX_SHIFT (3U) 436 #define CAN_ESR1_RX_WIDTH (1U) 437 #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) 438 439 #define CAN_ESR1_FLTCONF_MASK (0x30U) 440 #define CAN_ESR1_FLTCONF_SHIFT (4U) 441 #define CAN_ESR1_FLTCONF_WIDTH (2U) 442 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) 443 444 #define CAN_ESR1_TX_MASK (0x40U) 445 #define CAN_ESR1_TX_SHIFT (6U) 446 #define CAN_ESR1_TX_WIDTH (1U) 447 #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) 448 449 #define CAN_ESR1_IDLE_MASK (0x80U) 450 #define CAN_ESR1_IDLE_SHIFT (7U) 451 #define CAN_ESR1_IDLE_WIDTH (1U) 452 #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) 453 454 #define CAN_ESR1_RXWRN_MASK (0x100U) 455 #define CAN_ESR1_RXWRN_SHIFT (8U) 456 #define CAN_ESR1_RXWRN_WIDTH (1U) 457 #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) 458 459 #define CAN_ESR1_TXWRN_MASK (0x200U) 460 #define CAN_ESR1_TXWRN_SHIFT (9U) 461 #define CAN_ESR1_TXWRN_WIDTH (1U) 462 #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) 463 464 #define CAN_ESR1_STFERR_MASK (0x400U) 465 #define CAN_ESR1_STFERR_SHIFT (10U) 466 #define CAN_ESR1_STFERR_WIDTH (1U) 467 #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) 468 469 #define CAN_ESR1_FRMERR_MASK (0x800U) 470 #define CAN_ESR1_FRMERR_SHIFT (11U) 471 #define CAN_ESR1_FRMERR_WIDTH (1U) 472 #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) 473 474 #define CAN_ESR1_CRCERR_MASK (0x1000U) 475 #define CAN_ESR1_CRCERR_SHIFT (12U) 476 #define CAN_ESR1_CRCERR_WIDTH (1U) 477 #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) 478 479 #define CAN_ESR1_ACKERR_MASK (0x2000U) 480 #define CAN_ESR1_ACKERR_SHIFT (13U) 481 #define CAN_ESR1_ACKERR_WIDTH (1U) 482 #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) 483 484 #define CAN_ESR1_BIT0ERR_MASK (0x4000U) 485 #define CAN_ESR1_BIT0ERR_SHIFT (14U) 486 #define CAN_ESR1_BIT0ERR_WIDTH (1U) 487 #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) 488 489 #define CAN_ESR1_BIT1ERR_MASK (0x8000U) 490 #define CAN_ESR1_BIT1ERR_SHIFT (15U) 491 #define CAN_ESR1_BIT1ERR_WIDTH (1U) 492 #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) 493 494 #define CAN_ESR1_RWRNINT_MASK (0x10000U) 495 #define CAN_ESR1_RWRNINT_SHIFT (16U) 496 #define CAN_ESR1_RWRNINT_WIDTH (1U) 497 #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) 498 499 #define CAN_ESR1_TWRNINT_MASK (0x20000U) 500 #define CAN_ESR1_TWRNINT_SHIFT (17U) 501 #define CAN_ESR1_TWRNINT_WIDTH (1U) 502 #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) 503 504 #define CAN_ESR1_SYNCH_MASK (0x40000U) 505 #define CAN_ESR1_SYNCH_SHIFT (18U) 506 #define CAN_ESR1_SYNCH_WIDTH (1U) 507 #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) 508 509 #define CAN_ESR1_BOFFDONEINT_MASK (0x80000U) 510 #define CAN_ESR1_BOFFDONEINT_SHIFT (19U) 511 #define CAN_ESR1_BOFFDONEINT_WIDTH (1U) 512 #define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK) 513 514 #define CAN_ESR1_ERRINT_FAST_MASK (0x100000U) 515 #define CAN_ESR1_ERRINT_FAST_SHIFT (20U) 516 #define CAN_ESR1_ERRINT_FAST_WIDTH (1U) 517 #define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK) 518 519 #define CAN_ESR1_ERROVR_MASK (0x200000U) 520 #define CAN_ESR1_ERROVR_SHIFT (21U) 521 #define CAN_ESR1_ERROVR_WIDTH (1U) 522 #define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK) 523 524 #define CAN_ESR1_STFERR_FAST_MASK (0x4000000U) 525 #define CAN_ESR1_STFERR_FAST_SHIFT (26U) 526 #define CAN_ESR1_STFERR_FAST_WIDTH (1U) 527 #define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK) 528 529 #define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U) 530 #define CAN_ESR1_FRMERR_FAST_SHIFT (27U) 531 #define CAN_ESR1_FRMERR_FAST_WIDTH (1U) 532 #define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK) 533 534 #define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U) 535 #define CAN_ESR1_CRCERR_FAST_SHIFT (28U) 536 #define CAN_ESR1_CRCERR_FAST_WIDTH (1U) 537 #define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK) 538 539 #define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) 540 #define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U) 541 #define CAN_ESR1_BIT0ERR_FAST_WIDTH (1U) 542 #define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK) 543 544 #define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) 545 #define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U) 546 #define CAN_ESR1_BIT1ERR_FAST_WIDTH (1U) 547 #define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK) 548 /*! @} */ 549 550 /*! @name IMASK1 - Interrupt Masks 1 Register */ 551 /*! @{ */ 552 553 #define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU) 554 #define CAN_IMASK1_BUF31TO0M_SHIFT (0U) 555 #define CAN_IMASK1_BUF31TO0M_WIDTH (32U) 556 #define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK) 557 /*! @} */ 558 559 /*! @name IFLAG1 - Interrupt Flags 1 Register */ 560 /*! @{ */ 561 562 #define CAN_IFLAG1_BUF0I_MASK (0x1U) 563 #define CAN_IFLAG1_BUF0I_SHIFT (0U) 564 #define CAN_IFLAG1_BUF0I_WIDTH (1U) 565 #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) 566 567 #define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) 568 #define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) 569 #define CAN_IFLAG1_BUF4TO1I_WIDTH (4U) 570 #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) 571 572 #define CAN_IFLAG1_BUF5I_MASK (0x20U) 573 #define CAN_IFLAG1_BUF5I_SHIFT (5U) 574 #define CAN_IFLAG1_BUF5I_WIDTH (1U) 575 #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) 576 577 #define CAN_IFLAG1_BUF6I_MASK (0x40U) 578 #define CAN_IFLAG1_BUF6I_SHIFT (6U) 579 #define CAN_IFLAG1_BUF6I_WIDTH (1U) 580 #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) 581 582 #define CAN_IFLAG1_BUF7I_MASK (0x80U) 583 #define CAN_IFLAG1_BUF7I_SHIFT (7U) 584 #define CAN_IFLAG1_BUF7I_WIDTH (1U) 585 #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) 586 587 #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) 588 #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) 589 #define CAN_IFLAG1_BUF31TO8I_WIDTH (24U) 590 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) 591 /*! @} */ 592 593 /*! @name CTRL2 - Control 2 Register */ 594 /*! @{ */ 595 596 #define CAN_CTRL2_EDFLTDIS_MASK (0x800U) 597 #define CAN_CTRL2_EDFLTDIS_SHIFT (11U) 598 #define CAN_CTRL2_EDFLTDIS_WIDTH (1U) 599 #define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK) 600 601 #define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U) 602 #define CAN_CTRL2_ISOCANFDEN_SHIFT (12U) 603 #define CAN_CTRL2_ISOCANFDEN_WIDTH (1U) 604 #define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK) 605 606 #define CAN_CTRL2_PREXCEN_MASK (0x4000U) 607 #define CAN_CTRL2_PREXCEN_SHIFT (14U) 608 #define CAN_CTRL2_PREXCEN_WIDTH (1U) 609 #define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK) 610 611 #define CAN_CTRL2_TIMER_SRC_MASK (0x8000U) 612 #define CAN_CTRL2_TIMER_SRC_SHIFT (15U) 613 #define CAN_CTRL2_TIMER_SRC_WIDTH (1U) 614 #define CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK) 615 616 #define CAN_CTRL2_EACEN_MASK (0x10000U) 617 #define CAN_CTRL2_EACEN_SHIFT (16U) 618 #define CAN_CTRL2_EACEN_WIDTH (1U) 619 #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) 620 621 #define CAN_CTRL2_RRS_MASK (0x20000U) 622 #define CAN_CTRL2_RRS_SHIFT (17U) 623 #define CAN_CTRL2_RRS_WIDTH (1U) 624 #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) 625 626 #define CAN_CTRL2_MRP_MASK (0x40000U) 627 #define CAN_CTRL2_MRP_SHIFT (18U) 628 #define CAN_CTRL2_MRP_WIDTH (1U) 629 #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) 630 631 #define CAN_CTRL2_TASD_MASK (0xF80000U) 632 #define CAN_CTRL2_TASD_SHIFT (19U) 633 #define CAN_CTRL2_TASD_WIDTH (5U) 634 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) 635 636 #define CAN_CTRL2_RFFN_MASK (0xF000000U) 637 #define CAN_CTRL2_RFFN_SHIFT (24U) 638 #define CAN_CTRL2_RFFN_WIDTH (4U) 639 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) 640 641 #define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U) 642 #define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U) 643 #define CAN_CTRL2_BOFFDONEMSK_WIDTH (1U) 644 #define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK) 645 646 #define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) 647 #define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U) 648 #define CAN_CTRL2_ERRMSK_FAST_WIDTH (1U) 649 #define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK) 650 /*! @} */ 651 652 /*! @name ESR2 - Error and Status 2 Register */ 653 /*! @{ */ 654 655 #define CAN_ESR2_IMB_MASK (0x2000U) 656 #define CAN_ESR2_IMB_SHIFT (13U) 657 #define CAN_ESR2_IMB_WIDTH (1U) 658 #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) 659 660 #define CAN_ESR2_VPS_MASK (0x4000U) 661 #define CAN_ESR2_VPS_SHIFT (14U) 662 #define CAN_ESR2_VPS_WIDTH (1U) 663 #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) 664 665 #define CAN_ESR2_LPTM_MASK (0x7F0000U) 666 #define CAN_ESR2_LPTM_SHIFT (16U) 667 #define CAN_ESR2_LPTM_WIDTH (7U) 668 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) 669 /*! @} */ 670 671 /*! @name CRCR - CRC Register */ 672 /*! @{ */ 673 674 #define CAN_CRCR_TXCRC_MASK (0x7FFFU) 675 #define CAN_CRCR_TXCRC_SHIFT (0U) 676 #define CAN_CRCR_TXCRC_WIDTH (15U) 677 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) 678 679 #define CAN_CRCR_MBCRC_MASK (0x7F0000U) 680 #define CAN_CRCR_MBCRC_SHIFT (16U) 681 #define CAN_CRCR_MBCRC_WIDTH (7U) 682 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) 683 /*! @} */ 684 685 /*! @name RXFGMASK - Rx FIFO Global Mask Register */ 686 /*! @{ */ 687 688 #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) 689 #define CAN_RXFGMASK_FGM_SHIFT (0U) 690 #define CAN_RXFGMASK_FGM_WIDTH (32U) 691 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) 692 /*! @} */ 693 694 /*! @name RXFIR - Rx FIFO Information Register */ 695 /*! @{ */ 696 697 #define CAN_RXFIR_IDHIT_MASK (0x1FFU) 698 #define CAN_RXFIR_IDHIT_SHIFT (0U) 699 #define CAN_RXFIR_IDHIT_WIDTH (9U) 700 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) 701 /*! @} */ 702 703 /*! @name CBT - CAN Bit Timing Register */ 704 /*! @{ */ 705 706 #define CAN_CBT_EPSEG2_MASK (0x1FU) 707 #define CAN_CBT_EPSEG2_SHIFT (0U) 708 #define CAN_CBT_EPSEG2_WIDTH (5U) 709 #define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK) 710 711 #define CAN_CBT_EPSEG1_MASK (0x3E0U) 712 #define CAN_CBT_EPSEG1_SHIFT (5U) 713 #define CAN_CBT_EPSEG1_WIDTH (5U) 714 #define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK) 715 716 #define CAN_CBT_EPROPSEG_MASK (0xFC00U) 717 #define CAN_CBT_EPROPSEG_SHIFT (10U) 718 #define CAN_CBT_EPROPSEG_WIDTH (6U) 719 #define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK) 720 721 #define CAN_CBT_ERJW_MASK (0x1F0000U) 722 #define CAN_CBT_ERJW_SHIFT (16U) 723 #define CAN_CBT_ERJW_WIDTH (5U) 724 #define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK) 725 726 #define CAN_CBT_EPRESDIV_MASK (0x7FE00000U) 727 #define CAN_CBT_EPRESDIV_SHIFT (21U) 728 #define CAN_CBT_EPRESDIV_WIDTH (10U) 729 #define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK) 730 731 #define CAN_CBT_BTF_MASK (0x80000000U) 732 #define CAN_CBT_BTF_SHIFT (31U) 733 #define CAN_CBT_BTF_WIDTH (1U) 734 #define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK) 735 /*! @} */ 736 737 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 31 CS Register */ 738 /*! @{ */ 739 740 #define CAN_CS_TIME_STAMP_MASK (0xFFFFU) 741 #define CAN_CS_TIME_STAMP_SHIFT (0U) 742 #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) 743 744 #define CAN_CS_DLC_MASK (0xF0000U) 745 #define CAN_CS_DLC_SHIFT (16U) 746 #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) 747 748 #define CAN_CS_RTR_MASK (0x100000U) 749 #define CAN_CS_RTR_SHIFT (20U) 750 #define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) 751 752 #define CAN_CS_IDE_MASK (0x200000U) 753 #define CAN_CS_IDE_SHIFT (21U) 754 #define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) 755 756 #define CAN_CS_SRR_MASK (0x400000U) 757 #define CAN_CS_SRR_SHIFT (22U) 758 #define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) 759 760 #define CAN_CS_CODE_MASK (0xF000000U) 761 #define CAN_CS_CODE_SHIFT (24U) 762 #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) 763 764 #define CAN_CS_ESI_MASK (0x20000000U) 765 #define CAN_CS_ESI_SHIFT (29U) 766 #define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK) 767 768 #define CAN_CS_BRS_MASK (0x40000000U) 769 #define CAN_CS_BRS_SHIFT (30U) 770 #define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK) 771 772 #define CAN_CS_EDL_MASK (0x80000000U) 773 #define CAN_CS_EDL_SHIFT (31U) 774 #define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK) 775 /*! @} */ 776 777 /* The count of CAN_CS */ 778 #define CAN_CS_COUNT (32U) 779 780 /*! @name ID - Message Buffer 0 ID Register..Message Buffer 31 ID Register */ 781 /*! @{ */ 782 783 #define CAN_ID_EXT_MASK (0x3FFFFU) 784 #define CAN_ID_EXT_SHIFT (0U) 785 #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) 786 787 #define CAN_ID_STD_MASK (0x1FFC0000U) 788 #define CAN_ID_STD_SHIFT (18U) 789 #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) 790 791 #define CAN_ID_PRIO_MASK (0xE0000000U) 792 #define CAN_ID_PRIO_SHIFT (29U) 793 #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) 794 /*! @} */ 795 796 /* The count of CAN_ID */ 797 #define CAN_ID_COUNT (32U) 798 799 /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 31 WORD0 Register */ 800 /*! @{ */ 801 802 #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) 803 #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) 804 #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) 805 806 #define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) 807 #define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) 808 #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) 809 810 #define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) 811 #define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) 812 #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) 813 814 #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) 815 #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) 816 #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) 817 /*! @} */ 818 819 /* The count of CAN_WORD0 */ 820 #define CAN_WORD0_COUNT (32U) 821 822 /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 31 WORD1 Register */ 823 /*! @{ */ 824 825 #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) 826 #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) 827 #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) 828 829 #define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) 830 #define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) 831 #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) 832 833 #define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) 834 #define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) 835 #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) 836 837 #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) 838 #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) 839 #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) 840 /*! @} */ 841 842 /* The count of CAN_WORD1 */ 843 #define CAN_WORD1_COUNT (32U) 844 845 /*! @name RXIMR - Rx Individual Mask Registers */ 846 /*! @{ */ 847 848 #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) 849 #define CAN_RXIMR_MI_SHIFT (0U) 850 #define CAN_RXIMR_MI_WIDTH (32U) 851 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) 852 /*! @} */ 853 854 /*! @name CTRL1_PN - Pretended Networking Control 1 Register */ 855 /*! @{ */ 856 857 #define CAN_CTRL1_PN_FCS_MASK (0x3U) 858 #define CAN_CTRL1_PN_FCS_SHIFT (0U) 859 #define CAN_CTRL1_PN_FCS_WIDTH (2U) 860 #define CAN_CTRL1_PN_FCS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_FCS_SHIFT)) & CAN_CTRL1_PN_FCS_MASK) 861 862 #define CAN_CTRL1_PN_IDFS_MASK (0xCU) 863 #define CAN_CTRL1_PN_IDFS_SHIFT (2U) 864 #define CAN_CTRL1_PN_IDFS_WIDTH (2U) 865 #define CAN_CTRL1_PN_IDFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_IDFS_SHIFT)) & CAN_CTRL1_PN_IDFS_MASK) 866 867 #define CAN_CTRL1_PN_PLFS_MASK (0x30U) 868 #define CAN_CTRL1_PN_PLFS_SHIFT (4U) 869 #define CAN_CTRL1_PN_PLFS_WIDTH (2U) 870 #define CAN_CTRL1_PN_PLFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_PLFS_SHIFT)) & CAN_CTRL1_PN_PLFS_MASK) 871 872 #define CAN_CTRL1_PN_NMATCH_MASK (0xFF00U) 873 #define CAN_CTRL1_PN_NMATCH_SHIFT (8U) 874 #define CAN_CTRL1_PN_NMATCH_WIDTH (8U) 875 #define CAN_CTRL1_PN_NMATCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_NMATCH_SHIFT)) & CAN_CTRL1_PN_NMATCH_MASK) 876 877 #define CAN_CTRL1_PN_WUMF_MSK_MASK (0x10000U) 878 #define CAN_CTRL1_PN_WUMF_MSK_SHIFT (16U) 879 #define CAN_CTRL1_PN_WUMF_MSK_WIDTH (1U) 880 #define CAN_CTRL1_PN_WUMF_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WUMF_MSK_SHIFT)) & CAN_CTRL1_PN_WUMF_MSK_MASK) 881 882 #define CAN_CTRL1_PN_WTOF_MSK_MASK (0x20000U) 883 #define CAN_CTRL1_PN_WTOF_MSK_SHIFT (17U) 884 #define CAN_CTRL1_PN_WTOF_MSK_WIDTH (1U) 885 #define CAN_CTRL1_PN_WTOF_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WTOF_MSK_SHIFT)) & CAN_CTRL1_PN_WTOF_MSK_MASK) 886 /*! @} */ 887 888 /*! @name CTRL2_PN - Pretended Networking Control 2 Register */ 889 /*! @{ */ 890 891 #define CAN_CTRL2_PN_MATCHTO_MASK (0xFFFFU) 892 #define CAN_CTRL2_PN_MATCHTO_SHIFT (0U) 893 #define CAN_CTRL2_PN_MATCHTO_WIDTH (16U) 894 #define CAN_CTRL2_PN_MATCHTO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PN_MATCHTO_SHIFT)) & CAN_CTRL2_PN_MATCHTO_MASK) 895 /*! @} */ 896 897 /*! @name WU_MTC - Pretended Networking Wake Up Match Register */ 898 /*! @{ */ 899 900 #define CAN_WU_MTC_MCOUNTER_MASK (0xFF00U) 901 #define CAN_WU_MTC_MCOUNTER_SHIFT (8U) 902 #define CAN_WU_MTC_MCOUNTER_WIDTH (8U) 903 #define CAN_WU_MTC_MCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_MCOUNTER_SHIFT)) & CAN_WU_MTC_MCOUNTER_MASK) 904 905 #define CAN_WU_MTC_WUMF_MASK (0x10000U) 906 #define CAN_WU_MTC_WUMF_SHIFT (16U) 907 #define CAN_WU_MTC_WUMF_WIDTH (1U) 908 #define CAN_WU_MTC_WUMF(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WUMF_SHIFT)) & CAN_WU_MTC_WUMF_MASK) 909 910 #define CAN_WU_MTC_WTOF_MASK (0x20000U) 911 #define CAN_WU_MTC_WTOF_SHIFT (17U) 912 #define CAN_WU_MTC_WTOF_WIDTH (1U) 913 #define CAN_WU_MTC_WTOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WTOF_SHIFT)) & CAN_WU_MTC_WTOF_MASK) 914 /*! @} */ 915 916 /*! @name FLT_ID1 - Pretended Networking ID Filter 1 Register */ 917 /*! @{ */ 918 919 #define CAN_FLT_ID1_FLT_ID1_MASK (0x1FFFFFFFU) 920 #define CAN_FLT_ID1_FLT_ID1_SHIFT (0U) 921 #define CAN_FLT_ID1_FLT_ID1_WIDTH (29U) 922 #define CAN_FLT_ID1_FLT_ID1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_ID1_SHIFT)) & CAN_FLT_ID1_FLT_ID1_MASK) 923 924 #define CAN_FLT_ID1_FLT_RTR_MASK (0x20000000U) 925 #define CAN_FLT_ID1_FLT_RTR_SHIFT (29U) 926 #define CAN_FLT_ID1_FLT_RTR_WIDTH (1U) 927 #define CAN_FLT_ID1_FLT_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_RTR_SHIFT)) & CAN_FLT_ID1_FLT_RTR_MASK) 928 929 #define CAN_FLT_ID1_FLT_IDE_MASK (0x40000000U) 930 #define CAN_FLT_ID1_FLT_IDE_SHIFT (30U) 931 #define CAN_FLT_ID1_FLT_IDE_WIDTH (1U) 932 #define CAN_FLT_ID1_FLT_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_IDE_SHIFT)) & CAN_FLT_ID1_FLT_IDE_MASK) 933 /*! @} */ 934 935 /*! @name FLT_DLC - Pretended Networking DLC Filter Register */ 936 /*! @{ */ 937 938 #define CAN_FLT_DLC_FLT_DLC_HI_MASK (0xFU) 939 #define CAN_FLT_DLC_FLT_DLC_HI_SHIFT (0U) 940 #define CAN_FLT_DLC_FLT_DLC_HI_WIDTH (4U) 941 #define CAN_FLT_DLC_FLT_DLC_HI(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_HI_SHIFT)) & CAN_FLT_DLC_FLT_DLC_HI_MASK) 942 943 #define CAN_FLT_DLC_FLT_DLC_LO_MASK (0xF0000U) 944 #define CAN_FLT_DLC_FLT_DLC_LO_SHIFT (16U) 945 #define CAN_FLT_DLC_FLT_DLC_LO_WIDTH (4U) 946 #define CAN_FLT_DLC_FLT_DLC_LO(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_LO_SHIFT)) & CAN_FLT_DLC_FLT_DLC_LO_MASK) 947 /*! @} */ 948 949 /*! @name PL1_LO - Pretended Networking Payload Low Filter 1 Register */ 950 /*! @{ */ 951 952 #define CAN_PL1_LO_Data_byte_3_MASK (0xFFU) 953 #define CAN_PL1_LO_Data_byte_3_SHIFT (0U) 954 #define CAN_PL1_LO_Data_byte_3_WIDTH (8U) 955 #define CAN_PL1_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_3_SHIFT)) & CAN_PL1_LO_Data_byte_3_MASK) 956 957 #define CAN_PL1_LO_Data_byte_2_MASK (0xFF00U) 958 #define CAN_PL1_LO_Data_byte_2_SHIFT (8U) 959 #define CAN_PL1_LO_Data_byte_2_WIDTH (8U) 960 #define CAN_PL1_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_2_SHIFT)) & CAN_PL1_LO_Data_byte_2_MASK) 961 962 #define CAN_PL1_LO_Data_byte_1_MASK (0xFF0000U) 963 #define CAN_PL1_LO_Data_byte_1_SHIFT (16U) 964 #define CAN_PL1_LO_Data_byte_1_WIDTH (8U) 965 #define CAN_PL1_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_1_SHIFT)) & CAN_PL1_LO_Data_byte_1_MASK) 966 967 #define CAN_PL1_LO_Data_byte_0_MASK (0xFF000000U) 968 #define CAN_PL1_LO_Data_byte_0_SHIFT (24U) 969 #define CAN_PL1_LO_Data_byte_0_WIDTH (8U) 970 #define CAN_PL1_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_0_SHIFT)) & CAN_PL1_LO_Data_byte_0_MASK) 971 /*! @} */ 972 973 /*! @name PL1_HI - Pretended Networking Payload High Filter 1 Register */ 974 /*! @{ */ 975 976 #define CAN_PL1_HI_Data_byte_7_MASK (0xFFU) 977 #define CAN_PL1_HI_Data_byte_7_SHIFT (0U) 978 #define CAN_PL1_HI_Data_byte_7_WIDTH (8U) 979 #define CAN_PL1_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_7_SHIFT)) & CAN_PL1_HI_Data_byte_7_MASK) 980 981 #define CAN_PL1_HI_Data_byte_6_MASK (0xFF00U) 982 #define CAN_PL1_HI_Data_byte_6_SHIFT (8U) 983 #define CAN_PL1_HI_Data_byte_6_WIDTH (8U) 984 #define CAN_PL1_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_6_SHIFT)) & CAN_PL1_HI_Data_byte_6_MASK) 985 986 #define CAN_PL1_HI_Data_byte_5_MASK (0xFF0000U) 987 #define CAN_PL1_HI_Data_byte_5_SHIFT (16U) 988 #define CAN_PL1_HI_Data_byte_5_WIDTH (8U) 989 #define CAN_PL1_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_5_SHIFT)) & CAN_PL1_HI_Data_byte_5_MASK) 990 991 #define CAN_PL1_HI_Data_byte_4_MASK (0xFF000000U) 992 #define CAN_PL1_HI_Data_byte_4_SHIFT (24U) 993 #define CAN_PL1_HI_Data_byte_4_WIDTH (8U) 994 #define CAN_PL1_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_4_SHIFT)) & CAN_PL1_HI_Data_byte_4_MASK) 995 /*! @} */ 996 997 /*! @name FLT_ID2_IDMASK - Pretended Networking ID Filter 2 Register / ID Mask Register */ 998 /*! @{ */ 999 1000 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK (0x1FFFFFFFU) 1001 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT (0U) 1002 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_WIDTH (29U) 1003 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT)) & CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK) 1004 1005 #define CAN_FLT_ID2_IDMASK_RTR_MSK_MASK (0x20000000U) 1006 #define CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT (29U) 1007 #define CAN_FLT_ID2_IDMASK_RTR_MSK_WIDTH (1U) 1008 #define CAN_FLT_ID2_IDMASK_RTR_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_RTR_MSK_MASK) 1009 1010 #define CAN_FLT_ID2_IDMASK_IDE_MSK_MASK (0x40000000U) 1011 #define CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT (30U) 1012 #define CAN_FLT_ID2_IDMASK_IDE_MSK_WIDTH (1U) 1013 #define CAN_FLT_ID2_IDMASK_IDE_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_IDE_MSK_MASK) 1014 /*! @} */ 1015 1016 /*! @name PL2_PLMASK_LO - Pretended Networking Payload Low Filter 2 Register / Payload Low Mask register */ 1017 /*! @{ */ 1018 1019 #define CAN_PL2_PLMASK_LO_Data_byte_3_MASK (0xFFU) 1020 #define CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT (0U) 1021 #define CAN_PL2_PLMASK_LO_Data_byte_3_WIDTH (8U) 1022 #define CAN_PL2_PLMASK_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_3_MASK) 1023 1024 #define CAN_PL2_PLMASK_LO_Data_byte_2_MASK (0xFF00U) 1025 #define CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT (8U) 1026 #define CAN_PL2_PLMASK_LO_Data_byte_2_WIDTH (8U) 1027 #define CAN_PL2_PLMASK_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_2_MASK) 1028 1029 #define CAN_PL2_PLMASK_LO_Data_byte_1_MASK (0xFF0000U) 1030 #define CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT (16U) 1031 #define CAN_PL2_PLMASK_LO_Data_byte_1_WIDTH (8U) 1032 #define CAN_PL2_PLMASK_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_1_MASK) 1033 1034 #define CAN_PL2_PLMASK_LO_Data_byte_0_MASK (0xFF000000U) 1035 #define CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT (24U) 1036 #define CAN_PL2_PLMASK_LO_Data_byte_0_WIDTH (8U) 1037 #define CAN_PL2_PLMASK_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_0_MASK) 1038 /*! @} */ 1039 1040 /*! @name PL2_PLMASK_HI - Pretended Networking Payload High Filter 2 low order bits / Payload High Mask register */ 1041 /*! @{ */ 1042 1043 #define CAN_PL2_PLMASK_HI_Data_byte_7_MASK (0xFFU) 1044 #define CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT (0U) 1045 #define CAN_PL2_PLMASK_HI_Data_byte_7_WIDTH (8U) 1046 #define CAN_PL2_PLMASK_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_7_MASK) 1047 1048 #define CAN_PL2_PLMASK_HI_Data_byte_6_MASK (0xFF00U) 1049 #define CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT (8U) 1050 #define CAN_PL2_PLMASK_HI_Data_byte_6_WIDTH (8U) 1051 #define CAN_PL2_PLMASK_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_6_MASK) 1052 1053 #define CAN_PL2_PLMASK_HI_Data_byte_5_MASK (0xFF0000U) 1054 #define CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT (16U) 1055 #define CAN_PL2_PLMASK_HI_Data_byte_5_WIDTH (8U) 1056 #define CAN_PL2_PLMASK_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_5_MASK) 1057 1058 #define CAN_PL2_PLMASK_HI_Data_byte_4_MASK (0xFF000000U) 1059 #define CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT (24U) 1060 #define CAN_PL2_PLMASK_HI_Data_byte_4_WIDTH (8U) 1061 #define CAN_PL2_PLMASK_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_4_MASK) 1062 /*! @} */ 1063 1064 /*! @name WMBn_CS - Wake Up Message Buffer register for C/S */ 1065 /*! @{ */ 1066 1067 #define CAN_WMBn_CS_DLC_MASK (0xF0000U) 1068 #define CAN_WMBn_CS_DLC_SHIFT (16U) 1069 #define CAN_WMBn_CS_DLC_WIDTH (4U) 1070 #define CAN_WMBn_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_CS_DLC_SHIFT)) & CAN_WMBn_CS_DLC_MASK) 1071 1072 #define CAN_WMBn_CS_RTR_MASK (0x100000U) 1073 #define CAN_WMBn_CS_RTR_SHIFT (20U) 1074 #define CAN_WMBn_CS_RTR_WIDTH (1U) 1075 #define CAN_WMBn_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_CS_RTR_SHIFT)) & CAN_WMBn_CS_RTR_MASK) 1076 1077 #define CAN_WMBn_CS_IDE_MASK (0x200000U) 1078 #define CAN_WMBn_CS_IDE_SHIFT (21U) 1079 #define CAN_WMBn_CS_IDE_WIDTH (1U) 1080 #define CAN_WMBn_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_CS_IDE_SHIFT)) & CAN_WMBn_CS_IDE_MASK) 1081 1082 #define CAN_WMBn_CS_SRR_MASK (0x400000U) 1083 #define CAN_WMBn_CS_SRR_SHIFT (22U) 1084 #define CAN_WMBn_CS_SRR_WIDTH (1U) 1085 #define CAN_WMBn_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_CS_SRR_SHIFT)) & CAN_WMBn_CS_SRR_MASK) 1086 /*! @} */ 1087 1088 /*! @name WMBn_ID - Wake Up Message Buffer Register for ID */ 1089 /*! @{ */ 1090 1091 #define CAN_WMBn_ID_ID_MASK (0x1FFFFFFFU) 1092 #define CAN_WMBn_ID_ID_SHIFT (0U) 1093 #define CAN_WMBn_ID_ID_WIDTH (29U) 1094 #define CAN_WMBn_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_ID_ID_SHIFT)) & CAN_WMBn_ID_ID_MASK) 1095 /*! @} */ 1096 1097 /*! @name WMBn_D03 - Wake Up Message Buffer Register for Data 0-3 */ 1098 /*! @{ */ 1099 1100 #define CAN_WMBn_D03_Data_byte_3_MASK (0xFFU) 1101 #define CAN_WMBn_D03_Data_byte_3_SHIFT (0U) 1102 #define CAN_WMBn_D03_Data_byte_3_WIDTH (8U) 1103 #define CAN_WMBn_D03_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_D03_Data_byte_3_SHIFT)) & CAN_WMBn_D03_Data_byte_3_MASK) 1104 1105 #define CAN_WMBn_D03_Data_byte_2_MASK (0xFF00U) 1106 #define CAN_WMBn_D03_Data_byte_2_SHIFT (8U) 1107 #define CAN_WMBn_D03_Data_byte_2_WIDTH (8U) 1108 #define CAN_WMBn_D03_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_D03_Data_byte_2_SHIFT)) & CAN_WMBn_D03_Data_byte_2_MASK) 1109 1110 #define CAN_WMBn_D03_Data_byte_1_MASK (0xFF0000U) 1111 #define CAN_WMBn_D03_Data_byte_1_SHIFT (16U) 1112 #define CAN_WMBn_D03_Data_byte_1_WIDTH (8U) 1113 #define CAN_WMBn_D03_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_D03_Data_byte_1_SHIFT)) & CAN_WMBn_D03_Data_byte_1_MASK) 1114 1115 #define CAN_WMBn_D03_Data_byte_0_MASK (0xFF000000U) 1116 #define CAN_WMBn_D03_Data_byte_0_SHIFT (24U) 1117 #define CAN_WMBn_D03_Data_byte_0_WIDTH (8U) 1118 #define CAN_WMBn_D03_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_D03_Data_byte_0_SHIFT)) & CAN_WMBn_D03_Data_byte_0_MASK) 1119 /*! @} */ 1120 1121 /*! @name WMBn_D47 - Wake Up Message Buffer Register Data 4-7 */ 1122 /*! @{ */ 1123 1124 #define CAN_WMBn_D47_Data_byte_7_MASK (0xFFU) 1125 #define CAN_WMBn_D47_Data_byte_7_SHIFT (0U) 1126 #define CAN_WMBn_D47_Data_byte_7_WIDTH (8U) 1127 #define CAN_WMBn_D47_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_D47_Data_byte_7_SHIFT)) & CAN_WMBn_D47_Data_byte_7_MASK) 1128 1129 #define CAN_WMBn_D47_Data_byte_6_MASK (0xFF00U) 1130 #define CAN_WMBn_D47_Data_byte_6_SHIFT (8U) 1131 #define CAN_WMBn_D47_Data_byte_6_WIDTH (8U) 1132 #define CAN_WMBn_D47_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_D47_Data_byte_6_SHIFT)) & CAN_WMBn_D47_Data_byte_6_MASK) 1133 1134 #define CAN_WMBn_D47_Data_byte_5_MASK (0xFF0000U) 1135 #define CAN_WMBn_D47_Data_byte_5_SHIFT (16U) 1136 #define CAN_WMBn_D47_Data_byte_5_WIDTH (8U) 1137 #define CAN_WMBn_D47_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_D47_Data_byte_5_SHIFT)) & CAN_WMBn_D47_Data_byte_5_MASK) 1138 1139 #define CAN_WMBn_D47_Data_byte_4_MASK (0xFF000000U) 1140 #define CAN_WMBn_D47_Data_byte_4_SHIFT (24U) 1141 #define CAN_WMBn_D47_Data_byte_4_WIDTH (8U) 1142 #define CAN_WMBn_D47_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMBn_D47_Data_byte_4_SHIFT)) & CAN_WMBn_D47_Data_byte_4_MASK) 1143 /*! @} */ 1144 1145 /*! @name FDCTRL - CAN FD Control Register */ 1146 /*! @{ */ 1147 1148 #define CAN_FDCTRL_TDCVAL_MASK (0x3FU) 1149 #define CAN_FDCTRL_TDCVAL_SHIFT (0U) 1150 #define CAN_FDCTRL_TDCVAL_WIDTH (6U) 1151 #define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK) 1152 1153 #define CAN_FDCTRL_TDCOFF_MASK (0x1F00U) 1154 #define CAN_FDCTRL_TDCOFF_SHIFT (8U) 1155 #define CAN_FDCTRL_TDCOFF_WIDTH (5U) 1156 #define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK) 1157 1158 #define CAN_FDCTRL_TDCFAIL_MASK (0x4000U) 1159 #define CAN_FDCTRL_TDCFAIL_SHIFT (14U) 1160 #define CAN_FDCTRL_TDCFAIL_WIDTH (1U) 1161 #define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK) 1162 1163 #define CAN_FDCTRL_TDCEN_MASK (0x8000U) 1164 #define CAN_FDCTRL_TDCEN_SHIFT (15U) 1165 #define CAN_FDCTRL_TDCEN_WIDTH (1U) 1166 #define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK) 1167 1168 #define CAN_FDCTRL_MBDSR0_MASK (0x30000U) 1169 #define CAN_FDCTRL_MBDSR0_SHIFT (16U) 1170 #define CAN_FDCTRL_MBDSR0_WIDTH (2U) 1171 #define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK) 1172 1173 #define CAN_FDCTRL_FDRATE_MASK (0x80000000U) 1174 #define CAN_FDCTRL_FDRATE_SHIFT (31U) 1175 #define CAN_FDCTRL_FDRATE_WIDTH (1U) 1176 #define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK) 1177 /*! @} */ 1178 1179 /*! @name FDCBT - CAN FD Bit Timing Register */ 1180 /*! @{ */ 1181 1182 #define CAN_FDCBT_FPSEG2_MASK (0x7U) 1183 #define CAN_FDCBT_FPSEG2_SHIFT (0U) 1184 #define CAN_FDCBT_FPSEG2_WIDTH (3U) 1185 #define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK) 1186 1187 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) 1188 #define CAN_FDCBT_FPSEG1_SHIFT (5U) 1189 #define CAN_FDCBT_FPSEG1_WIDTH (3U) 1190 #define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK) 1191 1192 #define CAN_FDCBT_FPROPSEG_MASK (0x7C00U) 1193 #define CAN_FDCBT_FPROPSEG_SHIFT (10U) 1194 #define CAN_FDCBT_FPROPSEG_WIDTH (5U) 1195 #define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK) 1196 1197 #define CAN_FDCBT_FRJW_MASK (0x70000U) 1198 #define CAN_FDCBT_FRJW_SHIFT (16U) 1199 #define CAN_FDCBT_FRJW_WIDTH (3U) 1200 #define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK) 1201 1202 #define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U) 1203 #define CAN_FDCBT_FPRESDIV_SHIFT (20U) 1204 #define CAN_FDCBT_FPRESDIV_WIDTH (10U) 1205 #define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK) 1206 /*! @} */ 1207 1208 /*! @name FDCRC - CAN FD CRC Register */ 1209 /*! @{ */ 1210 1211 #define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU) 1212 #define CAN_FDCRC_FD_TXCRC_SHIFT (0U) 1213 #define CAN_FDCRC_FD_TXCRC_WIDTH (21U) 1214 #define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK) 1215 1216 #define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U) 1217 #define CAN_FDCRC_FD_MBCRC_SHIFT (24U) 1218 #define CAN_FDCRC_FD_MBCRC_WIDTH (7U) 1219 #define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK) 1220 /*! @} */ 1221 1222 /*! 1223 * @} 1224 */ /* end of group CAN_Register_Masks */ 1225 1226 /*! 1227 * @} 1228 */ /* end of group CAN_Peripheral_Access_Layer */ 1229 1230 #endif /* #if !defined(S32K116_FLEXCAN_H_) */ 1231
