1 /*
2  * Copyright 1997-2016 Freescale Semiconductor, Inc.
3  * Copyright 2016-2022 NXP
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*!
9  * @file S32K116_ERM.h
10  * @version 1.1
11  * @date 2022-01-21
12  * @brief Peripheral Access Layer for S32K116_ERM
13  *
14  * This file contains register definitions and macros for easy access to their
15  * bit fields.
16  *
17  * This file assumes LITTLE endian system.
18  */
19 
20 /**
21 * @page misra_violations MISRA-C:2012 violations
22 *
23 * @section [global]
24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
25 * The SoC header defines typedef for all modules.
26 *
27 * @section [global]
28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
29 * The SoC header defines macros for all modules and registers.
30 *
31 * @section [global]
32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
33 * These are generated macros used for accessing the bit-fields from registers.
34 *
35 * @section [global]
36 * Violates MISRA 2012 Required Rule 5.1, identifier clash
37 * The supported compilers use more than 31 significant characters for identifiers.
38 *
39 * @section [global]
40 * Violates MISRA 2012 Required Rule 5.2, identifier clash
41 * The supported compilers use more than 31 significant characters for identifiers.
42 *
43 * @section [global]
44 * Violates MISRA 2012 Required Rule 5.4, identifier clash
45 * The supported compilers use more than 31 significant characters for identifiers.
46 *
47 * @section [global]
48 * Violates MISRA 2012 Required Rule 5.5, identifier clash
49 * The supported compilers use more than 31 significant characters for identifiers.
50 *
51 * @section [global]
52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
53 * This type qualifier is needed to ensure correct I/O access and addressing.
54 */
55 
56 /* Prevention from multiple including the same memory map */
57 #if !defined(S32K116_ERM_H_)  /* Check if memory map has not been already included */
58 #define S32K116_ERM_H_
59 
60 #include "S32K116_COMMON.h"
61 
62 /* ----------------------------------------------------------------------------
63    -- ERM Peripheral Access Layer
64    ---------------------------------------------------------------------------- */
65 
66 /*!
67  * @addtogroup ERM_Peripheral_Access_Layer ERM Peripheral Access Layer
68  * @{
69  */
70 
71 /** ERM - Size of Registers Arrays */
72 #define ERM_EARn_COUNT                            1u
73 
74 /** ERM - Register Layout Typedef */
75 typedef struct {
76   __IO uint32_t CR0;                               /**< ERM Configuration Register 0, offset: 0x0 */
77   uint8_t RESERVED_0[12];
78   __IO uint32_t SR0;                               /**< ERM Status Register 0, offset: 0x10 */
79   uint8_t RESERVED_1[236];
80   __I  uint32_t EAR[ERM_EARn_COUNT];               /**< ERM Memory n Error Address Register, array offset: 0x100, array step: 0x4 */
81 } ERM_Type, *ERM_MemMapPtr;
82 
83 /** Number of instances of the ERM module. */
84 #define ERM_INSTANCE_COUNT                       (1u)
85 
86 /* ERM - Peripheral instance base addresses */
87 /** Peripheral ERM base address */
88 #define IP_ERM_BASE                              (0x40018000u)
89 /** Peripheral ERM base pointer */
90 #define IP_ERM                                   ((ERM_Type *)IP_ERM_BASE)
91 /** Array initializer of ERM peripheral base addresses */
92 #define IP_ERM_BASE_ADDRS                        { IP_ERM_BASE }
93 /** Array initializer of ERM peripheral base pointers */
94 #define IP_ERM_BASE_PTRS                         { IP_ERM }
95 
96 /* ----------------------------------------------------------------------------
97    -- ERM Register Masks
98    ---------------------------------------------------------------------------- */
99 
100 /*!
101  * @addtogroup ERM_Register_Masks ERM Register Masks
102  * @{
103  */
104 
105 /*! @name CR0 - ERM Configuration Register 0 */
106 /*! @{ */
107 
108 #define ERM_CR0_ENCIE0_MASK                      (0x40000000U)
109 #define ERM_CR0_ENCIE0_SHIFT                     (30U)
110 #define ERM_CR0_ENCIE0_WIDTH                     (1U)
111 #define ERM_CR0_ENCIE0(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE0_SHIFT)) & ERM_CR0_ENCIE0_MASK)
112 
113 #define ERM_CR0_ESCIE0_MASK                      (0x80000000U)
114 #define ERM_CR0_ESCIE0_SHIFT                     (31U)
115 #define ERM_CR0_ESCIE0_WIDTH                     (1U)
116 #define ERM_CR0_ESCIE0(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE0_SHIFT)) & ERM_CR0_ESCIE0_MASK)
117 /*! @} */
118 
119 /*! @name SR0 - ERM Status Register 0 */
120 /*! @{ */
121 
122 #define ERM_SR0_NCE0_MASK                        (0x40000000U)
123 #define ERM_SR0_NCE0_SHIFT                       (30U)
124 #define ERM_SR0_NCE0_WIDTH                       (1U)
125 #define ERM_SR0_NCE0(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE0_SHIFT)) & ERM_SR0_NCE0_MASK)
126 
127 #define ERM_SR0_SBC0_MASK                        (0x80000000U)
128 #define ERM_SR0_SBC0_SHIFT                       (31U)
129 #define ERM_SR0_SBC0_WIDTH                       (1U)
130 #define ERM_SR0_SBC0(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC0_SHIFT)) & ERM_SR0_SBC0_MASK)
131 /*! @} */
132 
133 /*! @name EAR - ERM Memory n Error Address Register */
134 /*! @{ */
135 
136 #define ERM_EAR_EAR_MASK                         (0xFFFFFFFFU)
137 #define ERM_EAR_EAR_SHIFT                        (0U)
138 #define ERM_EAR_EAR_WIDTH                        (32U)
139 #define ERM_EAR_EAR(x)                           (((uint32_t)(((uint32_t)(x)) << ERM_EAR_EAR_SHIFT)) & ERM_EAR_EAR_MASK)
140 /*! @} */
141 
142 /*!
143  * @}
144  */ /* end of group ERM_Register_Masks */
145 
146 /*!
147  * @}
148  */ /* end of group ERM_Peripheral_Access_Layer */
149 
150 #endif  /* #if !defined(S32K116_ERM_H_) */
151