1 /* 2 ** ################################################################### 3 ** Version: rev. 1.0, 2021-03-16 4 ** Build: b240325 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2024 NXP 11 ** SPDX-License-Identifier: BSD-3-Clause 12 ** 13 ** http: www.nxp.com 14 ** mail: support@nxp.com 15 ** 16 ** Revisions: 17 ** - rev. 1.0 (2021-03-16) 18 ** Initial version. 19 ** 20 ** ################################################################### 21 */ 22 23 #ifndef _RW612_FEATURES_H_ 24 #define _RW612_FEATURES_H_ 25 26 /* SOC module features */ 27 28 /* @brief ACOMP availability on the SoC. */ 29 #define FSL_FEATURE_SOC_ACOMP_COUNT (1) 30 /* @brief ADC availability on the SoC. */ 31 #define FSL_FEATURE_SOC_ADC_COUNT (2) 32 /* @brief AON_SOC_CIU availability on the SoC. */ 33 #define FSL_FEATURE_SOC_AON_SOC_CIU_COUNT (1) 34 /* @brief APU availability on the SoC. */ 35 #define FSL_FEATURE_SOC_APU_COUNT (2) 36 /* @brief BG availability on the SoC. */ 37 #define FSL_FEATURE_SOC_BG_COUNT (1) 38 /* @brief BLEAPU availability on the SoC. */ 39 #define FSL_FEATURE_SOC_BLEAPU_COUNT (1) 40 /* @brief BUCK11 availability on the SoC. */ 41 #define FSL_FEATURE_SOC_BUCK11_COUNT (1) 42 /* @brief BUCK18 availability on the SoC. */ 43 #define FSL_FEATURE_SOC_BUCK18_COUNT (1) 44 /* @brief CACHE64_CTRL availability on the SoC. */ 45 #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (2) 46 /* @brief CACHE64_POLSEL availability on the SoC. */ 47 #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (2) 48 /* @brief CAU availability on the SoC. */ 49 #define FSL_FEATURE_SOC_CAU_COUNT (1) 50 /* @brief CDOG availability on the SoC. */ 51 #define FSL_FEATURE_SOC_CDOG_COUNT (1) 52 /* @brief CIU1 availability on the SoC. */ 53 #define FSL_FEATURE_SOC_CIU1_COUNT (1) 54 /* @brief CIU2 availability on the SoC. */ 55 #define FSL_FEATURE_SOC_CIU2_COUNT (1) 56 /* @brief CLKCTL0 availability on the SoC. */ 57 #define FSL_FEATURE_SOC_CLKCTL0_COUNT (1) 58 /* @brief CLKCTL1 availability on the SoC. */ 59 #define FSL_FEATURE_SOC_CLKCTL1_COUNT (1) 60 /* @brief CRC availability on the SoC. */ 61 #define FSL_FEATURE_SOC_CRC_COUNT (1) 62 /* @brief CTIMER availability on the SoC. */ 63 #define FSL_FEATURE_SOC_CTIMER_COUNT (4) 64 /* @brief DAC availability on the SoC. */ 65 #define FSL_FEATURE_SOC_DAC_COUNT (1) 66 /* @brief DMA availability on the SoC. */ 67 #define FSL_FEATURE_SOC_DMA_COUNT (2) 68 /* @brief DMIC availability on the SoC. */ 69 #define FSL_FEATURE_SOC_DMIC_COUNT (1) 70 /* @brief ELS availability on the SoC. */ 71 #define FSL_FEATURE_SOC_ELS_COUNT (1) 72 /* @brief ENET availability on the SoC. */ 73 #define FSL_FEATURE_SOC_ENET_COUNT (1) 74 /* @brief FLEXCOMM availability on the SoC. */ 75 #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (5) 76 /* @brief FLEXSPI availability on the SoC. */ 77 #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) 78 /* @brief FREQME availability on the SoC. */ 79 #define FSL_FEATURE_SOC_FREQME_COUNT (1) 80 /* @brief GDMA availability on the SoC. */ 81 #define FSL_FEATURE_SOC_GDMA_COUNT (1) 82 /* @brief GPIO availability on the SoC. */ 83 #define FSL_FEATURE_SOC_GPIO_COUNT (2) 84 /* @brief I2C availability on the SoC. */ 85 #define FSL_FEATURE_SOC_I2C_COUNT (5) 86 /* @brief I2S availability on the SoC. */ 87 #define FSL_FEATURE_SOC_I2S_COUNT (5) 88 /* @brief INPUTMUX availability on the SoC. */ 89 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 90 /* @brief ITRC availability on the SoC. */ 91 #define FSL_FEATURE_SOC_ITRC_COUNT (1) 92 /* @brief LCDIC availability on the SoC. */ 93 #define FSL_FEATURE_SOC_LCDIC_COUNT (1) 94 /* @brief MCI_IO_MUX availability on the SoC. */ 95 #define FSL_FEATURE_SOC_MCI_IO_MUX_COUNT (1) 96 /* @brief MRT availability on the SoC. */ 97 #define FSL_FEATURE_SOC_MRT_COUNT (2) 98 /* @brief OCOTP availability on the SoC. */ 99 #define FSL_FEATURE_SOC_OCOTP_COUNT (1) 100 /* @brief OSTIMER availability on the SoC. */ 101 #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) 102 /* @brief PINT availability on the SoC. */ 103 #define FSL_FEATURE_SOC_PINT_COUNT (1) 104 /* @brief PKC availability on the SoC. */ 105 #define FSL_FEATURE_SOC_PKC_COUNT (1) 106 /* @brief POWERQUAD availability on the SoC. */ 107 #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) 108 /* @brief PUF availability on the SoC. */ 109 #define FSL_FEATURE_SOC_PUF_COUNT (1) 110 /* @brief RF_SYSCON availability on the SoC. */ 111 #define FSL_FEATURE_SOC_RF_SYSCON_COUNT (1) 112 /* @brief ROMC availability on the SoC. */ 113 #define FSL_FEATURE_SOC_ROMC_COUNT (1) 114 /* @brief RSTCTL0 availability on the SoC. */ 115 #define FSL_FEATURE_SOC_RSTCTL0_COUNT (1) 116 /* @brief RSTCTL1 availability on the SoC. */ 117 #define FSL_FEATURE_SOC_RSTCTL1_COUNT (1) 118 /* @brief RTC availability on the SoC. */ 119 #define FSL_FEATURE_SOC_RTC_COUNT (1) 120 /* @brief SCT availability on the SoC. */ 121 #define FSL_FEATURE_SOC_SCT_COUNT (1) 122 /* @brief SPI availability on the SoC. */ 123 #define FSL_FEATURE_SOC_SPI_COUNT (5) 124 /* @brief SYSCTL0 availability on the SoC. */ 125 #define FSL_FEATURE_SOC_SYSCTL0_COUNT (1) 126 /* @brief SYSCTL1 availability on the SoC. */ 127 #define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) 128 /* @brief SYSCTL2 availability on the SoC. */ 129 #define FSL_FEATURE_SOC_SYSCTL2_COUNT (1) 130 /* @brief SYSPLL_T3 availability on the SoC. */ 131 #define FSL_FEATURE_SOC_SYSPLL_T3_COUNT (1) 132 /* @brief SYSPLL_TCPU availability on the SoC. */ 133 #define FSL_FEATURE_SOC_SYSPLL_TCPU_COUNT (1) 134 /* @brief SOC_OTP_CTRL availability on the SoC. */ 135 #define FSL_FEATURE_SOC_SOC_OTP_CTRL_COUNT (1) 136 /* @brief SENSOR_CTRL availability on the SoC. */ 137 #define FSL_FEATURE_SOC_SENSOR_CTRL_COUNT (1) 138 /* @brief SDU_FN0_CARD availability on the SoC. */ 139 #define FSL_FEATURE_SOC_SDU_FN0_CARD_COUNT (1) 140 /* @brief SDU_FBR_CARD availability on the SoC. */ 141 #define FSL_FEATURE_SOC_SDU_FBR_CARD_COUNT (1) 142 /* @brief SDU_FN_CARD availability on the SoC. */ 143 #define FSL_FEATURE_SOC_SDU_FN_CARD_COUNT (1) 144 /* @brief TRNG availability on the SoC. */ 145 #define FSL_FEATURE_SOC_TRNG_COUNT (1) 146 /* @brief USART availability on the SoC. */ 147 #define FSL_FEATURE_SOC_USART_COUNT (5) 148 /* @brief USB availability on the SoC. */ 149 #define FSL_FEATURE_SOC_USB_COUNT (1) 150 /* @brief USIM availability on the SoC. */ 151 #define FSL_FEATURE_SOC_USIM_COUNT (1) 152 /* @brief UTICK availability on the SoC. */ 153 #define FSL_FEATURE_SOC_UTICK_COUNT (1) 154 /* @brief WLAPU availability on the SoC. */ 155 #define FSL_FEATURE_SOC_WLAPU_COUNT (1) 156 /* @brief WWDT availability on the SoC. */ 157 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 158 159 /* CACHE64_CTRL module features */ 160 161 /* @brief Cache Line size in byte. */ 162 #define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (32) 163 164 /* CACHE64_POLSEL module features */ 165 166 /* No feature definitions */ 167 168 /* CDOG module features */ 169 170 /* @brief CDOG Has No Reset */ 171 #define FSL_FEATURE_CDOG_HAS_NO_RESET (1) 172 /* @brief CDOG Load default configurations during init function */ 173 #define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (1) 174 175 /* CRC module features */ 176 177 /* @brief Has data register with name CRC */ 178 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 179 180 /* CTIMER module features */ 181 182 /* @brief CTIMER has no capture channel. */ 183 #define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) 184 /* @brief CTIMER has no capture 2 interrupt. */ 185 #define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) 186 /* @brief CTIMER capture 3 interrupt. */ 187 #define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) 188 /* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ 189 #define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) 190 /* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ 191 #define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) 192 /* @brief CTIMER Has register MSR */ 193 #define FSL_FEATURE_CTIMER_HAS_MSR (1) 194 195 /* DMA module features */ 196 197 /* @brief Number of channels */ 198 #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) (33) 199 /* @brief Number of all DMA channels */ 200 #define FSL_FEATURE_DMA_ALL_CHANNELS (66) 201 /* @brief Max Number of DMA channels */ 202 #define FSL_FEATURE_DMA_MAX_CHANNELS (33) 203 /* @brief Align size of DMA descriptor */ 204 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (1024) 205 /* @brief DMA head link descriptor table align size */ 206 #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) 207 208 /* DMIC module features */ 209 210 /* @brief Number of channels */ 211 #define FSL_FEATURE_DMIC_CHANNEL_NUM (4) 212 /* @brief DMIC channel support stereo data */ 213 #define FSL_FEATURE_DMIC_IO_HAS_STEREO_2_4_6 (1) 214 /* @brief DMIC does not support bypass channel clock */ 215 #define FSL_FEATURE_DMIC_IO_HAS_NO_BYPASS (1) 216 /* @brief DMIC channel FIFO register support sign extended */ 217 #define FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND (1) 218 /* @brief DMIC has no IOCFG register */ 219 #define FSL_FEATURE_DMIC_HAS_NO_IOCFG (1) 220 /* @brief DMIC has decimator reset function */ 221 #define FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC (1) 222 /* @brief DMIC has global channel synchronization function */ 223 #define FSL_FEATURE_DMIC_HAS_GLOBAL_SYNC_FUNC (0) 224 225 /* ENET module features */ 226 227 /* @brief Support Interrupt Coalesce */ 228 #define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1) 229 /* @brief Queue Size. */ 230 #define FSL_FEATURE_ENET_QUEUE (1) 231 /* @brief Has AVB Support. */ 232 #define FSL_FEATURE_ENET_HAS_AVB (0) 233 /* @brief Has Timer Pulse Width control. */ 234 #define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (1) 235 /* @brief Has Extend MDIO Support. */ 236 #define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1) 237 /* @brief Has Additional 1588 Timer Channel Interrupt. */ 238 #define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0) 239 /* @brief Support Interrupt Coalesce for each instance */ 240 #define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (0) 241 /* @brief Queue Size for each instance. */ 242 #define FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) (1) 243 /* @brief Has AVB Support for each instance. */ 244 #define FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(x) (0) 245 /* @brief Has Timer Pulse Width control for each instance. */ 246 #define FSL_FEATURE_ENET_INSTANCE_HAS_TIMER_PWCONTROLn(x) (1) 247 /* @brief Has Extend MDIO Support for each instance. */ 248 #define FSL_FEATURE_ENET_INSTANCE_HAS_EXTEND_MDIOn(x) (1) 249 /* @brief Has Additional 1588 Timer Channel Interrupt for each instance. */ 250 #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) 251 /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ 252 #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) 253 /* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ 254 #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) 255 /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ 256 #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) 257 /* @brief ENET Has Extra Clock Gate.(RW610). */ 258 #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (1) 259 /* @brief ENET support reset. */ 260 #define FSL_FEATURE_ENET_HAS_RSTCTL (1) 261 262 /* FLEXCOMM module features */ 263 264 /* @brief FLEXCOMM0 USART INDEX 0 */ 265 #define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) 266 /* @brief FLEXCOMM0 SPI INDEX 0 */ 267 #define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) 268 /* @brief FLEXCOMM0 I2C INDEX 0 */ 269 #define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) 270 /* @brief FLEXCOMM0 I2S INDEX 0 */ 271 #define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) 272 /* @brief FLEXCOMM1 USART INDEX 1 */ 273 #define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) 274 /* @brief FLEXCOMM1 SPI INDEX 1 */ 275 #define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) 276 /* @brief FLEXCOMM1 I2C INDEX 1 */ 277 #define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) 278 /* @brief FLEXCOMM1 I2S INDEX 1 */ 279 #define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) 280 /* @brief FLEXCOMM2 USART INDEX 2 */ 281 #define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) 282 /* @brief FLEXCOMM2 SPI INDEX 2 */ 283 #define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) 284 /* @brief FLEXCOMM2 I2C INDEX 2 */ 285 #define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) 286 /* @brief FLEXCOMM2 I2S INDEX 2 */ 287 #define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) 288 /* @brief FLEXCOMM3 USART INDEX 3 */ 289 #define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) 290 /* @brief FLEXCOMM3 SPI INDEX 3 */ 291 #define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) 292 /* @brief FLEXCOMM3 I2C INDEX 3 */ 293 #define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) 294 /* @brief FLEXCOMM3 I2S INDEX 3 */ 295 #define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) 296 /* @brief FLEXCOMM14 USART INDEX 14 */ 297 #define FSL_FEATURE_FLEXCOMM14_USART_INDEX (14) 298 /* @brief FLEXCOMM14 SPI(HS_SPI) INDEX 14 */ 299 #define FSL_FEATURE_FLEXCOMM14_SPI_INDEX (14) 300 /* @brief FLEXCOMM14 I2C INDEX 14 */ 301 #define FSL_FEATURE_FLEXCOMM14_I2C_INDEX (14) 302 /* @brief FLEXCOMM14 I2S INDEX 14 */ 303 #define FSL_FEATURE_FLEXCOMM14_I2S_INDEX (14) 304 /* @brief I2S has DMIC interconnection */ 305 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) \ 306 (((x) == FLEXCOMM0) ? (1) : \ 307 (((x) == FLEXCOMM1) ? (0) : \ 308 (((x) == FLEXCOMM2) ? (0) : \ 309 (((x) == FLEXCOMM3) ? (0) : \ 310 (((x) == FLEXCOMM14) ? (0) : (-1)))))) 311 312 /* FLEXSPI module features */ 313 314 /* @brief FlexSPI AHB buffer count */ 315 #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) 316 /* @brief FlexSPI has no MCR0 ARDFEN bit */ 317 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) 318 /* @brief FlexSPI has no MCR0 ATDFEN bit */ 319 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) 320 /* @brief FlexSPI has no IP parallel mode */ 321 #define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (1) 322 /* @brief FlexSPI has no AHB parallel mode */ 323 #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) 324 /* @brief FlexSPI support address shift */ 325 #define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) 326 /* @brief FlexSPI support sample clock source selection */ 327 #define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) 328 /* @brief FlexSPI support sample clock source or source_b selection */ 329 #define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) 330 /* @brief FlexSPI AHB RX buffer size (byte) */ 331 #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) 332 333 /* ADC module features */ 334 335 /* @brief Whether ADC has the single-end mode temp channel */ 336 #define FSL_FEATURE_ADC_HAS_NO_SINGLEEND_TEMP_CHANNEL (1) 337 /* @brief Whether ADC has the differential mode voice channel */ 338 #define FSL_FEATURE_ADC_HAS_NO_DIFFERENTIAL_VOICE_CHANNEL (1) 339 /* @brief Whether ADC has the differential mode temp channel */ 340 #define FSL_FEATURE_ADC_HAS_NO_DIFFERENTIAL_TEMP_CHANNEL (1) 341 342 /* GDMA module features */ 343 344 /* @brief GDMA Channel Number */ 345 #define FSL_FEATURE_GDMA_CHANNEL_NUM (4) 346 347 /* GPIO module features */ 348 349 /* @brief GPIO has interrupts */ 350 #define FSL_FEATURE_GPIO_HAS_INTERRUPT (1) 351 352 /* I2S module features */ 353 354 /* @brief I2S support dual channel transfer. */ 355 #define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1) 356 /* @brief I2S has DMIC interconnection. */ 357 #define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (1) 358 359 /* INPUTMUX module features */ 360 361 /* @brief Inputmux has DMA Request Enable */ 362 #define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) 363 /* @brief Inputmux has channel mux control */ 364 #define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) 365 366 /* MEMORY module features */ 367 368 /* @brief Memory map has offset between subsystems. */ 369 #define FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET (1) 370 371 /* MRT module features */ 372 373 /* @brief number of channels. */ 374 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) 375 376 /* OSTIMER module features */ 377 378 /* @brief Has no OS Timer control register in PMC */ 379 #define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1) 380 381 /* PINT module features */ 382 383 /* @brief Number of connected outputs */ 384 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) 385 386 /* POWERLIB module features */ 387 388 /* @brief Powerlib API is different with other LPC series devices. */ 389 #define FSL_FEATURE_POWERLIB_EXTEND (1) 390 391 /* RTC module features */ 392 393 /* @brief RTC has no reset control */ 394 #define FSL_FEATURE_RTC_HAS_NO_RESET (1) 395 /* @brief Has SUBSEC Register (register SUBSEC) */ 396 #define FSL_FEATURE_RTC_HAS_SUBSEC (1) 397 398 /* SCT module features */ 399 400 /* @brief Number of events */ 401 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) 402 /* @brief Number of states */ 403 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) 404 /* @brief Number of match capture */ 405 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) 406 /* @brief Number of outputs */ 407 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) 408 409 /* SPI module features */ 410 411 /* @brief SSEL pin count. */ 412 #define FSL_FEATURE_SPI_SSEL_COUNT (4) 413 414 /* TRNG module features */ 415 416 /* @brief TRNG does not support SCR4L. */ 417 #define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L (1) 418 /* @brief TRNG does not support SCR5L. */ 419 #define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L (1) 420 /* @brief TRNG does not support SCR6L. */ 421 #define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L (1) 422 /* @brief TRNG does not support PKRMAX. */ 423 #define FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX (1) 424 /* @brief TRNG does not support SAMP mode. */ 425 #define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE (1) 426 /* @brief TRNG does not support ACC. */ 427 #define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1) 428 /* @brief TRNG does not support SBLIM. */ 429 #define FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM (1) 430 /* @brief TRNG supports reset control. */ 431 #define FSL_FEATURE_TRNG_HAS_RSTCTL (1) 432 /* @brief TRNG supports dual oscillator mode. */ 433 #define FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS (1) 434 /* @brief TRNG supports control pin. */ 435 #define FSL_FEATURE_TRNG_HAS_CTRL_PIN (1) 436 437 /* USB module features */ 438 439 /* @brief USBC Atlantic Controller support on the SoC. */ 440 #define FSL_FEATURE_USB_ATLANTIC_EHCI_SUPPORT (1) 441 442 /* USIM module features */ 443 444 /* @brief USIM Tx/Rx FIFO size in byte. */ 445 #define FSL_FEATURE_USIM_FIFO_DEPTH (16) 446 447 /* UTICK module features */ 448 449 /* @brief UTICK does not support power down configure. */ 450 #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) 451 452 /* WWDT module features */ 453 454 /* @brief WWDT does not support oscillator lock. */ 455 #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) 456 /* @brief WWDT does not support power down configure. */ 457 #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) 458 459 #endif /* _RW612_FEATURES_H_ */ 460 461
