1 /*
2 ** ###################################################################
3 **     Version:             rev. 1.0, 2018-10-02
4 **     Build:               b180815
5 **
6 **     Abstract:
7 **         Chip specific module features.
8 **
9 **     Copyright 2016 Freescale Semiconductor, Inc.
10 **     Copyright 2016-2018 NXP
11 **
12 **     SPDX-License-Identifier: BSD-3-Clause
13 **
14 **     http:                 www.nxp.com
15 **     mail:                 support@nxp.com
16 **
17 **     Revisions:
18 **     - rev. 1.0 (2018-10-02)
19 **         Initial version.
20 **
21 ** ###################################################################
22 */
23 
24 #ifndef _RV32M1_zero_riscy_FEATURES_H_
25 #define _RV32M1_zero_riscy_FEATURES_H_
26 
27 /* SOC module features */
28 
29 /* @brief CAU3 availability on the SoC. */
30 #define FSL_FEATURE_SOC_CAU3_COUNT (1)
31 /* @brief CRC availability on the SoC. */
32 #define FSL_FEATURE_SOC_CRC_COUNT (1)
33 /* @brief DMAMUX availability on the SoC. */
34 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
35 /* @brief EDMA availability on the SoC. */
36 #define FSL_FEATURE_SOC_EDMA_COUNT (1)
37 /* @brief EMVSIM availability on the SoC. */
38 #define FSL_FEATURE_SOC_EMVSIM_COUNT (1)
39 /* @brief EVENT availability on the SoC. */
40 #define FSL_FEATURE_SOC_EVENT_COUNT (1)
41 /* @brief EWM availability on the SoC. */
42 #define FSL_FEATURE_SOC_EWM_COUNT (1)
43 /* @brief FB availability on the SoC. */
44 #define FSL_FEATURE_SOC_FB_COUNT (1)
45 /* @brief FGPIO availability on the SoC. */
46 #define FSL_FEATURE_SOC_FGPIO_COUNT (1)
47 /* @brief FLASH availability on the SoC. */
48 #define FSL_FEATURE_SOC_FLASH_COUNT (1)
49 /* @brief FLEXIO availability on the SoC. */
50 #define FSL_FEATURE_SOC_FLEXIO_COUNT (1)
51 /* @brief GPIO availability on the SoC. */
52 #define FSL_FEATURE_SOC_GPIO_COUNT (5)
53 /* @brief I2S availability on the SoC. */
54 #define FSL_FEATURE_SOC_I2S_COUNT (1)
55 /* @brief INTMUX availability on the SoC. */
56 #define FSL_FEATURE_SOC_INTMUX_COUNT (1)
57 /* @brief LLWU availability on the SoC. */
58 #define FSL_FEATURE_SOC_LLWU_COUNT (2)
59 /* @brief LPADC availability on the SoC. */
60 #define FSL_FEATURE_SOC_LPADC_COUNT (1)
61 /* @brief LPCMP availability on the SoC. */
62 #define FSL_FEATURE_SOC_LPCMP_COUNT (2)
63 /* @brief LPDAC availability on the SoC. */
64 #define FSL_FEATURE_SOC_LPDAC_COUNT (1)
65 /* @brief LPI2C availability on the SoC. */
66 #define FSL_FEATURE_SOC_LPI2C_COUNT (4)
67 /* @brief LPIT availability on the SoC. */
68 #define FSL_FEATURE_SOC_LPIT_COUNT (2)
69 /* @brief LPSPI availability on the SoC. */
70 #define FSL_FEATURE_SOC_LPSPI_COUNT (4)
71 /* @brief LPTMR availability on the SoC. */
72 #define FSL_FEATURE_SOC_LPTMR_COUNT (3)
73 /* @brief LPUART availability on the SoC. */
74 #define FSL_FEATURE_SOC_LPUART_COUNT (4)
75 /* @brief MCM availability on the SoC. */
76 #define FSL_FEATURE_SOC_MCM_COUNT (1)
77 /* @brief MMDVSQ availability on the SoC. */
78 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (1)
79 /* @brief MSCM availability on the SoC. */
80 #define FSL_FEATURE_SOC_MSCM_COUNT (1)
81 /* @brief MTB availability on the SoC. */
82 #define FSL_FEATURE_SOC_MTB_COUNT (1)
83 /* @brief MTBDWT availability on the SoC. */
84 #define FSL_FEATURE_SOC_MTBDWT_COUNT (1)
85 /* @brief MU availability on the SoC. */
86 #define FSL_FEATURE_SOC_MU_COUNT (1)
87 /* @brief PCC availability on the SoC. */
88 #define FSL_FEATURE_SOC_PCC_COUNT (2)
89 /* @brief PORT availability on the SoC. */
90 #define FSL_FEATURE_SOC_PORT_COUNT (5)
91 /* @brief ROM availability on the SoC. */
92 #define FSL_FEATURE_SOC_ROM_COUNT (1)
93 /* @brief RSIM availability on the SoC. */
94 #define FSL_FEATURE_SOC_RSIM_COUNT (1)
95 /* @brief RTC availability on the SoC. */
96 #define FSL_FEATURE_SOC_RTC_COUNT (1)
97 /* @brief SCG availability on the SoC. */
98 #define FSL_FEATURE_SOC_SCG_COUNT (1)
99 /* @brief SEMA42 availability on the SoC. */
100 #define FSL_FEATURE_SOC_SEMA42_COUNT (2)
101 /* @brief SIM availability on the SoC. */
102 #define FSL_FEATURE_SOC_SIM_COUNT (1)
103 /* @brief SMC availability on the SoC. */
104 #define FSL_FEATURE_SOC_SMC_COUNT (2)
105 /* @brief SPM availability on the SoC. */
106 #define FSL_FEATURE_SOC_SPM_COUNT (1)
107 /* @brief TPM availability on the SoC. */
108 #define FSL_FEATURE_SOC_TPM_COUNT (4)
109 /* @brief TRGMUX availability on the SoC. */
110 #define FSL_FEATURE_SOC_TRGMUX_COUNT (2)
111 /* @brief TRNG availability on the SoC. */
112 #define FSL_FEATURE_SOC_TRNG_COUNT (1)
113 /* @brief TSTMR availability on the SoC. */
114 #define FSL_FEATURE_SOC_TSTMR_COUNT (1)
115 /* @brief USB availability on the SoC. */
116 #define FSL_FEATURE_SOC_USB_COUNT (1)
117 /* @brief USBVREG availability on the SoC. */
118 #define FSL_FEATURE_SOC_USBVREG_COUNT (1)
119 /* @brief USDHC availability on the SoC. */
120 #define FSL_FEATURE_SOC_USDHC_COUNT (1)
121 /* @brief VREF availability on the SoC. */
122 #define FSL_FEATURE_SOC_VREF_COUNT (1)
123 /* @brief WDOG availability on the SoC. */
124 #define FSL_FEATURE_SOC_WDOG_COUNT (2)
125 /* @brief XRDC availability on the SoC. */
126 #define FSL_FEATURE_SOC_XRDC_COUNT (1)
127 /* @brief ZLL availability on the SoC. */
128 #define FSL_FEATURE_SOC_ZLL_COUNT (1)
129 
130 /* LPADC module features */
131 
132 /* @brief Has differential mode (bitfield CMDLn[DIFF]). */
133 #define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)
134 /* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
135 #define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0)
136 /* @brief Has internal clock (bitfield CFG[ADCKEN]). */
137 #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (1)
138 /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
139 #define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (1)
140 /* @brief Has calibration (bitfield CFG[CALOFS]). */
141 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (1)
142 /* @brief Has offset trim (register OFSTRIM). */
143 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
144 
145 /* CRC module features */
146 
147 /* @brief Has data register with name CRC */
148 #define FSL_FEATURE_CRC_HAS_CRC_REG (0)
149 
150 /* EDMA module features */
151 
152 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
153 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (8)
154 /* @brief Total number of DMA channels on all modules. */
155 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (8)
156 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
157 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
158 /* @brief Has DMA_Error interrupt vector. */
159 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0)
160 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
161 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (8)
162 
163 /* DMAMUX module features */
164 
165 /* @brief Number of DMA channels (related to number of register CHCFGn). */
166 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (8)
167 /* @brief Total number of DMA channels on all modules. */
168 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 8)
169 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
170 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
171 /* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */
172 #define FSL_FEATURE_DMAMUX_HAS_A_ON (1)
173 
174 /* EWM module features */
175 
176 /* @brief Has clock select (register CLKCTRL). */
177 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT  (0)
178 /* @brief Has clock prescaler (register CLKPRESCALER). */
179 #define FSL_FEATURE_EWM_HAS_PRESCALER  (1)
180 
181 /* FB module features */
182 
183 /* No feature definitions */
184 
185 /* FLEXIO module features */
186 
187 /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
188 #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
189 /* @brief Has Pin Data Input Register (FLEXIO_PIN) */
190 #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1)
191 /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
192 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1)
193 /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
194 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1)
195 /* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */
196 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1)
197 /* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */
198 #define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1)
199 /* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */
200 #define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1)
201 /* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */
202 #define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1)
203 /* @brief Reset value of the FLEXIO_VERID register */
204 #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001)
205 /* @brief Reset value of the FLEXIO_PARAM register */
206 #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808)
207 
208 /* FLASH module features */
209 
210 /* @brief Current core ID. */
211 #define FSL_FEATURE_FLASH_CURRENT_CORE_ID (1)
212 /* @brief Is of type FTFA. */
213 #define FSL_FEATURE_FLASH_IS_FTFA (0)
214 /* @brief Is of type FTFE. */
215 #define FSL_FEATURE_FLASH_IS_FTFE (1)
216 /* @brief Is of type FTFL. */
217 #define FSL_FEATURE_FLASH_IS_FTFL (0)
218 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
219 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
220 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
221 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
222 /* @brief Has EEPROM region protection (register FEPROT). */
223 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
224 /* @brief Has data flash region protection (register FDPROT). */
225 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
226 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
227 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1)
228 /* @brief Has flash cache control in FMC module. */
229 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
230 /* @brief Has flash cache control in MCM module. */
231 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
232 /* @brief Has flash cache control in MSCM module. */
233 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (1)
234 /* @brief Has prefetch speculation control in flash, such as kv5x. */
235 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
236 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for RV32M1 */
237 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (1)
238 /* @brief P-Flash start address. */
239 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x01000000)
240 /* @brief P-Flash block count. */
241 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
242 /* @brief P-Flash block size. */
243 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144)
244 /* @brief P-Flash sector size. */
245 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048)
246 /* @brief P-Flash write unit size. */
247 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
248 /* @brief P-Flash data path width. */
249 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8)
250 /* @brief P-Flash block swap feature. */
251 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
252 /* @brief P-Flash protection region count. */
253 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (16)
254 /* @brief Has multiple flash. */
255 #define FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH (1)
256 /* @brief Flash memory count. */
257 #define FSL_FEATURE_FLASH_MEMORY_COUNT (2)
258 /* @brief P-Flash start address. */
259 #define FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS (0x00000000)
260 /* @brief P-Flash block count. */
261 #define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT (2)
262 /* @brief P-Flash block size. */
263 #define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE (524288)
264 /* @brief P-Flash sector size. */
265 #define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE (4096)
266 /* @brief P-Flash write unit size. */
267 #define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE (8)
268 /* @brief P-Flash data path width. */
269 #define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_DATA_PATH_WIDTH (16)
270 /* @brief P-Flash protection region count. */
271 #define FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT (64)
272 /* @brief P-Flash block swap feature. */
273 #define FSL_FEATURE_FLASH_HAS_1_PFLASH_BLOCK_SWAP (1)
274 /* @brief Has FlexNVM memory. */
275 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
276 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
277 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
278 /* @brief FlexNVM block count. */
279 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
280 /* @brief FlexNVM block size. */
281 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
282 /* @brief FlexNVM sector size. */
283 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
284 /* @brief FlexNVM write unit size. */
285 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
286 /* @brief FlexNVM data path width. */
287 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
288 /* @brief Has FlexRAM memory. */
289 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
290 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
291 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x48000000)
292 /* @brief FlexRAM size. */
293 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
294 /* @brief Has 0x00 Read 1s Block command. */
295 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
296 /* @brief Flash 1 has 0x00 Read 1s Block command. */
297 #define FSL_FEATURE_FLASH_HAS_1_READ_1S_BLOCK_CMD (1)
298 /* @brief Has 0x01 Read 1s Section command. */
299 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
300 /* @brief Has 0x02 Program Check command. */
301 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
302 /* @brief Has 0x03 Read Resource command. */
303 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (0)
304 /* @brief Has 0x06 Program Longword command. */
305 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
306 /* @brief Has 0x07 Program Phrase command. */
307 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
308 /* @brief Has 0x08 Erase Flash Block command. */
309 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
310 /* @brief Flash 1 has 0x08 Erase Flash Block command. */
311 #define FSL_FEATURE_FLASH_HAS_1_ERASE_FLASH_BLOCK_CMD (1)
312 /* @brief Has 0x09 Erase Flash Sector command. */
313 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
314 /* @brief Has 0x0B Program Section command. */
315 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
316 /* @brief Has 0x0C Generate CRC signature for selected program flash sectors. */
317 #define FSL_FEATURE_FLASH_HAS_GENERATE_CRC_CMD (1)
318 /* @brief Has 0x40 Read 1s All Blocks command. */
319 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
320 /* @brief Has 0x41 Read Once command. */
321 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
322 /* @brief Has 0x43 Program Once command. */
323 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
324 /* @brief Has 0x44 Erase All Blocks command. */
325 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
326 /* @brief Has 0x45 Verify Backdoor Access Key command. */
327 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
328 /* @brief Has 0x46 Swap Control command. */
329 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
330 /* @brief Flash 1 has 0x46 Swap Control command. */
331 #define FSL_FEATURE_FLASH_HAS_1_SWAP_CONTROL_CMD (1)
332 /* @brief Has 0x49 Erase All Blocks Unsecure command. */
333 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
334 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
335 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
336 /* @brief Has 0x4B Erase All Execute-only Segments command. */
337 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
338 /* @brief Has 0x80 Program Partition command. */
339 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
340 /* @brief Has 0x81 Set FlexRAM Function command. */
341 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
342 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
343 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
344 /* @brief P-Flash Erase sector command address alignment. */
345 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8)
346 /* @brief P-Flash Erase sector command address alignment. */
347 #define FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT (16)
348 /* @brief P-Flash Program/Verify section command address alignment. */
349 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8)
350 /* @brief P-Flash Program/Verify section command address alignment. */
351 #define FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT (16)
352 /* @brief P-Flash Read resource command address alignment. */
353 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
354 /* @brief P-Flash Program check command address alignment. */
355 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
356 /* @brief P-Flash Program check command address alignment. */
357 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
358 /* @brief P-Flash 1 Program check command address alignment. */
359 #define FSL_FEATURE_FLASH_PFLASH_1_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16)
360 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
361 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
362 /* @brief FlexNVM Erase sector command address alignment. */
363 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
364 /* @brief FlexNVM Rrogram/Verify section command address alignment. */
365 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
366 /* @brief FlexNVM Read resource command address alignment. */
367 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
368 /* @brief FlexNVM Program check command address alignment. */
369 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
370 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
371 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
372 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
373 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
374 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
375 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
376 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
377 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
378 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
379 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
380 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
381 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
382 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
383 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
384 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
385 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
386 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
387 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
388 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
389 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
390 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
391 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
392 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
393 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
394 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
395 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
396 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
397 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
398 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
399 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
400 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
401 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
402 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
403 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
404 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
405 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
406 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
407 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
408 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
409 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
410 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
411 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
412 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
413 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
414 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
415 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
416 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
417 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
418 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
419 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
420 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
421 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
422 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
423 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
424 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
425 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
426 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
427 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
428 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
429 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
430 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
431 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
432 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
433 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
434 
435 /* GPIO module features */
436 
437 /* @brief Has fast (single cycle) access capability via a dedicated memory region. */
438 #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1)
439 /* @brief Has port input disable register (PIDR). */
440 #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
441 /* @brief Has dedicated interrupt vector. */
442 #define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1)
443 
444 /* SAI module features */
445 
446 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
447 #define FSL_FEATURE_SAI_FIFO_COUNT (8)
448 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
449 #define FSL_FEATURE_SAI_CHANNEL_COUNT (2)
450 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
451 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
452 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
453 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1)
454 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
455 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
456 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
457 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
458 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
459 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
460 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
461 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
462 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
463 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0)
464 /* @brief Interrupt source number */
465 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (1)
466 /* @brief Has register of MCR. */
467 #define FSL_FEATURE_SAI_HAS_MCR (0)
468 /* @brief Has bit field MICS of the MCR register. */
469 #define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1)
470 /* @brief Has register of MDR */
471 #define FSL_FEATURE_SAI_HAS_MDR (0)
472 /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */
473 #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0)
474 
475 /* INTMUX module features */
476 
477 /* @brief Number of INTMUX channels (related to number of register CHn_CSR). */
478 #define FSL_FEATURE_INTMUX_CHANNEL_COUNT (8)
479 /* @brief Number of INTMUX IRQ source. */
480 #define FSL_FEATURE_INTMUX_IRQ_COUNT (32)
481 /* @brief The start IRQ index of first INTMUX source IRQ. */
482 #define FSL_FEATURE_INTMUX_IRQ_START_INDEX (32)
483 /* @brief The direction of INTMUX. OUT, route the CM4 subsystem IRQ to System. */
484 #define FSL_FEATURE_INTMUX_DIRECTION_OUT (0)
485 /* @brief The total number of level1 interrupt vectors. */
486 #define FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS (32)
487 
488 /* LLWU module features */
489 
490 /* @brief Maximum number of pins connected to LLWU device. */
491 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (32)
492 /* @brief Maximum number of internal modules connected to LLWU device. */
493 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
494 /* @brief Number of digital filters. */
495 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
496 /* @brief Has MF register. */
497 #define FSL_FEATURE_LLWU_HAS_MF (0)
498 /* @brief Has PF register. */
499 #define FSL_FEATURE_LLWU_HAS_PF (1)
500 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
501 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
502 /* @brief Has no internal module wakeup flag register. */
503 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (1)
504 /* @brief Has external pin 0 connected to LLWU device. */
505 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
506 /* @brief Index of port of external pin. */
507 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOA_IDX)
508 /* @brief Number of external pin port on specified port. */
509 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
510 /* @brief Has external pin 1 connected to LLWU device. */
511 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
512 /* @brief Index of port of external pin. */
513 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOA_IDX)
514 /* @brief Number of external pin port on specified port. */
515 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
516 /* @brief Has external pin 2 connected to LLWU device. */
517 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
518 /* @brief Index of port of external pin. */
519 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOA_IDX)
520 /* @brief Number of external pin port on specified port. */
521 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (22)
522 /* @brief Has external pin 3 connected to LLWU device. */
523 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
524 /* @brief Index of port of external pin. */
525 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
526 /* @brief Number of external pin port on specified port. */
527 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (30)
528 /* @brief Has external pin 4 connected to LLWU device. */
529 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
530 /* @brief Index of port of external pin. */
531 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOB_IDX)
532 /* @brief Number of external pin port on specified port. */
533 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (1)
534 /* @brief Has external pin 5 connected to LLWU device. */
535 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
536 /* @brief Index of port of external pin. */
537 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
538 /* @brief Number of external pin port on specified port. */
539 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (2)
540 /* @brief Has external pin 6 connected to LLWU device. */
541 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
542 /* @brief Index of port of external pin. */
543 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOB_IDX)
544 /* @brief Number of external pin port on specified port. */
545 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (4)
546 /* @brief Has external pin 7 connected to LLWU device. */
547 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
548 /* @brief Index of port of external pin. */
549 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOB_IDX)
550 /* @brief Number of external pin port on specified port. */
551 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (6)
552 /* @brief Has external pin 8 connected to LLWU device. */
553 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
554 /* @brief Index of port of external pin. */
555 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX)
556 /* @brief Number of external pin port on specified port. */
557 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (7)
558 /* @brief Has external pin 9 connected to LLWU device. */
559 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
560 /* @brief Index of port of external pin. */
561 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOB_IDX)
562 /* @brief Number of external pin port on specified port. */
563 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (8)
564 /* @brief Has external pin 10 connected to LLWU device. */
565 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
566 /* @brief Index of port of external pin. */
567 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOB_IDX)
568 /* @brief Number of external pin port on specified port. */
569 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (16)
570 /* @brief Has external pin 11 connected to LLWU device. */
571 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
572 /* @brief Index of port of external pin. */
573 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOB_IDX)
574 /* @brief Number of external pin port on specified port. */
575 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (20)
576 /* @brief Has external pin 12 connected to LLWU device. */
577 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
578 /* @brief Index of port of external pin. */
579 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOB_IDX)
580 /* @brief Number of external pin port on specified port. */
581 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (22)
582 /* @brief Has external pin 13 connected to LLWU device. */
583 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
584 /* @brief Index of port of external pin. */
585 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOB_IDX)
586 /* @brief Number of external pin port on specified port. */
587 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (25)
588 /* @brief Has external pin 14 connected to LLWU device. */
589 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
590 /* @brief Index of port of external pin. */
591 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOB_IDX)
592 /* @brief Number of external pin port on specified port. */
593 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (28)
594 /* @brief Has external pin 15 connected to LLWU device. */
595 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
596 /* @brief Index of port of external pin. */
597 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX)
598 /* @brief Number of external pin port on specified port. */
599 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7)
600 /* @brief Has external pin 16 connected to LLWU device. */
601 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1)
602 /* @brief Index of port of external pin. */
603 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOC_IDX)
604 /* @brief Number of external pin port on specified port. */
605 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (9)
606 /* @brief Has external pin 17 connected to LLWU device. */
607 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1)
608 /* @brief Index of port of external pin. */
609 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOC_IDX)
610 /* @brief Number of external pin port on specified port. */
611 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (11)
612 /* @brief Has external pin 18 connected to LLWU device. */
613 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1)
614 /* @brief Index of port of external pin. */
615 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOC_IDX)
616 /* @brief Number of external pin port on specified port. */
617 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (12)
618 /* @brief Has external pin 19 connected to LLWU device. */
619 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1)
620 /* @brief Index of port of external pin. */
621 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOD_IDX)
622 /* @brief Number of external pin port on specified port. */
623 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (8)
624 /* @brief Has external pin 20 connected to LLWU device. */
625 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1)
626 /* @brief Index of port of external pin. */
627 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOD_IDX)
628 /* @brief Number of external pin port on specified port. */
629 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (10)
630 /* @brief Has external pin 21 connected to LLWU device. */
631 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1)
632 /* @brief Index of port of external pin. */
633 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX)
634 /* @brief Number of external pin port on specified port. */
635 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (1)
636 /* @brief Has external pin 22 connected to LLWU device. */
637 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1)
638 /* @brief Index of port of external pin. */
639 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOE_IDX)
640 /* @brief Number of external pin port on specified port. */
641 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (3)
642 /* @brief Has external pin 23 connected to LLWU device. */
643 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1)
644 /* @brief Index of port of external pin. */
645 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOE_IDX)
646 /* @brief Number of external pin port on specified port. */
647 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (8)
648 /* @brief Has external pin 24 connected to LLWU device. */
649 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (1)
650 /* @brief Index of port of external pin. */
651 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (GPIOE_IDX)
652 /* @brief Number of external pin port on specified port. */
653 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (9)
654 /* @brief Has external pin 25 connected to LLWU device. */
655 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (1)
656 /* @brief Index of port of external pin. */
657 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (GPIOE_IDX)
658 /* @brief Number of external pin port on specified port. */
659 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (10)
660 /* @brief Has external pin 26 connected to LLWU device. */
661 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (1)
662 /* @brief Index of port of external pin. */
663 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (GPIOE_IDX)
664 /* @brief Number of external pin port on specified port. */
665 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (12)
666 /* @brief Has external pin 27 connected to LLWU device. */
667 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
668 /* @brief Index of port of external pin. */
669 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
670 /* @brief Number of external pin port on specified port. */
671 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
672 /* @brief Has external pin 28 connected to LLWU device. */
673 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
674 /* @brief Index of port of external pin. */
675 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
676 /* @brief Number of external pin port on specified port. */
677 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
678 /* @brief Has external pin 29 connected to LLWU device. */
679 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
680 /* @brief Index of port of external pin. */
681 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
682 /* @brief Number of external pin port on specified port. */
683 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
684 /* @brief Has external pin 30 connected to LLWU device. */
685 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
686 /* @brief Index of port of external pin. */
687 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
688 /* @brief Number of external pin port on specified port. */
689 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
690 /* @brief Has external pin 31 connected to LLWU device. */
691 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
692 /* @brief Index of port of external pin. */
693 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
694 /* @brief Number of external pin port on specified port. */
695 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
696 /* @brief Has internal module 0 connected to LLWU device. */
697 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
698 /* @brief Has internal module 1 connected to LLWU device. */
699 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
700 /* @brief Has internal module 2 connected to LLWU device. */
701 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
702 /* @brief Has internal module 3 connected to LLWU device. */
703 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
704 /* @brief Has internal module 4 connected to LLWU device. */
705 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
706 /* @brief Has internal module 5 connected to LLWU device. */
707 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
708 /* @brief Has internal module 6 connected to LLWU device. */
709 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (1)
710 /* @brief Has internal module 7 connected to LLWU device. */
711 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
712 /* @brief Has LLWU_VERID. */
713 #define FSL_FEATURE_LLWU_HAS_VERID (1)
714 /* @brief Has LLWU_PARAM. */
715 #define FSL_FEATURE_LLWU_HAS_PARAM (1)
716 /* @brief LLWU register bit width. */
717 #define FSL_FEATURE_LLWU_REG_BITWIDTH (32)
718 /* @brief Has DMA Enable register LLWU_DE. */
719 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (1)
720 
721 /* LPDAC module features */
722 
723 /* @brief FIFO size. */
724 #define FSL_FEATURE_LPDAC_FIFO_SIZE (16)
725 
726 /* LPI2C module features */
727 
728 /* @brief Has separate DMA RX and TX requests. */
729 #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
730 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
731 #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4)
732 
733 /* LPIT module features */
734 
735 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
736 #define FSL_FEATURE_LPIT_TIMER_COUNT (4)
737 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
738 #define FSL_FEATURE_LPIT_HAS_LIFETIME_TIMER (0)
739 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
740 #define FSL_FEATURE_LPIT_HAS_CHAIN_MODE (0)
741 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
742 #define FSL_FEATURE_LPIT_HAS_SHARED_IRQ_HANDLER (0)
743 
744 /* LPSPI module features */
745 
746 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
747 #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4)
748 /* @brief Has separate DMA RX and TX requests. */
749 #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
750 
751 /* LPTMR module features */
752 
753 /* @brief Has shared interrupt handler with another LPTMR module. */
754 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
755 /* @brief Whether LPTMR counter is 32 bits width. */
756 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1)
757 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
758 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1)
759 
760 /* LPUART module features */
761 
762 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
763 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
764 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
765 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
766 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
767 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
768 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
769 #define FSL_FEATURE_LPUART_HAS_FIFO (1)
770 /* @brief Has 32-bit register MODIR */
771 #define FSL_FEATURE_LPUART_HAS_MODIR (1)
772 /* @brief Hardware flow control (RTS, CTS) is supported. */
773 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
774 /* @brief Infrared (modulation) is supported. */
775 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
776 /* @brief 2 bits long stop bit is available. */
777 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
778 /* @brief If 10-bit mode is supported. */
779 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
780 /* @brief If 7-bit mode is supported. */
781 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1)
782 /* @brief Baud rate fine adjustment is available. */
783 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
784 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
785 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
786 /* @brief Baud rate oversampling is available. */
787 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
788 /* @brief Baud rate oversampling is available. */
789 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
790 /* @brief Peripheral type. */
791 #define FSL_FEATURE_LPUART_IS_SCI (1)
792 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
793 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8)
794 /* @brief Maximal data width without parity bit. */
795 #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
796 /* @brief Maximal data width with parity bit. */
797 #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
798 /* @brief Supports two match addresses to filter incoming frames. */
799 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
800 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
801 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
802 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
803 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
804 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
805 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
806 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
807 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
808 /* @brief Has improved smart card (ISO7816 protocol) support. */
809 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
810 /* @brief Has local operation network (CEA709.1-B protocol) support. */
811 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
812 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
813 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
814 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
815 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
816 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
817 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
818 /* @brief Has separate DMA RX and TX requests. */
819 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
820 /* @brief Has separate RX and TX interrupts. */
821 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
822 /* @brief Has LPAURT_PARAM. */
823 #define FSL_FEATURE_LPUART_HAS_PARAM (1)
824 /* @brief Has LPUART_VERID. */
825 #define FSL_FEATURE_LPUART_HAS_VERID (1)
826 /* @brief Has LPUART_GLOBAL. */
827 #define FSL_FEATURE_LPUART_HAS_GLOBAL (1)
828 /* @brief Has LPUART_PINCFG. */
829 #define FSL_FEATURE_LPUART_HAS_PINCFG (1)
830 
831 /* MCM module features */
832 
833 /* @brief Has L1 cache. */
834 #define FSL_FEATURE_HAS_L1CACHE (1)
835 
836 /* MSCM module features */
837 
838 /* @brief Number of configuration information for processors. */
839 #define FSL_FEATURE_MSCM_HAS_CP_COUNT (2)
840 /* @brief Has data cache. */
841 #define FSL_FEATURE_MSCM_HAS_DATACACHE (0)
842 
843 /* MU module features */
844 
845 /* @brief MU side for current core */
846 #define FSL_FEATURE_MU_SIDE_B (1)
847 /* @brief MU Has register CCR */
848 #define FSL_FEATURE_MU_HAS_CCR (1)
849 /* @brief MU Has register SR[RS], BSR[ARS] */
850 #define FSL_FEATURE_MU_HAS_SR_RS (0)
851 /* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */
852 #define FSL_FEATURE_MU_HAS_RESET_INT (1)
853 /* @brief MU Has register SR[MURIP] */
854 #define FSL_FEATURE_MU_HAS_SR_MURIP (1)
855 /* @brief brief MU Has register SR[HRIP] */
856 #define FSL_FEATURE_MU_HAS_SR_HRIP (1)
857 /* @brief brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */
858 #define FSL_FEATURE_MU_NO_CLKE (0)
859 /* @brief brief MU does not support NMI, CR[NMI]. */
860 #define FSL_FEATURE_MU_NO_NMI (0)
861 /* @brief brief MU does not support hold the other core reset. CR[RSTH] or CCR[RSTH]. */
862 #define FSL_FEATURE_MU_NO_RSTH (0)
863 /* @brief brief MU does not supports MU reset, CR[MUR]. */
864 #define FSL_FEATURE_MU_NO_MUR (0)
865 /* @brief brief MU does not supports hardware reset, CR[HR] or CCR[HR]. */
866 #define FSL_FEATURE_MU_NO_HR (0)
867 /* @brief brief MU supports mask the hardware reset. CR[HRM] or CCR[HRM]. */
868 #define FSL_FEATURE_MU_HAS_HRM (1)
869 
870 /* interrupt module features */
871 
872 /* @brief Lowest interrupt request number. */
873 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
874 /* @brief Highest interrupt request number. */
875 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (31)
876 
877 /* PCC module features */
878 
879 /* @brief Has CLOCK GATE CONTROL bit (e.g PCC_CGC) */
880 #define FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL (1)
881 
882 /* PORT module features */
883 
884 /* @brief Has control lock (register bit PCR[LK]). */
885 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
886 /* @brief Has open drain control (register bit PCR[ODE]). */
887 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
888 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
889 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
890 /* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */
891 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
892 /* @brief Has pull resistor selection available. */
893 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
894 /* @brief Has pull resistor enable (register bit PCR[PE]). */
895 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
896 /* @brief Has slew rate control (register bit PCR[SRE]). */
897 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
898 /* @brief Has passive filter (register bit field PCR[PFE]). */
899 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
900 /* @brief Has drive strength control (register bit PCR[DSE]). */
901 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
902 /* @brief Defines width of PCR[MUX] field. */
903 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
904 /* @brief Has dedicated interrupt vector. */
905 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
906 /* @brief Has independent interrupt control(register ICR). */
907 #define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0)
908 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
909 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (1)
910 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */
911 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (1)
912 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
913 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (1)
914 
915 /* RADIO module features */
916 
917 /* @brief Zigbee availability. */
918 #define FSL_FEATURE_RADIO_HAS_ZIGBEE (1)
919 /* @brief Bluetooth availability. */
920 #define FSL_FEATURE_RADIO_HAS_BLE (1)
921 /* @brief ANT availability */
922 #define FSL_FEATURE_RADIO_HAS_ANT (0)
923 /* @brief Generic FSK module availability */
924 #define FSL_FEATURE_RADIO_HAS_GENFSK (1)
925 /* @brief Major version of the radio submodule */
926 #define FSL_FEATURE_RADIO_VERSION_MAJOR (3)
927 /* @brief Minor version of the radio submodule */
928 #define FSL_FEATURE_RADIO_VERSION_MINOR (0)
929 
930 /* RTC module features */
931 
932 /* @brief Has wakeup pin. */
933 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
934 /* @brief Has wakeup pin selection (bit field CR[WPS]). */
935 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
936 /* @brief Has low power features (registers MER, MCLR and MCHR). */
937 #define FSL_FEATURE_RTC_HAS_MONOTONIC (1)
938 /* @brief Has read/write access control (registers WAR and RAR). */
939 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
940 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
941 #define FSL_FEATURE_RTC_HAS_SECURITY (1)
942 /* @brief Has RTC_CLKIN available. */
943 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
944 /* @brief Has prescaler adjust for LPO. */
945 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1)
946 /* @brief Has Clock Pin Enable field. */
947 #define FSL_FEATURE_RTC_HAS_CPE (1)
948 /* @brief Has Timer Seconds Interrupt Configuration field. */
949 #define FSL_FEATURE_RTC_HAS_TSIC (1)
950 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
951 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
952 /* @brief Has Tamper Interrupt Register (register TIR). */
953 #define FSL_FEATURE_RTC_HAS_TIR (1)
954 /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */
955 #define FSL_FEATURE_RTC_HAS_TIR_TPIE (1)
956 /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */
957 #define FSL_FEATURE_RTC_HAS_TIR_SIE (1)
958 /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */
959 #define FSL_FEATURE_RTC_HAS_TIR_LCIE (1)
960 /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */
961 #define FSL_FEATURE_RTC_HAS_SR_TIDF (1)
962 /* @brief Has Tamper Detect Register (register TDR). */
963 #define FSL_FEATURE_RTC_HAS_TDR (1)
964 /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */
965 #define FSL_FEATURE_RTC_HAS_TDR_TPF (1)
966 /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */
967 #define FSL_FEATURE_RTC_HAS_TDR_STF (1)
968 /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */
969 #define FSL_FEATURE_RTC_HAS_TDR_LCTF (1)
970 /* @brief Has Tamper Time Seconds Register (register TTSR). */
971 #define FSL_FEATURE_RTC_HAS_TTSR (1)
972 /* @brief Has Pin Configuration Register (register PCR). */
973 #define FSL_FEATURE_RTC_HAS_PCR (1)
974 /* @brief Has Oscillator Enable(bitfield CR[OSCE]). */
975 #define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0)
976 
977 /* SCG module features */
978 
979 /* @brief Has platform clock divider SCG_CSR[DIVPLAT]. */
980 #define FSL_FEATURE_SCG_HAS_DIVPLAT (0)
981 /* @brief Has bus clock divider SCG_CSR[DIVBUS]. */
982 #define FSL_FEATURE_SCG_HAS_DIVBUS (1)
983 /* @brief Has external clock divide ratio SCG_CSR[DIVEXT]. */
984 #define FSL_FEATURE_SCG_HAS_DIVEXT (1)
985 /* @brief Has OSC capacitor setting SOSCCFG[SC2P ~ SC16P]. */
986 #define FSL_FEATURE_SCG_HAS_OSC_SCXP (0)
987 /* @brief Has SOSCCSR[SOSCERCLKEN]. */
988 #define FSL_FEATURE_SCG_HAS_OSC_ERCLK (0)
989 /* @brief Has OSC freq range SOSCCFG[RANGE]. */
990 #define FSL_FEATURE_SCG_HAS_SOSC_RANGE (0)
991 /* @brief Has CLKOUT configure register SCG_CLKOUTCNFG. */
992 #define FSL_FEATURE_SCG_HAS_CLKOUTCNFG (1)
993 /* @brief Has SCG_SOSCDIV[SOSCDIV3]. */
994 #define FSL_FEATURE_SCG_HAS_SOSCDIV3 (1)
995 /* @brief Has SCG_SIRCDIV[SIRCDIV3]. */
996 #define FSL_FEATURE_SCG_HAS_SIRCDIV3 (1)
997 /* @brief Has SCG_SIRCCSR[LPOPO]. */
998 #define FSL_FEATURE_SCG_HAS_SIRC_LPOPO (0)
999 /* @brief Has SCG_FIRCDIV[FIRCDIV3]. */
1000 #define FSL_FEATURE_SCG_HAS_FIRCDIV3 (1)
1001 /* @brief Has SCG_FIRCCSR[FIRCLPEN]. */
1002 #define FSL_FEATURE_SCG_HAS_FIRCLPEN (1)
1003 /* @brief Has SCG_FIRCCSR[FIRCREGOFF]. */
1004 #define FSL_FEATURE_SCG_HAS_FIRCREGOFF (1)
1005 /* @brief Has SCG_SPLLDIV[SPLLDIV3]. */
1006 #define FSL_FEATURE_SCG_HAS_SPLLDIV3 (0)
1007 /* @brief Has SCG_SPLLCFG[PLLPOSTDIV1]. */
1008 #define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV1 (0)
1009 /* @brief Has SCG_SPLLCFG[PLLPOSTDIV2]. */
1010 #define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV2 (0)
1011 /* @brief Has SCG_SPLLCFG[PLLS]. */
1012 #define FSL_FEATURE_SCG_HAS_SPLL_PLLS (0)
1013 /* @brief Has SCG_SPLLCFG[BYPASS]. */
1014 #define FSL_FEATURE_SCG_HAS_SPLL_BYPASS (0)
1015 /* @brief Has SCG_SPLLCFG[PFDSEL]. */
1016 #define FSL_FEATURE_SCG_HAS_SPLL_PFDSEL (0)
1017 /* @brief Has SCG_SPLLCSR[SPLLCM]. */
1018 #define FSL_FEATURE_SCG_HAS_SPLL_MONITOR (0)
1019 /* @brief Has SCG_LPFLLDIV[FLLDIV3]. */
1020 #define FSL_FEATURE_SCG_HAS_FLLDIV3 (1)
1021 /* @brief Has low power FLL, SCG_LPFLLCSR. */
1022 #define FSL_FEATURE_SCG_HAS_LPFLL (1)
1023 /* @brief Has system PLL, SCG_SPLLCSR. */
1024 #define FSL_FEATURE_SCG_HAS_SPLL (0)
1025 /* @brief Has system PLL PFD, SCG_SPLLPFD. */
1026 #define FSL_FEATURE_SCG_HAS_SPLLPFD (0)
1027 /* @brief Has auxiliary PLL, SCG_APLLCSR. */
1028 #define FSL_FEATURE_SCG_HAS_APLL (0)
1029 /* @brief Has RTC OSC control, SCG_ROSCCSR. */
1030 #define FSL_FEATURE_SCG_HAS_ROSC (1)
1031 /* @brief Has RTC OSC clock source. */
1032 #define FSL_FEATURE_SCG_HAS_ROSC_SYS_CLK_SRC (1)
1033 /* @brief Has RTC OSC clock out select. */
1034 #define FSL_FEATURE_SCG_HAS_ROSC_CLKOUT (1)
1035 /* @brief Has EXTERNAL clock out select. */
1036 #define FSL_FEATURE_SCG_HAS_EXT_CLKOUT (1)
1037 /* @brief Has no System OSC configuration register, SCG_SOSCCFG. */
1038 #define FSL_FEATURE_SCG_HAS_NO_SOSCCFG (1)
1039 /* @brief Has no SCG_SOSCCSR[SOSCEN]. */
1040 #define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCEN (0)
1041 /* @brief Has no SCG_SOSCCSR[SOSCSTEN]. */
1042 #define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCSTEN (0)
1043 /* @brief Has no SCG_SOSCCSR[SOSCLPEN]. */
1044 #define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCLPEN (0)
1045 /* @brief Has no FIRC trim configuration register, SCG_FIRCTCFG. */
1046 #define FSL_FEATURE_SCG_HAS_NO_FIRCTCFG (0)
1047 /* @brief Has FIRC trim source USB0 Start of Frame. */
1048 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB0 (0)
1049 /* @brief Has FIRC trim source USB1 Start of Frame. */
1050 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB1 (0)
1051 /* @brief Has FIRC trim source system OSC. */
1052 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_SOSC (1)
1053 /* @brief Has FIRC trim source RTC OSC. */
1054 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_RTCOSC (1)
1055 
1056 /* SEMA42 module features */
1057 
1058 /* @brief Gate counts */
1059 #define FSL_FEATURE_SEMA42_GATE_COUNT (16)
1060 
1061 /* SIM module features */
1062 
1063 /* @brief Has USB FS divider. */
1064 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
1065 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
1066 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
1067 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
1068 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
1069 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
1070 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
1071 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
1072 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (0)
1073 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
1074 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (0)
1075 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
1076 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0)
1077 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
1078 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
1079 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
1080 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
1081 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
1082 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
1083 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
1084 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
1085 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
1086 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
1087 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
1088 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
1089 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
1090 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
1091 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
1092 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
1093 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
1094 #define FSL_FEATURE_SIM_OPT_UART_COUNT (0)
1095 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
1096 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
1097 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
1098 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
1099 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
1100 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
1101 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
1102 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
1103 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
1104 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
1105 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
1106 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
1107 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
1108 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
1109 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
1110 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
1111 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
1112 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
1113 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
1114 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
1115 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
1116 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0)
1117 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
1118 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0)
1119 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
1120 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0)
1121 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
1122 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0)
1123 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
1124 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0)
1125 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
1126 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0)
1127 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
1128 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0)
1129 /* @brief Has FTM module(s) configuration. */
1130 #define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
1131 /* @brief Number of FTM modules. */
1132 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
1133 /* @brief Number of FTM triggers with selectable source. */
1134 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
1135 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
1136 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
1137 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
1138 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
1139 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
1140 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
1141 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
1142 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
1143 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
1144 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
1145 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
1146 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
1147 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
1148 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
1149 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
1150 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
1151 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
1152 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
1153 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
1154 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
1155 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
1156 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
1157 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
1158 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
1159 /* @brief Has TPM module(s) configuration. */
1160 #define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
1161 /* @brief The highest TPM module index. */
1162 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
1163 /* @brief Has TPM module with index 0. */
1164 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
1165 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
1166 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
1167 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
1168 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
1169 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1170 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
1171 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
1172 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
1173 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1174 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
1175 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
1176 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
1177 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
1178 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
1179 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
1180 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0)
1181 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
1182 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0)
1183 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
1184 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
1185 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
1186 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
1187 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
1188 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
1189 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
1190 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
1191 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
1192 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
1193 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
1194 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
1195 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
1196 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
1197 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
1198 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
1199 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
1200 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
1201 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
1202 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
1203 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
1204 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
1205 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
1206 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
1207 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
1208 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
1209 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
1210 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
1211 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
1212 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
1213 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
1214 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
1215 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
1216 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (0)
1217 /* @brief ADC module has alternate trigger (register bit SOPT7[ADC0ALTTRGEN]). */
1218 #define FSL_FEATURE_SIM_OPT_ADC_HAS_ALTERNATE_TRIGGER (0)
1219 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
1220 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (0)
1221 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
1222 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0)
1223 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
1224 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
1225 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
1226 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
1227 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
1228 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
1229 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
1230 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
1231 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
1232 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
1233 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
1234 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
1235 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
1236 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
1237 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
1238 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
1239 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
1240 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
1241 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
1242 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
1243 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
1244 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (0)
1245 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
1246 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (0)
1247 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
1248 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
1249 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
1250 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
1251 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
1252 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
1253 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
1254 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
1255 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
1256 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
1257 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
1258 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
1259 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
1260 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
1261 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
1262 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
1263 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
1264 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
1265 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
1266 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
1267 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
1268 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
1269 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
1270 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
1271 /* @brief Has device die ID (register bit field SDID[DIEID]). */
1272 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
1273 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
1274 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
1275 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
1276 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
1277 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
1278 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
1279 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
1280 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
1281 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
1282 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
1283 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
1284 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
1285 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
1286 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
1287 /* @brief Has flash for core0(CM4) (register bit field FCFG1[CORE0_PFSIZE]). */
1288 #define FSL_FEATURE_SIM_FCFG_HAS_CORE0_PFSIZE (1)
1289 /* @brief Has flash for core1(CM0) (register bit field FCFG1[CORE1_PFSIZE]). */
1290 #define FSL_FEATURE_SIM_FCFG_HAS_CORE1_PFSIZE (1)
1291 /* @brief Has sram for core0(CM4) (register bit field FCFG1[CORE0_SRAMSIZE]). */
1292 #define FSL_FEATURE_SIM_FCFG_HAS_CORE0_SRAMSIZE (1)
1293 /* @brief Has sram for core1(CM0) (register bit field FCFG1[CORE1_SRAMSIZE]). */
1294 #define FSL_FEATURE_SIM_FCFG_HAS_CORE1_SRAMSIZE (1)
1295 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
1296 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (0)
1297 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
1298 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0)
1299 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
1300 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (1)
1301 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
1302 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
1303 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
1304 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
1305 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
1306 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
1307 /* @brief Has miscellanious control register (register MCR). */
1308 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
1309 /* @brief Has COP watchdog (registers COPC and SRVCOP). */
1310 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
1311 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
1312 #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
1313 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
1314 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
1315 /* @brief Has MISCCTRL reg. */
1316 #define FSL_FEATURE_SIM_HAS_MISCCTRL (0)
1317 /* @brief Has LTCEN bit (e.g SIM_MISCCTRL). */
1318 #define FSL_FEATURE_SIM_HAS_MISCCTRL_LTCEN (0)
1319 /* @brief Has DMAINTSEL0 bit (e.g SIM_MISCCTRL). */
1320 #define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL0 (0)
1321 /* @brief Has DMAINTSEL1 bit (e.g SIM_MISCCTRL). */
1322 #define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL1 (0)
1323 /* @brief Has DMAINTSEL2 bit (e.g SIM_MISCCTRL). */
1324 #define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL2 (0)
1325 /* @brief Has DMAINTSEL3 bit (e.g SIM_MISCCTRL). */
1326 #define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL3 (0)
1327 /* @brief Has SECKEY0 reg. */
1328 #define FSL_FEATURE_SIM_HAS_SECKEY0 (0)
1329 /* @brief Has SECKEY bit (e.g SIM_SECKEY0). */
1330 #define FSL_FEATURE_SIM_HAS_SECKEY0_SECKEY (0)
1331 /* @brief Has SECKEY1 reg. */
1332 #define FSL_FEATURE_SIM_HAS_SECKEY1 (0)
1333 /* @brief Has SECKEY bit (e.g SIM_SECKEY1). */
1334 #define FSL_FEATURE_SIM_HAS_SECKEY1_SECKEY (0)
1335 /* @brief Has SECKEY2 reg. */
1336 #define FSL_FEATURE_SIM_HAS_SECKEY2 (0)
1337 /* @brief Has SECKEY bit (e.g SIM_SECKEY2). */
1338 #define FSL_FEATURE_SIM_HAS_SECKEY2_SECKEY (0)
1339 /* @brief Has SECKEY3 reg. */
1340 #define FSL_FEATURE_SIM_HAS_SECKEY3 (0)
1341 /* @brief Has SECKEY bit (e.g SIM_SECKEY3). */
1342 #define FSL_FEATURE_SIM_HAS_SECKEY3_SECKEY (0)
1343 /* @brief Has no SDID reg. */
1344 #define FSL_FEATURE_SIM_HAS_NO_SDID (0)
1345 /* @brief Has no UID reg. */
1346 #define FSL_FEATURE_SIM_HAS_NO_UID (0)
1347 /* @brief Has RFADDRL and RFADDRH registers. */
1348 #define FSL_FEATURE_SIM_HAS_RF_MAC_ADDR (1)
1349 /* @brief Has SYSTICK_CLK_EN bit in SIM_MISC2 register. */
1350 #define FSL_FEATURE_SIM_MISC2_HAS_SYSTICK_CLK_EN (1)
1351 /* @brief Has UIDM registers. */
1352 #define FSL_FEATURE_SIM_HAS_UIDM (1)
1353 
1354 /* SMC module features */
1355 
1356 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
1357 #define FSL_FEATURE_SMC_HAS_PSTOPO (0)
1358 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
1359 #define FSL_FEATURE_SMC_HAS_LPOPO (0)
1360 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
1361 #define FSL_FEATURE_SMC_HAS_PORPO (0)
1362 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
1363 #define FSL_FEATURE_SMC_HAS_LPWUI (0)
1364 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
1365 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
1366 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
1367 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
1368 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
1369 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
1370 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
1371 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
1372 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
1373 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1)
1374 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
1375 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
1376 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
1377 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
1378 /* @brief Has stop submode. */
1379 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
1380 /* @brief Has stop submode 0(VLLS0). */
1381 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
1382 /* @brief Has stop submode 2(VLLS2). */
1383 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
1384 /* @brief Has SMC_PARAM. */
1385 #define FSL_FEATURE_SMC_HAS_PARAM (1)
1386 /* @brief Has SMC_VERID. */
1387 #define FSL_FEATURE_SMC_HAS_VERID (1)
1388 /* @brief Has SMC_CSRE. */
1389 #define FSL_FEATURE_SMC_HAS_CSRE (0)
1390 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
1391 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (0)
1392 /* @brief Has tamper reset (register bit SRS[TAMPER]). */
1393 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
1394 /* @brief Has security violation reset (register bit SRS[SECVIO]). */
1395 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
1396 /* @brief Has security violation reset (register bit SRS[VBAT]). */
1397 #define FSL_FEATURE_SMC_HAS_SRS_VBAT (0)
1398 /* @brief Has security violation reset (register bit SRS[CORE0]). */
1399 #define FSL_FEATURE_SMC_HAS_SRS_CORE0 (1)
1400 /* @brief Has security violation reset (register bit SRS[CORE1]). */
1401 #define FSL_FEATURE_SMC_HAS_SRS_CORE1 (1)
1402 /* @brief Has security violation reset (register bit SRIE[VBAT]). */
1403 #define FSL_FEATURE_SMC_HAS_SRIE_VBAT (0)
1404 /* @brief Has security violation reset (register bit SRIE[CORE0]). */
1405 #define FSL_FEATURE_SMC_HAS_SRIE_CORE0 (1)
1406 /* @brief Has security violation reset (register bit SRIE[CORE1]). */
1407 #define FSL_FEATURE_SMC_HAS_SRIE_CORE1 (1)
1408 
1409 /* SysTick module features */
1410 
1411 /* @brief Systick has external reference clock. */
1412 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1)
1413 /* @brief Systick external reference clock is core clock divided by this value. */
1414 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16)
1415 
1416 /* TPM module features */
1417 
1418 /* @brief Number of channels. */
1419 #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \
1420     ((x) == TPM0 ? (6) : \
1421     ((x) == TPM1 ? (2) : \
1422     ((x) == TPM2 ? (6) : \
1423     ((x) == TPM3 ? (2) : (-1)))))
1424 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
1425 #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
1426 /* @brief Has TPM_PARAM. */
1427 #define FSL_FEATURE_TPM_HAS_PARAM (1)
1428 /* @brief Has TPM_VERID. */
1429 #define FSL_FEATURE_TPM_HAS_VERID (1)
1430 /* @brief Has TPM_GLOBAL. */
1431 #define FSL_FEATURE_TPM_HAS_GLOBAL (1)
1432 /* @brief Has TPM_TRIG. */
1433 #define FSL_FEATURE_TPM_HAS_TRIG (1)
1434 /* @brief Has counter pause on trigger. */
1435 #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
1436 /* @brief Has external trigger selection. */
1437 #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
1438 /* @brief Has TPM_COMBINE register. */
1439 #define FSL_FEATURE_TPM_HAS_COMBINE (1)
1440 /* @brief Whether COMBINE register has effect. */
1441 #define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1)
1442 /* @brief Has TPM_POL. */
1443 #define FSL_FEATURE_TPM_HAS_POL (1)
1444 /* @brief Has TPM_FILTER register. */
1445 #define FSL_FEATURE_TPM_HAS_FILTER (1)
1446 /* @brief Whether FILTER register has effect. */
1447 #define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1)
1448 /* @brief Has TPM_QDCTRL register. */
1449 #define FSL_FEATURE_TPM_HAS_QDCTRL (1)
1450 /* @brief Whether QDCTRL register has effect. */
1451 #define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1)
1452 
1453 /* TRGMUX module features */
1454 
1455 /* No feature definitions */
1456 
1457 /* TRNG module features */
1458 
1459 /* No feature definitions */
1460 
1461 /* TSTMR module features */
1462 
1463 /* @brief TSTMR clock frequency is 1MHZ. */
1464 #define FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_1MHZ (1)
1465 
1466 /* USB module features */
1467 
1468 /* @brief KHCI module instance count */
1469 #define FSL_FEATURE_USB_KHCI_COUNT (1)
1470 /* @brief HOST mode enabled */
1471 #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (0)
1472 /* @brief OTG mode enabled */
1473 #define FSL_FEATURE_USB_KHCI_OTG_ENABLED (0)
1474 /* @brief Size of the USB dedicated RAM */
1475 #define FSL_FEATURE_USB_KHCI_USB_RAM (2048)
1476 /* @brief Base address of the USB dedicated RAM */
1477 #define FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS (1208025088)
1478 /* @brief Has KEEP_ALIVE_CTRL register */
1479 #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (1)
1480 /* @brief Mode control of the USB Keep Alive */
1481 #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_MODE_CONTROL (USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK)
1482 /* @brief Has the Dynamic SOF threshold compare support */
1483 #define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1)
1484 /* @brief Has the VBUS detect support */
1485 #define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (1)
1486 /* @brief Has the IRC48M module clock support */
1487 #define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
1488 /* @brief Number of endpoints supported */
1489 #define FSL_FEATURE_USB_ENDPT_COUNT (16)
1490 /* @brief Has STALL_IL/OL_DIS registers */
1491 #define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1)
1492 /* @brief Has STALL_IH/OH_DIS registers */
1493 #define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1)
1494 
1495 /* USDHC module features */
1496 
1497 /* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */
1498 #define FSL_FEATURE_USDHC_HAS_EXT_DMA (0)
1499 /* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */
1500 #define FSL_FEATURE_USDHC_HAS_HS400_MODE (0)
1501 /* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */
1502 #define FSL_FEATURE_USDHC_HAS_SDR50_MODE (0)
1503 /* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */
1504 #define FSL_FEATURE_USDHC_HAS_SDR104_MODE (0)
1505 
1506 /* VREF module features */
1507 
1508 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */
1509 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
1510 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
1511 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
1512 /* @brief If high/low buffer mode supported */
1513 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
1514 /* @brief Module has also low reference (registers VREFL/VREFH) */
1515 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
1516 /* @brief Has VREF_TRM4. */
1517 #define FSL_FEATURE_VREF_HAS_TRM4 (1)
1518 
1519 /* WDOG module features */
1520 
1521 /* @brief Watchdog is available. */
1522 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
1523 /* @brief WDOG_CNT can be 32-bit written. */
1524 #define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1)
1525 
1526 /* XRDC module features */
1527 
1528 /* @brief Does not have global valid (register bit CR[GVLD]). */
1529 #define FSL_FEATURE_XRDC_HAS_NO_CR_GVLD (1)
1530 /* @brief Has domain ID of faulted access (register bit FDID[FDID]). */
1531 #define FSL_FEATURE_XRDC_HAS_FDID (1)
1532 /* @brief Has special 4-state model option (register bit PID[SP4SM]). */
1533 #define FSL_FEATURE_XRDC_PID_SP4SM (1)
1534 /* @brief Does not have logical partition identifier (register bit MDA_W[LPID]). */
1535 #define FSL_FEATURE_XRDC_NO_MDA_LPID (1)
1536 /* @brief Does not have logical partition enable option (register bit MDA_W[LPE]). */
1537 #define FSL_FEATURE_XRDC_NO_MDA_LPE (1)
1538 /* @brief Does not have peripheral semaphore enable option (register bit PDAC_W0[SE]). */
1539 #define FSL_FEATURE_XRDC_NO_PDAC_SE (1)
1540 /* @brief Does not have peripheral semaphore number (register bit PDAC_W0[SNUM]). */
1541 #define FSL_FEATURE_XRDC_NO_PDAC_SNUM (1)
1542 /* @brief Has peripheral excessive access lock owner (register bit PDAC_W0[EALO]). */
1543 #define FSL_FEATURE_XRDC_HAS_PDAC_EALO (1)
1544 /* @brief Has peripheral excessive access lock option (register bit PDAC_W1[EAL]). */
1545 #define FSL_FEATURE_XRDC_HAS_PDAC_EAL (1)
1546 /* @brief Has memory region end address (register bit MRGD_W1[ENDADDR]). */
1547 #define FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR (1)
1548 /* @brief Does not have memory region semaphore enable option (register bit MRGD_W2[SE]). */
1549 #define FSL_FEATURE_XRDC_NO_MRGD_SE (1)
1550 /* @brief Does not have memory region semaphore number (register bit MRGD_W2[SNUM]). */
1551 #define FSL_FEATURE_XRDC_NO_MRGD_SNUM (1)
1552 /* @brief Does not domain x access control policy option (register bit MRGD_W2[DxACP]). */
1553 #define FSL_FEATURE_XRDC_NO_MRGD_DXACP (1)
1554 /* @brief Does not have region size configuration (register bit MRGD_W2[SZ]). */
1555 #define FSL_FEATURE_XRDC_NO_MRGD_SZ (1)
1556 /* @brief Does not have subregion disable option (register bit MRGD_W2[SRD]). */
1557 #define FSL_FEATURE_XRDC_NO_MRGD_SRD (1)
1558 /* @brief Has memory region excessive access lock owner (register bit MRGD_W2[EALO]). */
1559 #define FSL_FEATURE_XRDC_HAS_MRGD_EALO (1)
1560 /* @brief Has domain x access policy select option (register bit MRGD_W2[DxSEL]). */
1561 #define FSL_FEATURE_XRDC_HAS_MRGD_DXSEL (1)
1562 /* @brief Has memory region excessive access lock option (register bit MRGD_W3[EAL]). */
1563 #define FSL_FEATURE_XRDC_HAS_MRGD_EAL (1)
1564 /* @brief Does not have lock option in MRGD_W3 register (register bit MRGD_W3[LK2]). */
1565 #define FSL_FEATURE_XRDC_NO_MRGD_W3_LK2 (1)
1566 /* @brief Does not have valid option in MRGD_W3 register (register bit MRGD_W3[VLD]). */
1567 #define FSL_FEATURE_XRDC_NO_MRGD_W3_VLD (1)
1568 /* @brief Has code region indicator select option (register bit MRGD_W3[CR]). */
1569 #define FSL_FEATURE_XRDC_HAS_MRGD_CR (1)
1570 /* @brief Has ASSSET lock option (register bit MRGD_W4[LKAS1]/[LKAS2]). */
1571 #define FSL_FEATURE_XRDC_HAS_MRGD_LKAS (1)
1572 /* @brief Has programmable access flags (register bit MRGD_W4[ACCSET1]/[ACCSET2]). */
1573 #define FSL_FEATURE_XRDC_HAS_MRGD_ACCSET (1)
1574 /* @brief Has lock option in MRGD_W4 register (register bit MRGD_W4[LK2]). */
1575 #define FSL_FEATURE_XRDC_HAS_MRGD_W4_LK2 (1)
1576 /* @brief Has valid option in MRGD_W4 register (register bit MRGD_W4[VLD]). */
1577 #define FSL_FEATURE_XRDC_HAS_MRGD_W4_VLD (1)
1578 /* @brief XRDC domain number (reset value of HWCFG0[NDID] plus 1). */
1579 #define FSL_FEATURE_XRDC_DOMAIN_COUNT (3)
1580 
1581 #endif /* _RV32M1_zero_riscy_FEATURES_H_ */
1582 
1583