1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2020 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _RTE_DEVICE_H 9 #define _RTE_DEVICE_H 10 11 #include "pin_mux.h" 12 13 /* UART Select. */ 14 /* Select UART0 - UART3. */ 15 /* User needs to provide the implementation of LPUARTX_GetFreq/LPUARTX_InitPins/LPUARTX_DeinitPins for the enabled 16 * LPUART instance. */ 17 #define RTE_USART0 0 18 #define RTE_USART0_DMA_EN 0 19 #define RTE_USART1 0 20 #define RTE_USART1_DMA_EN 0 21 #define RTE_USART2 0 22 #define RTE_USART2_DMA_EN 0 23 #define RTE_USART3 0 24 #define RTE_USART3_DMA_EN 0 25 /* Select LPUART0. */ 26 #define RTE_USART4 0 27 #define RTE_USART4_DMA_EN 0 28 29 /* UART configuration. */ 30 #define USART_RX_BUFFER_LEN 64 31 #define USART0_RX_BUFFER_ENABLE 0 32 #define USART1_RX_BUFFER_ENABLE 0 33 #define USART2_RX_BUFFER_ENABLE 0 34 #define USART3_RX_BUFFER_ENABLE 0 35 #define USART4_RX_BUFFER_ENABLE 0 36 37 #define RTE_USART0_PIN_INIT LPUART0_InitPins 38 #define RTE_USART0_PIN_DEINIT LPUART0_DeinitPins 39 #define RTE_USART0_DMA_TX_CH 0 40 #define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Tx 41 #define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX0 42 #define RTE_USART0_DMA_TX_DMA_BASE DMA0 43 #define RTE_USART0_DMA_RX_CH 1 44 #define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Rx 45 #define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX 46 #define RTE_USART0_DMA_RX_DMA_BASE DMA0 47 48 #define RTE_USART1_PIN_INIT LPUART1_InitPins 49 #define RTE_USART1_PIN_DEINIT LPUART1_DeinitPins 50 #define RTE_USART1_DMA_TX_CH 0 51 #define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Tx 52 #define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX 53 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 54 #define RTE_USART1_DMA_RX_CH 1 55 #define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Rx 56 #define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX 57 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 58 59 #define RTE_USART2_PIN_INIT LPUART2_InitPins 60 #define RTE_USART2_PIN_DEINIT LPUART2_DeinitPins 61 #define RTE_USART2_DMA_TX_CH 0 62 #define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Tx 63 #define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX 64 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 65 #define RTE_USART2_DMA_RX_CH 1 66 #define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Rx 67 #define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX 68 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 69 70 #define RTE_USART3_PIN_INIT LPUART3_InitPins 71 #define RTE_USART3_PIN_DEINIT LPUART3_DeinitPins 72 #define RTE_USART3_DMA_TX_CH 0 73 #define RTE_USART3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART3Tx 74 #define RTE_USART3_DMA_TX_DMAMUX_BASE DMAMUX 75 #define RTE_USART3_DMA_TX_DMA_BASE DMA0 76 #define RTE_USART3_DMA_RX_CH 1 77 #define RTE_USART3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART3Rx 78 #define RTE_USART3_DMA_RX_DMAMUX_BASE DMAMUX 79 #define RTE_USART3_DMA_RX_DMA_BASE DMA0 80 81 #define RTE_USART4_PIN_INIT LPUART4_InitPins 82 #define RTE_USART4_PIN_DEINIT LPUART4_DeinitPins 83 #define RTE_USART4_DMA_TX_CH 0 84 #define RTE_USART4_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Tx 85 #define RTE_USART4_DMA_TX_DMAMUX_BASE DMAMUX 86 #define RTE_USART4_DMA_TX_DMA_BASE DMA0 87 #define RTE_USART4_DMA_RX_CH 1 88 #define RTE_USART4_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Rx 89 #define RTE_USART4_DMA_RX_DMAMUX_BASE DMAMUX 90 #define RTE_USART4_DMA_RX_DMA_BASE DMA0 91 92 /* I2C Select, I2C0 - I2C1 */ 93 /* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance. 94 */ 95 #define RTE_I2C0 0 96 #define RTE_I2C0_DMA_EN 0 97 #define RTE_I2C1 0 98 #define RTE_I2C1_DMA_EN 0 99 100 /*I2C configuration*/ 101 #define RTE_I2C0_Master_DMA_BASE DMA0 102 #define RTE_I2C0_Master_DMA_CH 0 103 #define RTE_I2C0_Master_DMAMUX_BASE DMAMUX 104 #define RTE_I2C0_Master_PERI_SEL kDmaRequestMux0I2C0 105 106 #define RTE_I2C1_Master_DMA_BASE DMA0 107 #define RTE_I2C1_Master_DMA_CH 0 108 #define RTE_I2C1_Master_DMAMUX_BASE DMAMUX 109 #define RTE_I2C1_Master_PERI_SEL kDmaRequestMux0I2C1 110 111 /* SPI select, SPI0 - SPI2.*/ 112 /* User needs to provide the implementation of SPIX_GetFreq/SPIX_InitPins/SPIX_DeinitPins for the enabled SPI instance. 113 */ 114 #define RTE_SPI0 0 115 #define RTE_SPI0_DMA_EN 0 116 #define RTE_SPI1 0 117 #define RTE_SPI1_DMA_EN 0 118 #define RTE_SPI2 0 119 #define RTE_SPI2_DMA_EN 0 120 121 /* SPI configuration. */ 122 #define RTE_SPI0_PIN_INIT SPI0_InitPins 123 #define RTE_SPI0_PIN_DEINIT SPI0_DeinitPins 124 #define RTE_SPI0_DMA_TX_CH 3 125 #define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Tx 126 #define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX 127 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0 128 #define RTE_SPI0_DMA_RX_CH 2 129 #define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Rx 130 #define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX 131 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0 132 133 #define RTE_SPI1_PIN_INIT SPI1_InitPins 134 #define RTE_SPI1_PIN_DEINIT SPI1_DeinitPins 135 #define RTE_SPI1_DMA_TX_CH 2 136 #define RTE_SPI1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1Tx 137 #define RTE_SPI1_DMA_TX_DMAMUX_BASE DMAMUX 138 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0 139 #define RTE_SPI1_DMA_RX_CH 3 140 #define RTE_SPI1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1Rx 141 #define RTE_SPI1_DMA_RX_DMAMUX_BASE DMAMUX 142 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0 143 144 #define RTE_SPI2_PIN_INIT SPI2_InitPins 145 #define RTE_SPI2_PIN_DEINIT SPI2_DeinitPins 146 #define RTE_SPI2_DMA_TX_CH 2 147 #define RTE_SPI2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI2Tx 148 #define RTE_SPI2_DMA_TX_DMAMUX_BASE DMAMUX 149 #define RTE_SPI2_DMA_TX_DMA_BASE DMA0 150 #define RTE_SPI2_DMA_RX_CH 3 151 #define RTE_SPI2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI2Rx 152 #define RTE_SPI2_DMA_RX_DMAMUX_BASE DMAMUX 153 #define RTE_SPI2_DMA_RX_DMA_BASE DMA0 154 #endif /* _RTE_DEVICE_H */ 155
