1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2020 NXP 4 * All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef _RTE_DEVICE_H 10 #define _RTE_DEVICE_H 11 12 #include "pin_mux.h" 13 14 /* UART Select, LPUART0 - LPUART2. */ 15 /* User needs to provide the implementation of LPUARTX_GetFreq/LPUARTX_InitPins/LPUARTX_DeinitPins for the enabled 16 * LPUART instance. */ 17 #define RTE_USART0 0 18 #define RTE_USART0_DMA_EN 0 19 #define RTE_USART1 0 20 #define RTE_USART1_DMA_EN 0 21 #define RTE_USART2 0 22 #define RTE_USART2_DMA_EN 0 23 24 /* UART configuration. */ 25 #define USART_RX_BUFFER_LEN 64 26 #define USART0_RX_BUFFER_ENABLE 0 27 #define USART1_RX_BUFFER_ENABLE 0 28 #define USART2_RX_BUFFER_ENABLE 0 29 30 #define RTE_USART0_PIN_INIT LPUART0_InitPins 31 #define RTE_USART0_PIN_DEINIT LPUART0_DeinitPins 32 #define RTE_USART0_DMA_TX_CH 0 33 #define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Tx 34 #define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX 35 #define RTE_USART0_DMA_TX_DMA_BASE DMA0 36 #define RTE_USART0_DMA_RX_CH 1 37 #define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Rx 38 #define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX 39 #define RTE_USART0_DMA_RX_DMA_BASE DMA0 40 41 #define RTE_USART1_PIN_INIT LPUART1_InitPins 42 #define RTE_USART1_PIN_DEINIT LPUART1_DeinitPins 43 #define RTE_USART1_DMA_TX_CH 0 44 #define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART1Tx 45 #define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX 46 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 47 #define RTE_USART1_DMA_RX_CH 1 48 #define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART1Rx 49 #define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX 50 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 51 52 #define RTE_USART2_PIN_INIT LPUART2_InitPins 53 #define RTE_USART2_PIN_DEINIT LPUART2_DeinitPins 54 #define RTE_USART2_DMA_TX_CH 0 55 #define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART2Tx 56 #define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX 57 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 58 #define RTE_USART2_DMA_RX_CH 1 59 #define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART2Rx 60 #define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX 61 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 62 63 /* I2C Select, LPI2C0 - LPI2C1. */ 64 /* User needs to provide the implementation of LPI2CX_GetFreq/LPI2CX_InitPins/LPI2CX_DeinitPins for the enabled LPI2C 65 * instance. */ 66 #define RTE_I2C0 0 67 #define RTE_I2C0_DMA_EN 0 68 #define RTE_I2C1 0 69 #define RTE_I2C1_DMA_EN 0 70 71 /* LPI2C configuration. */ 72 #define RTE_I2C0_PIN_INIT LPI2C0_InitPins 73 #define RTE_I2C0_PIN_DEINIT LPI2C0_DeinitPins 74 #define RTE_I2C0_DMA_TX_CH 0 75 #define RTE_I2C0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPI2C0Tx 76 #define RTE_I2C0_DMA_TX_DMAMUX_BASE DMAMUX 77 #define RTE_I2C0_DMA_TX_DMA_BASE DMA0 78 #define RTE_I2C0_DMA_RX_CH 1 79 #define RTE_I2C0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPI2C0Rx 80 #define RTE_I2C0_DMA_RX_DMAMUX_BASE DMAMUX 81 #define RTE_I2C0_DMA_RX_DMA_BASE DMA0 82 83 #define RTE_I2C1_PIN_INIT LPI2C1_InitPins 84 #define RTE_I2C1_PIN_DEINIT LPI2C1_DeinitPins 85 #define RTE_I2C1_DMA_TX_CH 0 86 #define RTE_I2C1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPI2C1Tx 87 #define RTE_I2C1_DMA_TX_DMAMUX_BASE DMAMUX 88 #define RTE_I2C1_DMA_TX_DMA_BASE DMA0 89 #define RTE_I2C1_DMA_RX_CH 1 90 #define RTE_I2C1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPI2C1Rx 91 #define RTE_I2C1_DMA_RX_DMAMUX_BASE DMAMUX 92 #define RTE_I2C1_DMA_RX_DMA_BASE DMA0 93 94 /* SPI Select, DSPI0 - DSPI1. */ 95 /* User needs to provide the implementation of LPSPIX_GetFreq/LPSPIX_InitPins/LPSPIX_DeinitPins for the enabled LPSPI 96 * instance. */ 97 #define RTE_SPI0 0 98 #define RTE_SPI0_DMA_EN 0 99 #define RTE_SPI1 0 100 #define RTE_SPI1_DMA_EN 0 101 102 /* SPI configuration. */ 103 #define RTE_SPI0_PCS_TO_SCK_DELAY 1000 104 #define RTE_SPI0_SCK_TO_PSC_DELAY 1000 105 #define RTE_SPI0_BETWEEN_TRANSFER_DELAY 1000 106 #define RTE_SPI0_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs3) 107 #define RTE_SPI0_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs3) 108 #define RTE_SPI0_PIN_INIT LPSPI0_InitPins 109 #define RTE_SPI0_PIN_DEINIT LPSPI0_DeinitPins 110 #define RTE_SPI0_DMA_TX_CH 0 111 #define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPSPI0Tx 112 #define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX 113 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0 114 #define RTE_SPI0_DMA_RX_CH 1 115 #define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPSPI0Rx 116 #define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX 117 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0 118 119 #define RTE_SPI1_PCS_TO_SCK_DELAY 1000 120 #define RTE_SPI1_SCK_TO_PSC_DELAY 1000 121 #define RTE_SPI1_BETWEEN_TRANSFER_DELAY 1000 122 #define RTE_SPI1_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs3) 123 #define RTE_SPI1_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs3) 124 #define RTE_SPI1_PIN_INIT LPSPI1_InitPins 125 #define RTE_SPI1_PIN_DEINIT LPSPI1_DeinitPins 126 #define RTE_SPI1_DMA_TX_CH 0 127 #define RTE_SPI1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPSPI1Tx 128 #define RTE_SPI1_DMA_TX_DMAMUX_BASE DMAMUX 129 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0 130 #define RTE_SPI1_DMA_RX_CH 1 131 #define RTE_SPI1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPSPI1Rx 132 #define RTE_SPI1_DMA_RX_DMAMUX_BASE DMAMUX 133 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0 134 135 #endif /* _RTE_DEVICE_H */ 136
