1 /*! ********************************************************************************* 2 * Copyright 2022-2024 NXP 3 * All rights reserved. 4 * 5 * \file 6 * 7 * SPDX-License-Identifier: BSD-3-Clause 8 ********************************************************************************** */ 9 10 #ifndef __PHY_TIME_H__ 11 #define __PHY_TIME_H__ 12 13 #define BM_ZLL_IRQSTS_TMRxMSK (ZLL_IRQSTS_TMR1MSK_MASK | \ 14 ZLL_IRQSTS_TMR2MSK_MASK | \ 15 ZLL_IRQSTS_TMR3MSK_MASK | \ 16 ZLL_IRQSTS_TMR4MSK_MASK ) 17 18 #define TMR_REG_EN_1 (ZLL_PHY_CTRL_TMR1CMP_EN_MASK) 19 #define TMR_REG_EN_2 (ZLL_PHY_CTRL_TMR2CMP_EN_MASK | ZLL_PHY_CTRL_TMRTRIGEN_MASK) 20 #define TMR_REG_EN_3 (ZLL_PHY_CTRL_TMR3CMP_EN_MASK | ZLL_PHY_CTRL_TC3TMOUT_MASK) 21 #define TMR_REG_EN_4 (ZLL_PHY_CTRL_TMR4CMP_EN_MASK) 22 23 #define TMR_REG_SET_1 (ZLL->T1CMP) 24 #define TMR_REG_SET_2 (ZLL->T2CMP) 25 #define TMR_REG_SET_3 (ZLL->T3CMP) 26 #define TMR_REG_SET_4 (ZLL->T4CMP) 27 28 #define TMR_REG_EN(__tmr__) TMR_REG_EN_ ## __tmr__ 29 #define TMR_REG_SET(__tmr__) TMR_REG_SET_ ## __tmr__ 30 #define TMR_REG_MSK(__tmr__) ZLL_IRQSTS_TMR ## __tmr__ ## MSK_MASK 31 #define TMR_REG_IRQ(__tmr__) ZLL_IRQSTS_TMR ## __tmr__ ## IRQ_MASK 32 33 #define ENABLE_TMR(__tmr__) ZLL->PHY_CTRL |= (TMR_REG_EN(__tmr__)) 34 #define DISABLE_TMR(__tmr__) ZLL->PHY_CTRL &= ~(TMR_REG_EN(__tmr__)) 35 #define SET_TMR(__tmr__, __time__) TMR_REG_SET(__tmr__) = __time__ 36 37 #define CLEAR_TMR_IRQ(__tmr__) do { \ 38 uint32_t irq_sts; \ 39 \ 40 irq_sts = ZLL->IRQSTS & BM_ZLL_IRQSTS_TMRxMSK; \ 41 irq_sts |= (TMR_REG_IRQ(__tmr__)); \ 42 ZLL->IRQSTS = irq_sts; \ 43 } while(0) 44 45 #define UNMASK_AND_CLEAR_TMR_IRQ(__tmr__) do { \ 46 uint32_t irq_sts; \ 47 \ 48 irq_sts = ZLL->IRQSTS & BM_ZLL_IRQSTS_TMRxMSK; \ 49 irq_sts &= ~(TMR_REG_MSK(__tmr__)); \ 50 irq_sts |= (TMR_REG_IRQ(__tmr__)); \ 51 ZLL->IRQSTS = irq_sts; \ 52 } while(0) 53 54 #define MASK_TMR_IRQ(__tmr__) do { \ 55 uint32_t irq_sts; \ 56 \ 57 irq_sts = ZLL->IRQSTS & BM_ZLL_IRQSTS_TMRxMSK; \ 58 irq_sts |= (TMR_REG_MSK(__tmr__) | TMR_REG_IRQ(__tmr__)); \ 59 ZLL->IRQSTS = irq_sts; \ 60 } while(0) 61 62 #define TMR_SET(__tmr__, __time__) do { \ 63 OSA_InterruptDisable(); \ 64 \ 65 DISABLE_TMR(__tmr__); \ 66 SET_TMR(__tmr__, __time__); \ 67 CLEAR_TMR_IRQ(__tmr__); \ 68 ENABLE_TMR(__tmr__); \ 69 \ 70 OSA_InterruptEnable(); \ 71 } while(0) 72 73 #define TMR_UNMASK_AND_SET(__tmr__, __time__) do { \ 74 OSA_InterruptDisable(); \ 75 \ 76 DISABLE_TMR(__tmr__); \ 77 SET_TMR(__tmr__, __time__); \ 78 UNMASK_AND_CLEAR_TMR_IRQ(__tmr__); \ 79 ENABLE_TMR(__tmr__); \ 80 \ 81 OSA_InterruptEnable(); \ 82 } while(0) 83 84 #define TMR_CLEAR(__tmr__) do { \ 85 OSA_InterruptDisable(); \ 86 \ 87 DISABLE_TMR(__tmr__); \ 88 MASK_TMR_IRQ(__tmr__); \ 89 \ 90 OSA_InterruptEnable(); \ 91 } while(0) 92 93 #define PhyTimeDisableEventTrigger() TMR_CLEAR(2) 94 #define PhyTimeSetEventTrigger(__time__) TMR_UNMASK_AND_SET(2, __time__) 95 96 #define PhyTimeDisableEventTimeout() TMR_CLEAR(3) 97 #define PhyTimeSetEventTimeout(__time__) TMR_SET(3, __time__) 98 99 #define PhyTimeDisableWaitTimeout() TMR_CLEAR(1) 100 #define PhyTimeSetWaitTimeout(__time__) TMR_UNMASK_AND_SET(1, __time__) 101 102 #endif /* __PHY_TIME_H__ */ 103
