1 /*! ********************************************************************************* 2 * Copyright 2023-2024 NXP 3 * All rights reserved. 4 * 5 * \file Platform specific definitions. This file contains the default values for 6 * platform files. 7 * 8 * SPDX-License-Identifier: BSD-3-Clause 9 ********************************************************************************** */ 10 11 #ifndef __PHY_PLATFORM_H__ 12 #define __PHY_PLATFORM_H__ 13 14 /*! ********************************************************************************* 15 ************************************************************************************* 16 * Include 17 ************************************************************************************* 18 ********************************************************************************** */ 19 20 #ifdef PHY_PLATFORM_SPECIFIC_CONFIG_FILE 21 // Name of the file for defining platform specific macros and functions. 22 // For example "PhyPlatform_RW610n.h", "PhyPlatform_IW512.h", "PhyPlatform_K32W1.h" 23 #include PHY_PLATFORM_SPECIFIC_CONFIG_FILE 24 #endif 25 26 /*! ********************************************************************************* 27 ************************************************************************************* 28 * Public macros 29 ************************************************************************************* 30 ********************************************************************************** */ 31 32 #ifndef gPhyIrqPriority_c 33 #define gPhyIrqPriority_c (0x80) 34 #endif 35 36 // TODO Should be moved to platform file 37 #if defined(KW45B41Z83_NBU_SERIES) 38 #define gPhyIrqNo_d (ZIGBEE_INT_IRQn) 39 #elif defined(K32W1480_SERIES) || defined(MCXW716C_SERIES) || defined(MCXW716A_SERIES) 40 #define gPhyIrqNo_d (RF_802_15_4_IRQn) 41 #elif defined(MCXW72BD_cm33_core0_SERIES) 42 #define gPhyIrqNo_d ((IRQn_Type)53) 43 #elif defined(MCXW72BD_cm33_core1_SERIES) 44 #define gPhyIrqNo_d ((IRQn_Type)ZIGBEE_INT_IRQn) 45 #endif 46 47 /* 48 The channel number corresponds to the number of all the channels, between 11 to 26. 49 It is used in the PhyUpdateTxPowerLimit() function which updates the power limit of 50 all the channels in the case a Front-end module is mounted with a power amplifier on 51 the narrow band path. 52 */ 53 #define CHANNEL_NUMBER (16) 54 55 /* 56 * MIN_ENERGY_LEVEL, MAX_ENERGY_LEVEL are parameters used to scale 57 * energy level between values 0x00-0xFF 58 */ 59 #ifndef MIN_ENERGY_LEVEL 60 #define MIN_ENERGY_LEVEL (-80) 61 #endif 62 #ifndef MAX_ENERGY_LEVEL 63 #define MAX_ENERGY_LEVEL (-3) 64 #endif 65 66 #ifndef CONVERT_ENERGY_LEVEL 67 /* Convert energy level from dbm into a 0x00-0xFF value */ 68 #define CONVERT_ENERGY_LEVEL(energy) ((17 * energy) / 5 + 272) 69 #endif 70 71 /* if the external Front End module Power Amplifier is enable, the maximum power level is +20dBm */ 72 #define gPhyMaxTxPowerLevel_With_FEM_PA_enable_d (0x28) 73 74 /* The interval at which the Phy will poll for a new buffer */ 75 #ifndef gPhyRxRetryInterval_c 76 #define gPhyRxRetryInterval_c (60) /* [symbols] */ 77 #endif 78 79 #ifndef gPhyUseExternalCoexistence_d 80 #define gPhyUseExternalCoexistence_d (0) 81 #endif 82 83 /* LQI calculation RSSI compensation value - this value + RX min RSSI should equal 0*/ 84 #ifndef gPhyLqiOffsetCompValue_d 85 #define gPhyLqiOffsetCompValue_d (102) 86 #endif 87 88 /* Number of table entries for generic IE data that can be added to an Enhanced ACK */ 89 #ifndef gPhyIeDataTableSize 90 #define gPhyIeDataTableSize (2) 91 #endif 92 93 /* Size of HW SAM Table size, RADIO specific */ 94 #define gPhyHwSAMTableSize_d (128) 95 96 #ifndef gPhySAPSize_d 97 #define gPhySAPSize_d (gPhyHwSAMTableSize_d) 98 #endif 99 100 #ifndef gPhySAASize_d 101 #define gPhySAASize_d (gPhyHwSAMTableSize_d) 102 #endif 103 104 #ifdef gPhyUseHwSAMTable 105 /* Make sure that SAP Table size is properly configured when HW Table is used */ 106 #if (gPhySAPSize_d > gPhyHwSAMTableSize_d) 107 #error "Phy SAP size bigger than HW capabilities" 108 #endif 109 /* Make sure that SAA Table size is properly configured when HW Table is used */ 110 #if (gPhySAASize_d > gPhyHwSAMTableSize_d) 111 #error "Phy SAA size bigger than HW capabilities" 112 #endif 113 114 /* TODO: Implement HW SAA */ 115 #error "SAA HW Table is not implemented for to use HW SAM table" 116 #endif 117 118 /* For MAC split we can't know for now whether Dual PAN is enabled. 119 Use half of the queue size to avoid any problems */ 120 #define gPhyIndirectQueueSize_d (gPhySAPSize_d / 2) 121 122 #ifndef FFU_CNS_TX_PWR_TABLE_CALIBRATION 123 #define FFU_CNS_TX_PWR_TABLE_CALIBRATION 0 124 #endif 125 126 #if (FFU_CNS_TX_PWR_TABLE_CALIBRATION == 1) 127 /* The power table mapping for the 15.4 is below. The power should be specified as 128 absolute value in 1/2 dBm step. The 15.4 LL will send out this power to BCA for 129 arbitration with WiFi before sending to BRF. FW doesn't directly write the BRF registers 130 unless it is a test mode. 131 132 TX Power Range in dBm : -20dBm to +15 dBm 133 Step increase : 1/2 dB 134 ESMAC Tx Power Index : -40(0xD8) to +30(0x1E) [High precision change in 0.5 dB for validation] 135 */ 136 #ifndef gPhyDefaultTxPowerLevel_d 137 #define gPhyDefaultTxPowerLevel_d (0) 138 #endif 139 140 #ifndef gPhyMaxTxPowerLevel_d 141 #define gPhyMaxTxPowerLevel_d (0x1E) 142 #endif 143 144 #ifndef gPhyMinTxPowerLevel_d 145 #define gPhyMinTxPowerLevel_d (0xD8) 146 #endif 147 148 #ifndef gPhyMinTxPowerLevelInt8_d 149 #define gPhyMinTxPowerLevelInt8_d (-64) 150 #endif 151 152 #ifndef gPhyMaxTxPowerLevelInt8_d 153 #define gPhyMaxTxPowerLevelInt8_d (63) 154 #endif 155 156 #else /* FFU_CNS_TX_PWR_TABLE_CALIBRATION */ 157 #ifndef gPhyDefaultTxPowerLevel_d 158 #define gPhyDefaultTxPowerLevel_d (22) 159 #endif 160 161 #ifndef gPhyMaxTxPowerLevel_d 162 #define gPhyMaxTxPowerLevel_d (32) 163 #endif 164 #endif /* FFU_CNS_TX_PWR_TABLE_CALIBRATION */ 165 166 /* Tx Power level limit for each individual channel */ 167 #ifndef gChannelTxPowerLimit_c 168 #define gChannelTxPowerLimit_c { gPhyMaxTxPowerLevel_d, /* 11 */ \ 169 gPhyMaxTxPowerLevel_d, /* 12 */ \ 170 gPhyMaxTxPowerLevel_d, /* 13 */ \ 171 gPhyMaxTxPowerLevel_d, /* 14 */ \ 172 gPhyMaxTxPowerLevel_d, /* 15 */ \ 173 gPhyMaxTxPowerLevel_d, /* 16 */ \ 174 gPhyMaxTxPowerLevel_d, /* 17 */ \ 175 gPhyMaxTxPowerLevel_d, /* 18 */ \ 176 gPhyMaxTxPowerLevel_d, /* 19 */ \ 177 gPhyMaxTxPowerLevel_d, /* 20 */ \ 178 gPhyMaxTxPowerLevel_d, /* 21 */ \ 179 gPhyMaxTxPowerLevel_d, /* 22 */ \ 180 gPhyMaxTxPowerLevel_d, /* 23 */ \ 181 gPhyMaxTxPowerLevel_d, /* 24 */ \ 182 gPhyMaxTxPowerLevel_d, /* 25 */ \ 183 gPhyMaxTxPowerLevel_d } /* 26 */ 184 #endif 185 186 #ifndef mPhyOverhead_d 187 #define mPhyOverhead_d (10) /* [sym] */ 188 #endif 189 190 #ifndef LQI_REG_MAX_VAL 191 #define LQI_REG_MAX_VAL ((uint8_t)127) /* Maximum value of LQI from the register*/ 192 #endif 193 #ifndef LQI_MAX_VAL 194 #define LQI_MAX_VAL ((uint8_t)0xFF) /* Maximum value of LQI*/ 195 #endif 196 #ifndef CLIP_LQI_VAL 197 #define CLIP_LQI_VAL ((int16_t)-20) /* WSW-21635: Clip 15.4 LQI value to 0xFF for above -20dBm */ 198 #endif 199 200 #ifndef gPhyLeniency_c 201 /* LENIENCY rule 40- allow all possible combinations from iee 802.15.4 2015 table 7.2 */ 202 /* LENIENCY rule 41- allow reception of enh ack frame where PAN ID compression doesn't match 203 the sent frame -> Thread issue */ 204 #define gPhyLeniency_c (0x300) 205 #endif 206 207 /* Front End loss value used for TX power calculation */ 208 #ifndef FE_LOSS_VALUE 209 #define FE_LOSS_VALUE 0 210 #endif 211 212 /* External Front End module Power Amplifier gain enable */ 213 #ifndef FE_POWER_AMPLIFIER_ENABLE 214 #define FE_POWER_AMPLIFIER_ENABLE 0 215 #endif 216 217 /* External Front End module Power Amplifier gain (dB) */ 218 #ifndef FE_POWER_AMPLIFIER_GAIN 219 #define FE_POWER_AMPLIFIER_GAIN 0 220 #endif 221 222 /* External Front End module LNA (Low Noise Attenuator) enable */ 223 #ifndef FE_LNA_ENABLE 224 #define FE_LNA_ENABLE 0 225 #endif 226 227 /* External Front End module LNA (Low Noise Attenuator) gain (dB) */ 228 #ifndef FE_LNA_GAIN 229 #define FE_LNA_GAIN 0 230 #endif 231 232 233 /* 234 * When receiving a frame, the radio will send an acknowledge automatically (if not 235 * an enhanced ACK). This flag enables the deactivation of this feature. 236 */ 237 #ifndef AUTO_ACK_DISABLE_SUPPORT 238 #define AUTO_ACK_DISABLE_SUPPORT 0 239 #endif 240 241 /* Enables to configure and get current TX power limit in gPhyChannelTxPowerLimits */ 242 #ifndef TX_POWER_LIMIT_FEATURE 243 #define TX_POWER_LIMIT_FEATURE 0 244 #endif 245 246 247 /* Enables to use variable mode of CCA instead of a fixed one (gPhyCCAMode1_c) */ 248 #ifndef CCA_MODE_SELECT_SUPPORT 249 #define CCA_MODE_SELECT_SUPPORT 0 250 #endif 251 252 /* Calculate RSSI based on LQI value instead of returning last RSSI value */ 253 #ifndef LAST_RSSI_USING_LQI 254 #define LAST_RSSI_USING_LQI 1 255 #endif 256 257 /* Support of ARB GRANT DEASSERTION by the radio. */ 258 #ifndef ARB_GRANT_DEASSERTION_SUPPORT 259 #define ARB_GRANT_DEASSERTION_SUPPORT 0 260 #endif 261 262 /* 263 * Enable radio coex metrics measurements count for Arbitration Grant wait, 264 * delayed, immediate... 265 */ 266 #ifndef RADIO_COEX_METRICS_ENABLE 267 #define RADIO_COEX_METRICS_ENABLE 0 268 #endif 269 270 /* Use RSSI and SNR weight for LQI calculation in Phy_LqiConvert */ 271 #ifndef WEIGHT_IN_LQI_CALCULATION 272 #define WEIGHT_IN_LQI_CALCULATION 0 273 #endif 274 275 /* Support of the use of XCVR misc driver api in ASP.c */ 276 #ifndef XCVR_MISC_SUPPORT 277 #if defined (RW610N_BT_CM3_SERIES) 278 #define XCVR_MISC_SUPPORT 0 279 #elif !(RW610_FPGA) 280 #define XCVR_MISC_SUPPORT 0 281 #else 282 #define XCVR_MISC_SUPPORT 1 283 #endif 284 #endif 285 286 /* Add the Front-End loss (in dB) to the RSSI value */ 287 #ifndef RSSI_WITH_FELOSS 288 #define RSSI_WITH_FELOSS (0) 289 #endif 290 291 292 /* 293 * PhyHwInit flags to enable default initialisation 294 */ 295 /* Select Data Rate to legacy 802.15.4 */ 296 #ifndef HWINIT_CONFIGURE_LEGACY_DATA_RATE 297 #define HWINIT_CONFIGURE_LEGACY_DATA_RATE (0) 298 #endif 299 300 /* Set CCA Mode2 Threshold Values */ 301 #ifndef HWINIT_CONFIGURE_CCA2_THRESHOLD 302 #define HWINIT_CONFIGURE_CCA2_THRESHOLD (0) 303 #endif 304 305 /* Use the CCA1 information computed by the RX Digital */ 306 #ifndef HWINIT_USE_CCA1_FROM_RX_DIGITAL 307 #define HWINIT_USE_CCA1_FROM_RX_DIGITAL (0) 308 #endif 309 310 /* Reset to 0b0 - Use standalone (new) CCA Mode 2 Engine, decoupled from demodulator */ 311 #ifndef HWINIT_USE_CCA2_DECOUPLED_FROM_DEMOD 312 #define HWINIT_USE_CCA2_DECOUPLED_FROM_DEMOD (0) 313 #endif 314 315 /* The CCA RSSI must come from RX DIG otherwise the CCA will not work correctly and will report 316 last received packet RSSI */ 317 #ifndef HWINIT_CCA1_FROM_RX_DIG 318 #define HWINIT_CCA1_FROM_RX_DIG() (XCVR_ZBDEMOD->CCA_LQI_SRC |= XCVR_ZBDEMOD_CCA_LQI_SRC_CCA1_FROM_RX_DIG(0x1U)) 319 #endif 320 321 /* Configure RFMC->RF2P4GHZ_COEXT instead of ZLL->COEX_PRIORITY registers */ 322 #ifndef HWINIT_USE_RFMC_COEX 323 #define HWINIT_USE_RFMC_COEX (1) 324 #endif 325 326 /* Set COEX_REQ_DELAY_EN for arb_request is delayed until preamble is detected during R sequence. 327 Can be set to 0 or 1 to configure register */ 328 #ifndef HWINIT_COEX_REQ_DELAY_EN_VALUE 329 #define HWINIT_COEX_REQ_DELAY_EN_VALUE (0) 330 #endif 331 332 /* Configure DTEST signals for debug */ 333 #ifndef HWINIT_DEBUG_DTEST 334 #define HWINIT_DEBUG_DTEST (0) 335 #endif 336 337 /* Update finetuned RSSI RSSI_ADJ_NB Offset value */ 338 #ifndef HWINIT_SET_RSSI_ADJUSTEMENT 339 #define HWINIT_SET_RSSI_ADJUSTEMENT 0 340 #endif 341 342 /* RSSI adjustment offset for all channels */ 343 #ifndef HWINIT_RSSI_ADJ_NB 344 #define HWINIT_RSSI_ADJ_NB 0 345 #endif 346 347 /* Use ZLL_PHY_CTRL_TSM_MSK_MASK for ZLL->PHY_CTRL configuration */ 348 #ifndef HWINIT_MASK_TSM_ZLL 349 #define HWINIT_MASK_TSM_ZLL (0) 350 #endif 351 352 /* Configure ZLL->ACKDELAY register */ 353 #ifndef HWINIT_ACKDELAY_VALUE 354 #define HWINIT_ACKDELAY_VALUE (-4) 355 #endif 356 357 /* Configure ZLL->ACKDELAY register */ 358 #ifndef HWINIT_TXDELAY_VALUE 359 #define HWINIT_TXDELAY_VALUE (0) 360 #endif 361 362 /* Configure ZLL->ACKDELAY register */ 363 #ifndef HWINIT_RXDELAY_VALUE 364 #define HWINIT_RXDELAY_VALUE (0) 365 #endif 366 367 /* Configure corectly LQI reporting by WH -> RSSI calculation starts when preamble is detected */ 368 #ifndef HWINIT_RSSI_STARTS_AT_PREAMBLE 369 #define HWINIT_RSSI_STARTS_AT_PREAMBLE (1) 370 #endif 371 372 /* This feature is used for Front End Switching Control. 373 These settings used only for Single Antenna & NA for Dual Ant cases */ 374 #ifndef HWINIT_FRONT_END_SWITCHING_SUPPORT 375 #define HWINIT_FRONT_END_SWITCHING_SUPPORT (0) 376 #endif 377 378 /* Support the use of BCA_BYPASS register */ 379 #ifndef HWINIT_BCA_BYPASS_SUPPORT 380 #define HWINIT_BCA_BYPASS_SUPPORT (1) 381 #endif 382 383 384 /* 385 * Phy IRQ handling functions needed for easier integration in common code. 386 */ 387 #ifndef PHY_PhyIrqCreate 388 #define PHY_PhyIrqCreate() 389 #endif 390 391 #ifndef PHY_PhyIrqClearPending 392 #define PHY_PhyIrqClearPending() NVIC_ClearPendingIRQ(gPhyIrqNo_d) 393 #endif 394 395 #ifndef PHY_PhyIrqSetPending 396 #define PHY_PhyIrqSetPending() NVIC_SetPendingIRQ(gPhyIrqNo_d) 397 #endif 398 399 #ifndef PHY_PhyIrqEnable 400 #define PHY_PhyIrqEnable() NVIC_EnableIRQ(gPhyIrqNo_d); 401 #endif 402 403 #ifndef PHY_PhyIrqDisable 404 #define PHY_PhyIrqDisable() NVIC_DisableIRQ(gPhyIrqNo_d); 405 #endif 406 407 #ifndef PHY_PhyIrqSetPriority 408 #define PHY_PhyIrqSetPriority() NVIC_SetPriority(gPhyIrqNo_d, gPhyIrqPriority_c >> (8 - __NVIC_PRIO_BITS)); 409 #endif 410 411 /* Set a PHY CTRL register field, defined for easier integration in common code.*/ 412 #ifndef SET_PHYCTRL_FIELD 413 #define SET_PHYCTRL_FIELD(mask) ZLL->PHY_CTRL |= (mask ## _MASK) 414 #endif 415 416 /* clear a PHY CTRL register field, defined for easier integration in common code.*/ 417 #ifndef CLR_PHYCTRL_FIELD 418 #define CLR_PHYCTRL_FIELD(mask) ZLL->PHY_CTRL &= ~(mask ## _MASK) 419 #endif 420 421 /* 422 * IsCpuInterruptContext : returns 1 if CPU is in interrupt context and 0 if not. 423 * Not define for common case, returns always 0 424 */ 425 #ifndef IsCpuInterruptContext 426 #define IsCpuInterruptContext() 0 427 #endif 428 429 void PhyPlatformHwInit(); 430 431 /* 432 * functions used during FPGA stage 433 */ 434 #ifndef FFU_FPGA_INTF 435 #define FFU_FPGA_INTF (0) 436 #endif 437 438 #if FFU_FPGA_INTF == 1 439 void FPGA_SendChannelSwitchCmd(uint32_t channel); 440 void FPGA_SendSetPwrLevelCmd(uint8_t pwrStep); 441 #else 442 #define FPGA_SendChannelSwitchCmd(channel) 443 #define FPGA_SendSetPwrLevelCmd(pwrStep) 444 #endif 445 446 /* 447 * Default RSSI offset definition 448 */ 449 #ifndef gChannelRssiOffset_c 450 #define gChannelRssiOffset_c { 0, /* 11 */ \ 451 0, /* 12 */ \ 452 0, /* 13 */ \ 453 0, /* 14 */ \ 454 0, /* 15 */ \ 455 0, /* 16 */ \ 456 0, /* 17 */ \ 457 0, /* 18 */ \ 458 0, /* 19 */ \ 459 0, /* 20 */ \ 460 0, /* 21 */ \ 461 0, /* 22 */ \ 462 0, /* 23 */ \ 463 0, /* 24 */ \ 464 0, /* 25 */ \ 465 0 } /* 26 */ 466 #endif 467 468 #endif /* __PHY_PLATFORM_H__ */ 469
