1 /*
2 * Copyright 2021-2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file Mru_Ip_Irq.c
9 *
10 * @version 2.0.0
11 *
12 * @brief ISR handler file.
13 * @details Declaration APIs for Mru ISR.
14 *
15 * @addtogroup MRU_IP_DRIVER Mru Ip Driver
16 * @{
17 */
18
19 #ifdef __cplusplus
20 extern "C"
21 {
22 #endif
23
24 /*==================================================================================================
25 * INCLUDE FILES
26 * 1) system and project includes
27 * 2) needed interfaces from external units
28 * 3) internal and external interfaces from this unit
29 ==================================================================================================*/
30 #include "Mru_Ip.h"
31
32 /*==================================================================================================
33 * SOURCE FILE VERSION INFORMATION
34 ==================================================================================================*/
35 #define CDD_PLATFORM_MRU_IP_VENDOR_ID_IRQ_C 43
36 #define CDD_PLATFORM_MRU_IP_AR_RELEASE_MAJOR_VERSION_IRQ_C 4
37 #define CDD_PLATFORM_MRU_IP_AR_RELEASE_MINOR_VERSION_IRQ_C 7
38 #define CDD_PLATFORM_MRU_IP_AR_RELEASE_REVISION_VERSION_IRQ_C 0
39 #define CDD_PLATFORM_MRU_IP_SW_MAJOR_VERSION_IRQ_C 2
40 #define CDD_PLATFORM_MRU_IP_SW_MINOR_VERSION_IRQ_C 0
41 #define CDD_PLATFORM_MRU_IP_SW_PATCH_VERSION_IRQ_C 0
42 /*==================================================================================================
43 * FILE VERSION CHECKS
44 ==================================================================================================*/
45 /* Check if Mru_Ip.h and Mru_Ip_Irq.c are of the same vendor */
46 #if (CDD_PLATFORM_MRU_IP_VENDOR_ID != CDD_PLATFORM_MRU_IP_VENDOR_ID_IRQ_C)
47 #error "Mru_Ip.h and Mru_Ip_Irq.c have different vendor ids"
48 #endif
49 /* Check if Mru_Ip.h file and Mru_Ip_Irq.c file are of the same Autosar version */
50 #if ((CDD_PLATFORM_MRU_IP_AR_RELEASE_MAJOR_VERSION != CDD_PLATFORM_MRU_IP_AR_RELEASE_MAJOR_VERSION_IRQ_C) || \
51 (CDD_PLATFORM_MRU_IP_AR_RELEASE_MINOR_VERSION != CDD_PLATFORM_MRU_IP_AR_RELEASE_MINOR_VERSION_IRQ_C) || \
52 (CDD_PLATFORM_MRU_IP_AR_RELEASE_REVISION_VERSION != CDD_PLATFORM_MRU_IP_AR_RELEASE_REVISION_VERSION_IRQ_C))
53 #error "AutoSar Version Numbers of Mru_Ip.h and Mru_Ip_Irq.c are different"
54 #endif
55 #if ((CDD_PLATFORM_MRU_IP_SW_MAJOR_VERSION != CDD_PLATFORM_MRU_IP_SW_MAJOR_VERSION_IRQ_C) || \
56 (CDD_PLATFORM_MRU_IP_SW_MINOR_VERSION != CDD_PLATFORM_MRU_IP_SW_MINOR_VERSION_IRQ_C) || \
57 (CDD_PLATFORM_MRU_IP_SW_PATCH_VERSION != CDD_PLATFORM_MRU_IP_SW_PATCH_VERSION_IRQ_C))
58 #error "Software Version Numbers of Mru_Ip.h and Mru_Ip_Irq.c are different"
59 #endif
60 /*==================================================================================================
61 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
62 ==================================================================================================*/
63 /*==================================================================================================
64 * LOCAL MACROS
65 ==================================================================================================*/
66 /*==================================================================================================
67 * LOCAL CONSTANTS
68 ==================================================================================================*/
69 /*==================================================================================================
70 * LOCAL VARIABLES
71 ==================================================================================================*/
72 /*==================================================================================================
73 * GLOBAL CONSTANTS
74 ==================================================================================================*/
75 /*==================================================================================================
76 * GLOBAL VARIABLES
77 ==================================================================================================*/
78 #ifdef PLATFORM_IP_ENABLE_MRU
79 #if (PLATFORM_IP_ENABLE_MRU == STD_ON)
80
81 #define PLATFORM_START_SEC_VAR_CLEARED_UNSPECIFIED
82 #include "Platform_MemMap.h"
83
84 extern Mru_Ip_StateStructureType* Mru_Ip_apxStateStructureArray[MRU_IP_NUMBER_OF_INSTANCES];
85
86 #define PLATFORM_STOP_SEC_VAR_CLEARED_UNSPECIFIED
87 #include "Platform_MemMap.h"
88 /*==================================================================================================
89 * LOCAL FUNCTION PROTOTYPES
90 ==================================================================================================*/
91 #define PLATFORM_START_SEC_CODE
92 #include "Platform_MemMap.h"
93
94 #ifdef SMU_MRU_ENABLED
95 #if (!defined MRU_IP_SKIP_SMU_MRU_INT0_HANDLER)
96 ISR(Mru_Ip_SMU_MRU_Int0_IRQHandler);
97 #endif
98 #if (!defined MRU_IP_SKIP_SMU_MRU_INT1_HANDLER)
99 ISR(Mru_Ip_SMU_MRU_Int1_IRQHandler);
100 #endif
101 #endif
102
103 #ifdef RTU0_MRU0_ENABLED
104 #if (!defined MRU_IP_SKIP_RTU0_MRU0_INT0_HANDLER)
105 ISR(Mru_Ip_RTU0_MRU0_Int0_IRQHandler);
106 #endif
107 #if (!defined MRU_IP_SKIP_RTU0_MRU0_INT1_HANDLER)
108 ISR(Mru_Ip_RTU0_MRU0_Int1_IRQHandler);
109 #endif
110 #endif
111
112 #ifdef RTU0_MRU1_ENABLED
113 #if (!defined MRU_IP_SKIP_RTU0_MRU1_INT0_HANDLER)
114 ISR(Mru_Ip_RTU0_MRU1_Int0_IRQHandler);
115 #endif
116 #if (!defined MRU_IP_SKIP_RTU0_MRU1_INT1_HANDLER)
117 ISR(Mru_Ip_RTU0_MRU1_Int1_IRQHandler);
118 #endif
119 #endif
120
121 #ifdef RTU0_MRU2_ENABLED
122 #if (!defined MRU_IP_SKIP_RTU0_MRU2_INT0_HANDLER)
123 ISR(Mru_Ip_RTU0_MRU2_Int0_IRQHandler);
124 #endif
125 #if (!defined MRU_IP_SKIP_RTU0_MRU2_INT1_HANDLER)
126 ISR(Mru_Ip_RTU0_MRU2_Int1_IRQHandler);
127 #endif
128 #endif
129
130 #ifdef RTU0_MRU3_ENABLED
131 #if (!defined MRU_IP_SKIP_RTU0_MRU3_INT0_HANDLER)
132 ISR(Mru_Ip_RTU0_MRU3_Int0_IRQHandler);
133 #endif
134 #if (!defined MRU_IP_SKIP_RTU0_MRU3_INT1_HANDLER)
135 ISR(Mru_Ip_RTU0_MRU3_Int1_IRQHandler);
136 #endif
137 #endif
138
139 #ifdef RTU1_MRU4_ENABLED
140 #if (!defined MRU_IP_SKIP_RTU1_MRU4_INT0_HANDLER)
141 ISR(Mru_Ip_RTU1_MRU4_Int0_IRQHandler);
142 #endif
143 #if (!defined MRU_IP_SKIP_RTU1_MRU4_INT1_HANDLER)
144 ISR(Mru_Ip_RTU1_MRU4_Int1_IRQHandler);
145 #endif
146 #endif
147
148 #ifdef RTU1_MRU5_ENABLED
149 #if (!defined MRU_IP_SKIP_RTU1_MRU5_INT0_HANDLER)
150 ISR(Mru_Ip_RTU1_MRU5_Int0_IRQHandler);
151 #endif
152 #if (!defined MRU_IP_SKIP_RTU1_MRU5_INT1_HANDLER)
153 ISR(Mru_Ip_RTU1_MRU5_Int1_IRQHandler);
154 #endif
155 #endif
156
157 #ifdef RTU1_MRU6_ENABLED
158 #if (!defined MRU_IP_SKIP_RTU1_MRU6_INT0_HANDLER)
159 ISR(Mru_Ip_RTU1_MRU6_Int0_IRQHandler);
160 #endif
161 #if (!defined MRU_IP_SKIP_RTU1_MRU6_INT1_HANDLER)
162 ISR(Mru_Ip_RTU1_MRU6_Int1_IRQHandler);
163 #endif
164 #endif
165
166 #ifdef RTU1_MRU7_ENABLED
167 #if (!defined MRU_IP_SKIP_RTU1_MRU7_INT0_HANDLER)
168 ISR(Mru_Ip_RTU1_MRU7_Int0_IRQHandler);
169 #endif
170 #if (!defined MRU_IP_SKIP_RTU1_MRU7_INT1_HANDLER)
171 ISR(Mru_Ip_RTU1_MRU7_Int1_IRQHandler);
172 #endif
173 #endif
174
175 #ifdef CE_MRU0_ENABLED
176 #if (!defined MRU_IP_SKIP_CE_MRU0_INT0_HANDLER)
177 ISR(Mru_Ip_CE_MRU0_Int0_IRQHandler);
178 #endif
179 #if (!defined MRU_IP_SKIP_CE_MRU0_INT1_HANDLER)
180 ISR(Mru_Ip_CE_MRU0_Int1_IRQHandler);
181 #endif
182 #endif
183
184 #ifdef CE_MRU1_ENABLED
185 #if (!defined MRU_IP_SKIP_CE_MRU1_INT0_HANDLER)
186 ISR(Mru_Ip_CE_MRU1_Int0_IRQHandler);
187 #endif
188 #if (!defined MRU_IP_SKIP_CE_MRU1_INT1_HANDLER)
189 ISR(Mru_Ip_CE_MRU1_Int1_IRQHandler);
190 #endif
191 #endif
192
193 #ifdef CE_MRU2_ENABLED
194 #if (!defined MRU_IP_SKIP_CE_MRU2_INT0_HANDLER)
195 ISR(Mru_Ip_CE_MRU2_Int0_IRQHandler);
196 #endif
197 #if (!defined MRU_IP_SKIP_CE_MRU2_INT1_HANDLER)
198 ISR(Mru_Ip_CE_MRU2_Int1_IRQHandler);
199 #endif
200 #endif
201
202 #ifdef CE_MRU3_ENABLED
203 #if (!defined MRU_IP_SKIP_CE_MRU3_INT0_HANDLER)
204 ISR(Mru_Ip_CE_MRU3_Int0_IRQHandler);
205 #endif
206 #if (!defined MRU_IP_SKIP_CE_MRU3_INT1_HANDLER)
207 ISR(Mru_Ip_CE_MRU3_Int1_IRQHandler);
208 #endif
209 #endif
210
211 #ifdef CE_MRU4_ENABLED
212 #if (!defined MRU_IP_SKIP_CE_MRU4_INT0_HANDLER)
213 ISR(Mru_Ip_CE_MRU4_Int0_IRQHandler);
214 #endif
215 #if (!defined MRU_IP_SKIP_CE_MRU4_INT1_HANDLER)
216 ISR(Mru_Ip_CE_MRU4_Int1_IRQHandler);
217 #endif
218 #endif
219
220 #ifdef CE_MRU5_ENABLED
221 #if (!defined MRU_IP_SKIP_CE_MRU5_INT0_HANDLER)
222 ISR(Mru_Ip_CE_MRU5_Int0_IRQHandler);
223 #endif
224 #if (!defined MRU_IP_SKIP_CE_MRU5_INT1_HANDLER)
225 ISR(Mru_Ip_CE_MRU5_Int1_IRQHandler);
226 #endif
227 #endif
228
229 #ifdef CE_MRU6_ENABLED
230 #if (!defined MRU_IP_SKIP_CE_MRU6_INT0_HANDLER)
231 ISR(Mru_Ip_CE_MRU6_Int0_IRQHandler);
232 #endif
233 #if (!defined MRU_IP_SKIP_CE_MRU6_INT1_HANDLER)
234 ISR(Mru_Ip_CE_MRU6_Int1_IRQHandler);
235 #endif
236 #endif
237
238 #ifdef CE_MRU7_ENABLED
239 #if (!defined MRU_IP_SKIP_CE_MRU7_INT0_HANDLER)
240 ISR(Mru_Ip_CE_MRU7_Int0_IRQHandler);
241 #endif
242 #if (!defined MRU_IP_SKIP_CE_MRU7_INT1_HANDLER)
243 ISR(Mru_Ip_CE_MRU7_Int1_IRQHandler);
244 #endif
245 #endif
246
247 #ifdef CE_MRU8_ENABLED
248 #if (!defined MRU_IP_SKIP_CE_MRU8_INT0_HANDLER)
249 ISR(Mru_Ip_CE_MRU8_Int0_IRQHandler);
250 #endif
251 #if (!defined MRU_IP_SKIP_CE_MRU8_INT1_HANDLER)
252 ISR(Mru_Ip_CE_MRU8_Int1_IRQHandler);
253 #endif
254 #endif
255
256 #ifdef CE_MRU9_ENABLED
257 #if (!defined MRU_IP_SKIP_CE_MRU9_INT0_HANDLER)
258 ISR(Mru_Ip_CE_MRU9_Int0_IRQHandler);
259 #endif
260 #if (!defined MRU_IP_SKIP_CE_MRU9_INT1_HANDLER)
261 ISR(Mru_Ip_CE_MRU9_Int1_IRQHandler);
262 #endif
263 #endif
264
265 #ifdef CE_MRU10_ENABLED
266 #if (!defined MRU_IP_SKIP_CE_MRU10_INT0_HANDLER)
267 ISR(Mru_Ip_CE_MRU10_Int0_IRQHandler);
268 #endif
269 #if (!defined MRU_IP_SKIP_CE_MRU10_INT1_HANDLER)
270 ISR(Mru_Ip_CE_MRU10_Int1_IRQHandler);
271 #endif
272 #endif
273
274 #ifdef CE_MRU11_ENABLED
275 #if (!defined MRU_IP_SKIP_CE_MRU11_INT0_HANDLER)
276 ISR(Mru_Ip_CE_MRU11_Int0_IRQHandler);
277 #endif
278 #if (!defined MRU_IP_SKIP_CE_MRU11_INT1_HANDLER)
279 ISR(Mru_Ip_CE_MRU11_Int1_IRQHandler);
280 #endif
281 #endif
282
283 #ifdef CE_MRU12_ENABLED
284 #if (!defined MRU_IP_SKIP_CE_MRU12_INT0_HANDLER)
285 ISR(Mru_Ip_CE_MRU12_Int0_IRQHandler);
286 #endif
287 #if (!defined MRU_IP_SKIP_CE_MRU12_INT1_HANDLER)
288 ISR(Mru_Ip_CE_MRU12_Int1_IRQHandler);
289 #endif
290 #endif
291
292 #ifdef CE_MRU13_ENABLED
293 #if (!defined MRU_IP_SKIP_CE_MRU13_INT0_HANDLER)
294 ISR(Mru_Ip_CE_MRU13_Int0_IRQHandler);
295 #endif
296 #if (!defined MRU_IP_SKIP_CE_MRU13_INT1_HANDLER)
297 ISR(Mru_Ip_CE_MRU13_Int1_IRQHandler);
298 #endif
299 #endif
300
301 #ifdef CE_MRU14_ENABLED
302 #if (!defined MRU_IP_SKIP_CE_MRU14_INT0_HANDLER)
303 ISR(Mru_Ip_CE_MRU14_Int0_IRQHandler);
304 #endif
305 #if (!defined MRU_IP_SKIP_CE_MRU14_INT1_HANDLER)
306 ISR(Mru_Ip_CE_MRU14_Int1_IRQHandler);
307 #endif
308 #endif
309
310 #ifdef CE_MRU15_ENABLED
311 #if (!defined MRU_IP_SKIP_CE_MRU15_INT0_HANDLER)
312 ISR(Mru_Ip_CE_MRU15_Int0_IRQHandler);
313 #endif
314 #if (!defined MRU_IP_SKIP_CE_MRU15_INT1_HANDLER)
315 ISR(Mru_Ip_CE_MRU15_Int1_IRQHandler);
316 #endif
317 #endif
318
319 #ifdef CE_MRU16_ENABLED
320 #if (!defined MRU_IP_SKIP_CE_MRU16_INT0_HANDLER)
321 ISR(Mru_Ip_CE_MRU16_Int0_IRQHandler);
322 #endif
323 #if (!defined MRU_IP_SKIP_CE_MRU16_INT1_HANDLER)
324 ISR(Mru_Ip_CE_MRU16_Int1_IRQHandler);
325 #endif
326 #endif
327
328 #ifdef CE_MRU17_ENABLED
329 #if (!defined MRU_IP_SKIP_CE_MRU17_INT0_HANDLER)
330 ISR(Mru_Ip_CE_MRU17_Int0_IRQHandler);
331 #endif
332 #if (!defined MRU_IP_SKIP_CE_MRU17_INT1_HANDLER)
333 ISR(Mru_Ip_CE_MRU17_Int1_IRQHandler);
334 #endif
335 #endif
336
337 #ifdef CE_MRU18_ENABLED
338 #if (!defined MRU_IP_SKIP_CE_MRU18_INT0_HANDLER)
339 ISR(Mru_Ip_CE_MRU18_Int0_IRQHandler);
340 #endif
341 #if (!defined MRU_IP_SKIP_CE_MRU18_INT1_HANDLER)
342 ISR(Mru_Ip_CE_MRU18_Int1_IRQHandler);
343 #endif
344 #endif
345
346 #ifdef CE_MRU19_ENABLED
347 #if (!defined MRU_IP_SKIP_CE_MRU19_INT0_HANDLER)
348 ISR(Mru_Ip_CE_MRU19_Int0_IRQHandler);
349 #endif
350 #if (!defined MRU_IP_SKIP_CE_MRU19_INT1_HANDLER)
351 ISR(Mru_Ip_CE_MRU19_Int1_IRQHandler);
352 #endif
353 #endif
354
355 #if ((defined CE_MRU6_ENABLED && (!defined MRU_IP_SKIP_CE_MRU6_INT0_HANDLER)) || (defined CE_MRU7_ENABLED && (!defined MRU_IP_SKIP_CE_MRU7_INT0_HANDLER)) || (defined CE_MRU8_ENABLED && (!defined MRU_IP_SKIP_CE_MRU8_INT0_HANDLER)) || \
356 (defined CE_MRU9_ENABLED && (!defined MRU_IP_SKIP_CE_MRU9_INT0_HANDLER)) || (defined CE_MRU10_ENABLED && (!defined MRU_IP_SKIP_CE_MRU10_INT0_HANDLER)) || (defined CE_MRU11_ENABLED && (!defined MRU_IP_SKIP_CE_MRU11_INT0_HANDLER)))
357 ISR(Mru_Ip_CE_MRU6_TO_MRU11_Int0_IRQHandler);
358 #endif
359 #if ((defined CE_MRU6_ENABLED && (!defined MRU_IP_SKIP_CE_MRU6_INT1_HANDLER)) || (defined CE_MRU7_ENABLED && (!defined MRU_IP_SKIP_CE_MRU7_INT1_HANDLER)) || (defined CE_MRU8_ENABLED && (!defined MRU_IP_SKIP_CE_MRU8_INT1_HANDLER)) || \
360 (defined CE_MRU9_ENABLED && (!defined MRU_IP_SKIP_CE_MRU9_INT1_HANDLER)) || (defined CE_MRU10_ENABLED && (!defined MRU_IP_SKIP_CE_MRU10_INT1_HANDLER)) || (defined CE_MRU11_ENABLED && (!defined MRU_IP_SKIP_CE_MRU11_INT1_HANDLER)))
361 ISR(Mru_Ip_CE_MRU6_TO_MRU11_Int1_IRQHandler);
362 #endif
363 /*==================================================================================================
364 * LOCAL FUNCTIONS
365 ==================================================================================================*/
366 /*==================================================================================================
367 * GLOBAL FUNCTIONS
368 ==================================================================================================*/
369 #ifdef SMU_MRU_ENABLED
370 #if (!defined MRU_IP_SKIP_SMU_MRU_INT0_HANDLER)
ISR(Mru_Ip_SMU_MRU_Int0_IRQHandler)371 ISR(Mru_Ip_SMU_MRU_Int0_IRQHandler)
372 {
373 SMU_MRU_Type* Base = Mru_Ip_apxSMU_Bases[MRU_IP_SMU_MRU_INSTANCE];
374 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_SMU_MRU_ID];
375 uint8 ChannelIdx;
376
377 if(NULL_PTR != State)
378 {
379 /* the driver has been initialized */
380 /* Processing IRQ */
381 Mru_Ip_IrqHandler(MRU_IP_SMU_MRU_ID, MRU_IP_INT_GROUP_0);
382 }
383 else
384 {
385 /* the driver has not been initialized */
386 /* clear all flags for all channels */
387 for(ChannelIdx = 0u; ChannelIdx < SMU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
388 {
389 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
390 }
391 }
392 }
393 #endif
394 #if (!defined MRU_IP_SKIP_SMU_MRU_INT1_HANDLER)
ISR(Mru_Ip_SMU_MRU_Int1_IRQHandler)395 ISR(Mru_Ip_SMU_MRU_Int1_IRQHandler)
396 {
397 SMU_MRU_Type* Base = Mru_Ip_apxSMU_Bases[MRU_IP_SMU_MRU_INSTANCE];
398 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_SMU_MRU_ID];
399 uint8 ChannelIdx;
400
401 if(NULL_PTR != State)
402 {
403 /* the driver has been initialized */
404 /* Processing IRQ */
405 Mru_Ip_IrqHandler(MRU_IP_SMU_MRU_ID, MRU_IP_INT_GROUP_1);
406 }
407 else
408 {
409 /* the driver has not been initialized */
410 /* clear all flags for all channels */
411 for(ChannelIdx = 0u; ChannelIdx < SMU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
412 {
413 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
414 }
415 }
416 }
417 #endif
418 #endif
419
420 #ifdef RTU0_MRU0_ENABLED
421 #if (!defined MRU_IP_SKIP_RTU0_MRU0_INT0_HANDLER)
ISR(Mru_Ip_RTU0_MRU0_Int0_IRQHandler)422 ISR(Mru_Ip_RTU0_MRU0_Int0_IRQHandler)
423 {
424 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU0_INSTANCE];
425 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU0_MRU0_ID];
426 uint8 ChannelIdx;
427
428 if(NULL_PTR != State)
429 {
430 /* the driver has been initialized */
431 /* Processing IRQ */
432 Mru_Ip_IrqHandler(MRU_IP_RTU0_MRU0_ID, MRU_IP_INT_GROUP_0);
433 }
434 else
435 {
436 /* the driver has not been initialized */
437 /* clear all flags for all channels */
438 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
439 {
440 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
441 }
442 }
443 }
444 #endif
445 #if (!defined MRU_IP_SKIP_RTU0_MRU0_INT1_HANDLER)
ISR(Mru_Ip_RTU0_MRU0_Int1_IRQHandler)446 ISR(Mru_Ip_RTU0_MRU0_Int1_IRQHandler)
447 {
448 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU0_INSTANCE];
449 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU0_MRU0_ID];
450 uint8 ChannelIdx;
451
452 if(NULL_PTR != State)
453 {
454 /* the driver has been initialized */
455 /* Processing IRQ */
456 Mru_Ip_IrqHandler(MRU_IP_RTU0_MRU0_ID, MRU_IP_INT_GROUP_1);
457 }
458 else
459 {
460 /* the driver has not been initialized */
461 /* clear all flags for all channels */
462 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
463 {
464 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
465 }
466 }
467 }
468 #endif
469 #endif
470
471 #ifdef RTU0_MRU1_ENABLED
472 #if (!defined MRU_IP_SKIP_RTU0_MRU1_INT0_HANDLER)
ISR(Mru_Ip_RTU0_MRU1_Int0_IRQHandler)473 ISR(Mru_Ip_RTU0_MRU1_Int0_IRQHandler)
474 {
475 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU1_INSTANCE];
476 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU0_MRU1_ID];
477 uint8 ChannelIdx;
478
479 if(NULL_PTR != State)
480 {
481 /* the driver has been initialized */
482 /* Processing IRQ */
483 Mru_Ip_IrqHandler(MRU_IP_RTU0_MRU1_ID, MRU_IP_INT_GROUP_0);
484 }
485 else
486 {
487 /* the driver has not been initialized */
488 /* clear all flags for all channels */
489 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
490 {
491 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
492 }
493 }
494 }
495 #endif
496 #if (!defined MRU_IP_SKIP_RTU0_MRU1_INT1_HANDLER)
ISR(Mru_Ip_RTU0_MRU1_Int1_IRQHandler)497 ISR(Mru_Ip_RTU0_MRU1_Int1_IRQHandler)
498 {
499 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU1_INSTANCE];
500 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU0_MRU1_ID];
501 uint8 ChannelIdx;
502
503 if(NULL_PTR != State)
504 {
505 /* the driver has been initialized */
506 /* Processing IRQ */
507 Mru_Ip_IrqHandler(MRU_IP_RTU0_MRU1_ID, MRU_IP_INT_GROUP_1);
508 }
509 else
510 {
511 /* the driver has not been initialized */
512 /* clear all flags for all channels */
513 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
514 {
515 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
516 }
517 }
518 }
519 #endif
520 #endif
521
522 #ifdef RTU0_MRU2_ENABLED
523 #if (!defined MRU_IP_SKIP_RTU0_MRU2_INT0_HANDLER)
ISR(Mru_Ip_RTU0_MRU2_Int0_IRQHandler)524 ISR(Mru_Ip_RTU0_MRU2_Int0_IRQHandler)
525 {
526 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU2_INSTANCE];
527 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU0_MRU2_ID];
528 uint8 ChannelIdx;
529
530 if(NULL_PTR != State)
531 {
532 /* the driver has been initialized */
533 /* Processing IRQ */
534 Mru_Ip_IrqHandler(MRU_IP_RTU0_MRU2_ID, MRU_IP_INT_GROUP_0);
535 }
536 else
537 {
538 /* the driver has not been initialized */
539 /* clear all flags for all channels */
540 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
541 {
542 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
543 }
544 }
545 }
546 #endif
547 #if (!defined MRU_IP_SKIP_RTU0_MRU2_INT1_HANDLER)
ISR(Mru_Ip_RTU0_MRU2_Int1_IRQHandler)548 ISR(Mru_Ip_RTU0_MRU2_Int1_IRQHandler)
549 {
550 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU2_INSTANCE];
551 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU0_MRU2_ID];
552 uint8 ChannelIdx;
553
554 if(NULL_PTR != State)
555 {
556 /* the driver has been initialized */
557 /* Processing IRQ */
558 Mru_Ip_IrqHandler(MRU_IP_RTU0_MRU2_ID, MRU_IP_INT_GROUP_1);
559 }
560 else
561 {
562 /* the driver has not been initialized */
563 /* clear all flags for all channels */
564 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
565 {
566 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
567 }
568 }
569 }
570 #endif
571 #endif
572
573 #ifdef RTU0_MRU3_ENABLED
574 #if (!defined MRU_IP_SKIP_RTU0_MRU3_INT0_HANDLER)
ISR(Mru_Ip_RTU0_MRU3_Int0_IRQHandler)575 ISR(Mru_Ip_RTU0_MRU3_Int0_IRQHandler)
576 {
577 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU3_INSTANCE];
578 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU0_MRU3_ID];
579 uint8 ChannelIdx;
580
581 if(NULL_PTR != State)
582 {
583 /* the driver has been initialized */
584 /* Processing IRQ */
585 Mru_Ip_IrqHandler(MRU_IP_RTU0_MRU3_ID, MRU_IP_INT_GROUP_0);
586 }
587 else
588 {
589 /* the driver has not been initialized */
590 /* clear all flags for all channels */
591 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
592 {
593 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
594 }
595 }
596 }
597 #endif
598 #if (!defined MRU_IP_SKIP_RTU0_MRU3_INT1_HANDLER)
ISR(Mru_Ip_RTU0_MRU3_Int1_IRQHandler)599 ISR(Mru_Ip_RTU0_MRU3_Int1_IRQHandler)
600 {
601 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU3_INSTANCE];
602 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU0_MRU3_ID];
603 uint8 ChannelIdx;
604
605 if(NULL_PTR != State)
606 {
607 /* the driver has been initialized */
608 /* Processing IRQ */
609 Mru_Ip_IrqHandler(MRU_IP_RTU0_MRU3_ID, MRU_IP_INT_GROUP_1);
610 }
611 else
612 {
613 /* the driver has not been initialized */
614 /* clear all flags for all channels */
615 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
616 {
617 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
618 }
619 }
620 }
621 #endif
622 #endif
623
624 #ifdef RTU1_MRU4_ENABLED
625 #if (!defined MRU_IP_SKIP_RTU1_MRU4_INT0_HANDLER)
ISR(Mru_Ip_RTU1_MRU4_Int0_IRQHandler)626 ISR(Mru_Ip_RTU1_MRU4_Int0_IRQHandler)
627 {
628 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU1_MRU4_INSTANCE];
629 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU1_MRU4_ID];
630 uint8 ChannelIdx;
631
632 if(NULL_PTR != State)
633 {
634 /* the driver has been initialized */
635 /* Processing IRQ */
636 Mru_Ip_IrqHandler(MRU_IP_RTU1_MRU4_ID, MRU_IP_INT_GROUP_0);
637 }
638 else
639 {
640 /* the driver has not been initialized */
641 /* clear all flags for all channels */
642 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
643 {
644 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
645 }
646 }
647 }
648 #endif
649 #if (!defined MRU_IP_SKIP_RTU1_MRU4_INT1_HANDLER)
ISR(Mru_Ip_RTU1_MRU4_Int1_IRQHandler)650 ISR(Mru_Ip_RTU1_MRU4_Int1_IRQHandler)
651 {
652 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU1_MRU4_INSTANCE];
653 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU1_MRU4_ID];
654 uint8 ChannelIdx;
655
656 if(NULL_PTR != State)
657 {
658 /* the driver has been initialized */
659 /* Processing IRQ */
660 Mru_Ip_IrqHandler(MRU_IP_RTU1_MRU4_ID, MRU_IP_INT_GROUP_1);
661 }
662 else
663 {
664 /* the driver has not been initialized */
665 /* clear all flags for all channels */
666 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
667 {
668 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
669 }
670 }
671 }
672 #endif
673 #endif
674
675 #ifdef RTU1_MRU5_ENABLED
676 #if (!defined MRU_IP_SKIP_RTU1_MRU5_INT0_HANDLER)
ISR(Mru_Ip_RTU1_MRU5_Int0_IRQHandler)677 ISR(Mru_Ip_RTU1_MRU5_Int0_IRQHandler)
678 {
679 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU1_MRU5_INSTANCE];
680 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU1_MRU5_ID];
681 uint8 ChannelIdx;
682
683 if(NULL_PTR != State)
684 {
685 /* the driver has been initialized */
686 /* Processing IRQ */
687 Mru_Ip_IrqHandler(MRU_IP_RTU1_MRU5_ID, MRU_IP_INT_GROUP_0);
688 }
689 else
690 {
691 /* the driver has not been initialized */
692 /* clear all flags for all channels */
693 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
694 {
695 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
696 }
697 }
698 }
699 #endif
700 #if (!defined MRU_IP_SKIP_RTU1_MRU5_INT1_HANDLER)
ISR(Mru_Ip_RTU1_MRU5_Int1_IRQHandler)701 ISR(Mru_Ip_RTU1_MRU5_Int1_IRQHandler)
702 {
703 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU1_MRU5_INSTANCE];
704 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU1_MRU5_ID];
705 uint8 ChannelIdx;
706
707 if(NULL_PTR != State)
708 {
709 /* the driver has been initialized */
710 /* Processing IRQ */
711 Mru_Ip_IrqHandler(MRU_IP_RTU1_MRU5_ID, MRU_IP_INT_GROUP_1);
712 }
713 else
714 {
715 /* the driver has not been initialized */
716 /* clear all flags for all channels */
717 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
718 {
719 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
720 }
721 }
722 }
723 #endif
724 #endif
725
726 #ifdef RTU1_MRU6_ENABLED
727 #if (!defined MRU_IP_SKIP_RTU1_MRU6_INT0_HANDLER)
ISR(Mru_Ip_RTU1_MRU6_Int0_IRQHandler)728 ISR(Mru_Ip_RTU1_MRU6_Int0_IRQHandler)
729 {
730 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU1_MRU6_INSTANCE];
731 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU1_MRU6_ID];
732 uint8 ChannelIdx;
733
734 if(NULL_PTR != State)
735 {
736 /* the driver has been initialized */
737 /* Processing IRQ */
738 Mru_Ip_IrqHandler(MRU_IP_RTU1_MRU6_ID, MRU_IP_INT_GROUP_0);
739 }
740 else
741 {
742 /* the driver has not been initialized */
743 /* clear all flags for all channels */
744 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
745 {
746 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
747 }
748 }
749 }
750 #endif
751 #if (!defined MRU_IP_SKIP_RTU1_MRU6_INT1_HANDLER)
ISR(Mru_Ip_RTU1_MRU6_Int1_IRQHandler)752 ISR(Mru_Ip_RTU1_MRU6_Int1_IRQHandler)
753 {
754 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU1_MRU6_INSTANCE];
755 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU1_MRU6_ID];
756 uint8 ChannelIdx;
757
758 if(NULL_PTR != State)
759 {
760 /* the driver has been initialized */
761 /* Processing IRQ */
762 Mru_Ip_IrqHandler(MRU_IP_RTU1_MRU6_ID, MRU_IP_INT_GROUP_1);
763 }
764 else
765 {
766 /* the driver has not been initialized */
767 /* clear all flags for all channels */
768 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
769 {
770 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
771 }
772 }
773 }
774 #endif
775 #endif
776
777 #ifdef RTU1_MRU7_ENABLED
778 #if (!defined MRU_IP_SKIP_RTU1_MRU7_INT0_HANDLER)
ISR(Mru_Ip_RTU1_MRU7_Int0_IRQHandler)779 ISR(Mru_Ip_RTU1_MRU7_Int0_IRQHandler)
780 {
781 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU1_MRU7_INSTANCE];
782 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU1_MRU7_ID];
783 uint8 ChannelIdx;
784
785 if(NULL_PTR != State)
786 {
787 /* the driver has been initialized */
788 /* Processing IRQ */
789 Mru_Ip_IrqHandler(MRU_IP_RTU1_MRU7_ID, MRU_IP_INT_GROUP_0);
790 }
791 else
792 {
793 /* the driver has not been initialized */
794 /* clear all flags for all channels */
795 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
796 {
797 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
798 }
799 }
800 }
801 #endif
802 #if (!defined MRU_IP_SKIP_RTU1_MRU7_INT1_HANDLER)
ISR(Mru_Ip_RTU1_MRU7_Int1_IRQHandler)803 ISR(Mru_Ip_RTU1_MRU7_Int1_IRQHandler)
804 {
805 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU1_MRU7_INSTANCE];
806 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU1_MRU7_ID];
807 uint8 ChannelIdx;
808
809 if(NULL_PTR != State)
810 {
811 /* the driver has been initialized */
812 /* Processing IRQ */
813 Mru_Ip_IrqHandler(MRU_IP_RTU1_MRU7_ID, MRU_IP_INT_GROUP_1);
814 }
815 else
816 {
817 /* the driver has not been initialized */
818 /* clear all flags for all channels */
819 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
820 {
821 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
822 }
823 }
824 }
825 #endif
826 #endif
827
828 #ifdef CE_MRU0_ENABLED
829 #if (!defined MRU_IP_SKIP_CE_MRU0_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU0_Int0_IRQHandler)830 ISR(Mru_Ip_CE_MRU0_Int0_IRQHandler)
831 {
832 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU0_INSTANCE];
833 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU0_ID];
834 uint8 ChannelIdx;
835
836 if(NULL_PTR != State)
837 {
838 /* the driver has been initialized */
839 /* Processing IRQ */
840 Mru_Ip_IrqHandler(MRU_IP_CE_MRU0_ID, MRU_IP_INT_GROUP_0);
841 }
842 else
843 {
844 /* the driver has not been initialized */
845 /* clear all flags for all channels */
846 for(ChannelIdx = 0u; ChannelIdx < CE_MRU0_CH_NUM; ChannelIdx++)
847 {
848 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
849 }
850 }
851 }
852 #endif
853 #if (!defined MRU_IP_SKIP_CE_MRU0_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU0_Int1_IRQHandler)854 ISR(Mru_Ip_CE_MRU0_Int1_IRQHandler)
855 {
856 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU0_INSTANCE];
857 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU0_ID];
858 uint8 ChannelIdx;
859
860 if(NULL_PTR != State)
861 {
862 /* the driver has been initialized */
863 /* Processing IRQ */
864 Mru_Ip_IrqHandler(MRU_IP_CE_MRU0_ID, MRU_IP_INT_GROUP_1);
865 }
866 else
867 {
868 /* the driver has not been initialized */
869 /* clear all flags for all channels */
870 for(ChannelIdx = 0u; ChannelIdx < CE_MRU0_CH_NUM; ChannelIdx++)
871 {
872 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
873 }
874 }
875 }
876 #endif
877 #endif
878
879 #ifdef CE_MRU1_ENABLED
880 #if (!defined MRU_IP_SKIP_CE_MRU1_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU1_Int0_IRQHandler)881 ISR(Mru_Ip_CE_MRU1_Int0_IRQHandler)
882 {
883 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU1_INSTANCE];
884 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU1_ID];
885 uint8 ChannelIdx;
886
887 if(NULL_PTR != State)
888 {
889 /* the driver has been initialized */
890 /* Processing IRQ */
891 Mru_Ip_IrqHandler(MRU_IP_CE_MRU1_ID, MRU_IP_INT_GROUP_0);
892 }
893 else
894 {
895 /* the driver has not been initialized */
896 /* clear all flags for all channels */
897 for(ChannelIdx = 0u; ChannelIdx < CE_MRU1_CH_NUM; ChannelIdx++)
898 {
899 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
900 }
901 }
902 }
903 #endif
904 #if (!defined MRU_IP_SKIP_CE_MRU1_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU1_Int1_IRQHandler)905 ISR(Mru_Ip_CE_MRU1_Int1_IRQHandler)
906 {
907 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU1_INSTANCE];
908 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU1_ID];
909 uint8 ChannelIdx;
910
911 if(NULL_PTR != State)
912 {
913 /* the driver has been initialized */
914 /* Processing IRQ */
915 Mru_Ip_IrqHandler(MRU_IP_CE_MRU1_ID, MRU_IP_INT_GROUP_1);
916 }
917 else
918 {
919 /* the driver has not been initialized */
920 /* clear all flags for all channels */
921 for(ChannelIdx = 0u; ChannelIdx < CE_MRU1_CH_NUM; ChannelIdx++)
922 {
923 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
924 }
925 }
926 }
927 #endif
928 #endif
929
930 #ifdef CE_MRU2_ENABLED
931 #if (!defined MRU_IP_SKIP_CE_MRU2_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU2_Int0_IRQHandler)932 ISR(Mru_Ip_CE_MRU2_Int0_IRQHandler)
933 {
934 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU2_INSTANCE];
935 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU2_ID];
936 uint8 ChannelIdx;
937
938 if(NULL_PTR != State)
939 {
940 /* the driver has been initialized */
941 /* Processing IRQ */
942 Mru_Ip_IrqHandler(MRU_IP_CE_MRU2_ID, MRU_IP_INT_GROUP_0);
943 }
944 else
945 {
946 /* the driver has not been initialized */
947 /* clear all flags for all channels */
948 for(ChannelIdx = 0u; ChannelIdx < CE_MRU2_CH_NUM; ChannelIdx++)
949 {
950 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
951 }
952 }
953 }
954 #endif
955 #if (!defined MRU_IP_SKIP_CE_MRU2_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU2_Int1_IRQHandler)956 ISR(Mru_Ip_CE_MRU2_Int1_IRQHandler)
957 {
958 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU2_INSTANCE];
959 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU2_ID];
960 uint8 ChannelIdx;
961
962 if(NULL_PTR != State)
963 {
964 /* the driver has been initialized */
965 /* Processing IRQ */
966 Mru_Ip_IrqHandler(MRU_IP_CE_MRU2_ID, MRU_IP_INT_GROUP_1);
967 }
968 else
969 {
970 /* the driver has not been initialized */
971 /* clear all flags for all channels */
972 for(ChannelIdx = 0u; ChannelIdx < CE_MRU2_CH_NUM; ChannelIdx++)
973 {
974 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
975 }
976 }
977 }
978 #endif
979 #endif
980
981 #ifdef CE_MRU3_ENABLED
982 #if (!defined MRU_IP_SKIP_CE_MRU3_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU3_Int0_IRQHandler)983 ISR(Mru_Ip_CE_MRU3_Int0_IRQHandler)
984 {
985 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU3_INSTANCE];
986 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU3_ID];
987 uint8 ChannelIdx;
988
989 if(NULL_PTR != State)
990 {
991 /* the driver has been initialized */
992 /* Processing IRQ */
993 Mru_Ip_IrqHandler(MRU_IP_CE_MRU3_ID, MRU_IP_INT_GROUP_0);
994 }
995 else
996 {
997 /* the driver has not been initialized */
998 /* clear all flags for all channels */
999 for(ChannelIdx = 0u; ChannelIdx < CE_MRU3_CH_NUM; ChannelIdx++)
1000 {
1001 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1002 }
1003 }
1004 }
1005 #endif
1006 #if (!defined MRU_IP_SKIP_CE_MRU3_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU3_Int1_IRQHandler)1007 ISR(Mru_Ip_CE_MRU3_Int1_IRQHandler)
1008 {
1009 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU3_INSTANCE];
1010 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU3_ID];
1011 uint8 ChannelIdx;
1012
1013 if(NULL_PTR != State)
1014 {
1015 /* the driver has been initialized */
1016 /* Processing IRQ */
1017 Mru_Ip_IrqHandler(MRU_IP_CE_MRU3_ID, MRU_IP_INT_GROUP_1);
1018 }
1019 else
1020 {
1021 /* the driver has not been initialized */
1022 /* clear all flags for all channels */
1023 for(ChannelIdx = 0u; ChannelIdx < CE_MRU3_CH_NUM; ChannelIdx++)
1024 {
1025 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1026 }
1027 }
1028 }
1029 #endif
1030 #endif
1031
1032 #ifdef CE_MRU4_ENABLED
1033 #if (!defined MRU_IP_SKIP_CE_MRU4_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU4_Int0_IRQHandler)1034 ISR(Mru_Ip_CE_MRU4_Int0_IRQHandler)
1035 {
1036 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU4_INSTANCE];
1037 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU4_ID];
1038 uint8 ChannelIdx;
1039
1040 if(NULL_PTR != State)
1041 {
1042 /* the driver has been initialized */
1043 /* Processing IRQ */
1044 Mru_Ip_IrqHandler(MRU_IP_CE_MRU4_ID, MRU_IP_INT_GROUP_0);
1045 }
1046 else
1047 {
1048 /* the driver has not been initialized */
1049 /* clear all flags for all channels */
1050 for(ChannelIdx = 0u; ChannelIdx < CE_MRU4_CH_NUM; ChannelIdx++)
1051 {
1052 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1053 }
1054 }
1055 }
1056 #endif
1057 #if (!defined MRU_IP_SKIP_CE_MRU4_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU4_Int1_IRQHandler)1058 ISR(Mru_Ip_CE_MRU4_Int1_IRQHandler)
1059 {
1060 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU4_INSTANCE];
1061 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU4_ID];
1062 uint8 ChannelIdx;
1063
1064 if(NULL_PTR != State)
1065 {
1066 /* the driver has been initialized */
1067 /* Processing IRQ */
1068 Mru_Ip_IrqHandler(MRU_IP_CE_MRU4_ID, MRU_IP_INT_GROUP_1);
1069 }
1070 else
1071 {
1072 /* the driver has not been initialized */
1073 /* clear all flags for all channels */
1074 for(ChannelIdx = 0u; ChannelIdx < CE_MRU4_CH_NUM; ChannelIdx++)
1075 {
1076 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1077 }
1078 }
1079 }
1080 #endif
1081 #endif
1082
1083 #ifdef CE_MRU5_ENABLED
1084 #if (!defined MRU_IP_SKIP_CE_MRU5_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU5_Int0_IRQHandler)1085 ISR(Mru_Ip_CE_MRU5_Int0_IRQHandler)
1086 {
1087 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU5_INSTANCE];
1088 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU5_ID];
1089 uint8 ChannelIdx;
1090
1091 if(NULL_PTR != State)
1092 {
1093 /* the driver has been initialized */
1094 /* Processing IRQ */
1095 Mru_Ip_IrqHandler(MRU_IP_CE_MRU5_ID, MRU_IP_INT_GROUP_0);
1096 }
1097 else
1098 {
1099 /* the driver has not been initialized */
1100 /* clear all flags for all channels */
1101 for(ChannelIdx = 0u; ChannelIdx < CE_MRU5_CH_NUM; ChannelIdx++)
1102 {
1103 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1104 }
1105 }
1106 }
1107 #endif
1108 #if (!defined MRU_IP_SKIP_CE_MRU5_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU5_Int1_IRQHandler)1109 ISR(Mru_Ip_CE_MRU5_Int1_IRQHandler)
1110 {
1111 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU5_INSTANCE];
1112 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU5_ID];
1113 uint8 ChannelIdx;
1114
1115 if(NULL_PTR != State)
1116 {
1117 /* the driver has been initialized */
1118 /* Processing IRQ */
1119 Mru_Ip_IrqHandler(MRU_IP_CE_MRU5_ID, MRU_IP_INT_GROUP_1);
1120 }
1121 else
1122 {
1123 /* the driver has not been initialized */
1124 /* clear all flags for all channels */
1125 for(ChannelIdx = 0u; ChannelIdx < CE_MRU5_CH_NUM; ChannelIdx++)
1126 {
1127 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1128 }
1129 }
1130 }
1131 #endif
1132 #endif
1133
1134 #ifdef CE_MRU6_ENABLED
1135 #if (!defined MRU_IP_SKIP_CE_MRU6_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU6_Int0_IRQHandler)1136 ISR(Mru_Ip_CE_MRU6_Int0_IRQHandler)
1137 {
1138 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU6_INSTANCE];
1139 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU6_ID];
1140 uint8 ChannelIdx;
1141
1142 if(NULL_PTR != State)
1143 {
1144 /* the driver has been initialized */
1145 /* Processing IRQ */
1146 Mru_Ip_IrqHandler(MRU_IP_CE_MRU6_ID, MRU_IP_INT_GROUP_0);
1147 }
1148 else
1149 {
1150 /* the driver has not been initialized */
1151 /* clear all flags for all channels */
1152 for(ChannelIdx = 0u; ChannelIdx < CE_MRU6_CH_NUM; ChannelIdx++)
1153 {
1154 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1155 }
1156 }
1157 }
1158 #endif
1159 #if (!defined MRU_IP_SKIP_CE_MRU6_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU6_Int1_IRQHandler)1160 ISR(Mru_Ip_CE_MRU6_Int1_IRQHandler)
1161 {
1162 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU6_INSTANCE];
1163 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU6_ID];
1164 uint8 ChannelIdx;
1165
1166 if(NULL_PTR != State)
1167 {
1168 /* the driver has been initialized */
1169 /* Processing IRQ */
1170 Mru_Ip_IrqHandler(MRU_IP_CE_MRU6_ID, MRU_IP_INT_GROUP_1);
1171 }
1172 else
1173 {
1174 /* the driver has not been initialized */
1175 /* clear all flags for all channels */
1176 for(ChannelIdx = 0u; ChannelIdx < CE_MRU6_CH_NUM; ChannelIdx++)
1177 {
1178 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1179 }
1180 }
1181 }
1182 #endif
1183 #endif
1184
1185 #ifdef CE_MRU7_ENABLED
1186 #if (!defined MRU_IP_SKIP_CE_MRU7_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU7_Int0_IRQHandler)1187 ISR(Mru_Ip_CE_MRU7_Int0_IRQHandler)
1188 {
1189 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU7_INSTANCE];
1190 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU7_ID];
1191 uint8 ChannelIdx;
1192
1193 if(NULL_PTR != State)
1194 {
1195 /* the driver has been initialized */
1196 /* Processing IRQ */
1197 Mru_Ip_IrqHandler(MRU_IP_CE_MRU7_ID, MRU_IP_INT_GROUP_0);
1198 }
1199 else
1200 {
1201 /* the driver has not been initialized */
1202 /* clear all flags for all channels */
1203 for(ChannelIdx = 0u; ChannelIdx < CE_MRU7_CH_NUM; ChannelIdx++)
1204 {
1205 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1206 }
1207 }
1208 }
1209 #endif
1210 #if (!defined MRU_IP_SKIP_CE_MRU7_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU7_Int1_IRQHandler)1211 ISR(Mru_Ip_CE_MRU7_Int1_IRQHandler)
1212 {
1213 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU7_INSTANCE];
1214 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU7_ID];
1215 uint8 ChannelIdx;
1216
1217 if(NULL_PTR != State)
1218 {
1219 /* the driver has been initialized */
1220 /* Processing IRQ */
1221 Mru_Ip_IrqHandler(MRU_IP_CE_MRU7_ID, MRU_IP_INT_GROUP_1);
1222 }
1223 else
1224 {
1225 /* the driver has not been initialized */
1226 /* clear all flags for all channels */
1227 for(ChannelIdx = 0u; ChannelIdx < CE_MRU7_CH_NUM; ChannelIdx++)
1228 {
1229 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1230 }
1231 }
1232 }
1233 #endif
1234 #endif
1235
1236 #ifdef CE_MRU8_ENABLED
1237 #if (!defined MRU_IP_SKIP_CE_MRU8_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU8_Int0_IRQHandler)1238 ISR(Mru_Ip_CE_MRU8_Int0_IRQHandler)
1239 {
1240 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU8_INSTANCE];
1241 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU8_ID];
1242 uint8 ChannelIdx;
1243
1244 if(NULL_PTR != State)
1245 {
1246 /* the driver has been initialized */
1247 /* Processing IRQ */
1248 Mru_Ip_IrqHandler(MRU_IP_CE_MRU8_ID, MRU_IP_INT_GROUP_0);
1249 }
1250 else
1251 {
1252 /* the driver has not been initialized */
1253 /* clear all flags for all channels */
1254 for(ChannelIdx = 0u; ChannelIdx < CE_MRU8_CH_NUM; ChannelIdx++)
1255 {
1256 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1257 }
1258 }
1259 }
1260 #endif
1261 #if (!defined MRU_IP_SKIP_CE_MRU8_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU8_Int1_IRQHandler)1262 ISR(Mru_Ip_CE_MRU8_Int1_IRQHandler)
1263 {
1264 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU8_INSTANCE];
1265 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU8_ID];
1266 uint8 ChannelIdx;
1267
1268 if(NULL_PTR != State)
1269 {
1270 /* the driver has been initialized */
1271 /* Processing IRQ */
1272 Mru_Ip_IrqHandler(MRU_IP_CE_MRU8_ID, MRU_IP_INT_GROUP_1);
1273 }
1274 else
1275 {
1276 /* the driver has not been initialized */
1277 /* clear all flags for all channels */
1278 for(ChannelIdx = 0u; ChannelIdx < CE_MRU8_CH_NUM; ChannelIdx++)
1279 {
1280 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1281 }
1282 }
1283 }
1284 #endif
1285 #endif
1286
1287 #ifdef CE_MRU9_ENABLED
1288 #if (!defined MRU_IP_SKIP_CE_MRU9_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU9_Int0_IRQHandler)1289 ISR(Mru_Ip_CE_MRU9_Int0_IRQHandler)
1290 {
1291 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU9_INSTANCE];
1292 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU9_ID];
1293 uint8 ChannelIdx;
1294
1295 if(NULL_PTR != State)
1296 {
1297 /* the driver has been initialized */
1298 /* Processing IRQ */
1299 Mru_Ip_IrqHandler(MRU_IP_CE_MRU9_ID, MRU_IP_INT_GROUP_0);
1300 }
1301 else
1302 {
1303 /* the driver has not been initialized */
1304 /* clear all flags for all channels */
1305 for(ChannelIdx = 0u; ChannelIdx < CE_MRU9_CH_NUM; ChannelIdx++)
1306 {
1307 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1308 }
1309 }
1310 }
1311 #endif
1312 #if (!defined MRU_IP_SKIP_CE_MRU9_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU9_Int1_IRQHandler)1313 ISR(Mru_Ip_CE_MRU9_Int1_IRQHandler)
1314 {
1315 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU9_INSTANCE];
1316 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU9_ID];
1317 uint8 ChannelIdx;
1318
1319 if(NULL_PTR != State)
1320 {
1321 /* the driver has been initialized */
1322 /* Processing IRQ */
1323 Mru_Ip_IrqHandler(MRU_IP_CE_MRU9_ID, MRU_IP_INT_GROUP_1);
1324 }
1325 else
1326 {
1327 /* the driver has not been initialized */
1328 /* clear all flags for all channels */
1329 for(ChannelIdx = 0u; ChannelIdx < CE_MRU9_CH_NUM; ChannelIdx++)
1330 {
1331 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1332 }
1333 }
1334 }
1335 #endif
1336 #endif
1337
1338 #ifdef CE_MRU10_ENABLED
1339 #if (!defined MRU_IP_SKIP_CE_MRU10_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU10_Int0_IRQHandler)1340 ISR(Mru_Ip_CE_MRU10_Int0_IRQHandler)
1341 {
1342 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU10_INSTANCE];
1343 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU10_ID];
1344 uint8 ChannelIdx;
1345
1346 if(NULL_PTR != State)
1347 {
1348 /* the driver has been initialized */
1349 /* Processing IRQ */
1350 Mru_Ip_IrqHandler(MRU_IP_CE_MRU10_ID, MRU_IP_INT_GROUP_0);
1351 }
1352 else
1353 {
1354 /* the driver has not been initialized */
1355 /* clear all flags for all channels */
1356 for(ChannelIdx = 0u; ChannelIdx < CE_MRU10_CH_NUM; ChannelIdx++)
1357 {
1358 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1359 }
1360 }
1361 }
1362 #endif
1363 #if (!defined MRU_IP_SKIP_CE_MRU10_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU10_Int1_IRQHandler)1364 ISR(Mru_Ip_CE_MRU10_Int1_IRQHandler)
1365 {
1366 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU10_INSTANCE];
1367 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU10_ID];
1368 uint8 ChannelIdx;
1369
1370 if(NULL_PTR != State)
1371 {
1372 /* the driver has been initialized */
1373 /* Processing IRQ */
1374 Mru_Ip_IrqHandler(MRU_IP_CE_MRU10_ID, MRU_IP_INT_GROUP_1);
1375 }
1376 else
1377 {
1378 /* the driver has not been initialized */
1379 /* clear all flags for all channels */
1380 for(ChannelIdx = 0u; ChannelIdx < CE_MRU10_CH_NUM; ChannelIdx++)
1381 {
1382 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1383 }
1384 }
1385 }
1386 #endif
1387 #endif
1388
1389 #ifdef CE_MRU11_ENABLED
1390 #if (!defined MRU_IP_SKIP_CE_MRU11_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU11_Int0_IRQHandler)1391 ISR(Mru_Ip_CE_MRU11_Int0_IRQHandler)
1392 {
1393 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU11_INSTANCE];
1394 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU11_ID];
1395 uint8 ChannelIdx;
1396
1397 if(NULL_PTR != State)
1398 {
1399 /* the driver has been initialized */
1400 /* Processing IRQ */
1401 Mru_Ip_IrqHandler(MRU_IP_CE_MRU11_ID, MRU_IP_INT_GROUP_0);
1402 }
1403 else
1404 {
1405 /* the driver has not been initialized */
1406 /* clear all flags for all channels */
1407 for(ChannelIdx = 0u; ChannelIdx < CE_MRU11_CH_NUM; ChannelIdx++)
1408 {
1409 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1410 }
1411 }
1412 }
1413 #endif
1414 #if (!defined MRU_IP_SKIP_CE_MRU11_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU11_Int1_IRQHandler)1415 ISR(Mru_Ip_CE_MRU11_Int1_IRQHandler)
1416 {
1417 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU11_INSTANCE];
1418 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU11_ID];
1419 uint8 ChannelIdx;
1420
1421 if(NULL_PTR != State)
1422 {
1423 /* the driver has been initialized */
1424 /* Processing IRQ */
1425 Mru_Ip_IrqHandler(MRU_IP_CE_MRU11_ID, MRU_IP_INT_GROUP_1);
1426 }
1427 else
1428 {
1429 /* the driver has not been initialized */
1430 /* clear all flags for all channels */
1431 for(ChannelIdx = 0u; ChannelIdx < CE_MRU11_CH_NUM; ChannelIdx++)
1432 {
1433 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1434 }
1435 }
1436 }
1437 #endif
1438 #endif
1439
1440 #ifdef CE_MRU12_ENABLED
1441 #if (!defined MRU_IP_SKIP_CE_MRU12_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU12_Int0_IRQHandler)1442 ISR(Mru_Ip_CE_MRU12_Int0_IRQHandler)
1443 {
1444 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU12_INSTANCE];
1445 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU12_ID];
1446 uint8 ChannelIdx;
1447
1448 if(NULL_PTR != State)
1449 {
1450 /* the driver has been initialized */
1451 /* Processing IRQ */
1452 Mru_Ip_IrqHandler(MRU_IP_CE_MRU12_ID, MRU_IP_INT_GROUP_0);
1453 }
1454 else
1455 {
1456 /* the driver has not been initialized */
1457 /* clear all flags for all channels */
1458 for(ChannelIdx = 0u; ChannelIdx < CE_MRU12_CH_NUM; ChannelIdx++)
1459 {
1460 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1461 }
1462 }
1463 }
1464 #endif
1465 #if (!defined MRU_IP_SKIP_CE_MRU12_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU12_Int1_IRQHandler)1466 ISR(Mru_Ip_CE_MRU12_Int1_IRQHandler)
1467 {
1468 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU12_INSTANCE];
1469 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU12_ID];
1470 uint8 ChannelIdx;
1471
1472 if(NULL_PTR != State)
1473 {
1474 /* the driver has been initialized */
1475 /* Processing IRQ */
1476 Mru_Ip_IrqHandler(MRU_IP_CE_MRU12_ID, MRU_IP_INT_GROUP_1);
1477 }
1478 else
1479 {
1480 /* the driver has not been initialized */
1481 /* clear all flags for all channels */
1482 for(ChannelIdx = 0u; ChannelIdx < CE_MRU12_CH_NUM; ChannelIdx++)
1483 {
1484 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1485 }
1486 }
1487 }
1488 #endif
1489 #endif
1490
1491 #ifdef CE_MRU13_ENABLED
1492 #if (!defined MRU_IP_SKIP_CE_MRU13_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU13_Int0_IRQHandler)1493 ISR(Mru_Ip_CE_MRU13_Int0_IRQHandler)
1494 {
1495 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU13_INSTANCE];
1496 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU13_ID];
1497 uint8 ChannelIdx;
1498
1499 if(NULL_PTR != State)
1500 {
1501 /* the driver has been initialized */
1502 /* Processing IRQ */
1503 Mru_Ip_IrqHandler(MRU_IP_CE_MRU13_ID, MRU_IP_INT_GROUP_0);
1504 }
1505 else
1506 {
1507 /* the driver has not been initialized */
1508 /* clear all flags for all channels */
1509 for(ChannelIdx = 0u; ChannelIdx < CE_MRU13_CH_NUM; ChannelIdx++)
1510 {
1511 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1512 }
1513 }
1514 }
1515 #endif
1516 #if (!defined MRU_IP_SKIP_CE_MRU13_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU13_Int1_IRQHandler)1517 ISR(Mru_Ip_CE_MRU13_Int1_IRQHandler)
1518 {
1519 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU13_INSTANCE];
1520 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU13_ID];
1521 uint8 ChannelIdx;
1522
1523 if(NULL_PTR != State)
1524 {
1525 /* the driver has been initialized */
1526 /* Processing IRQ */
1527 Mru_Ip_IrqHandler(MRU_IP_CE_MRU13_ID, MRU_IP_INT_GROUP_1);
1528 }
1529 else
1530 {
1531 /* the driver has not been initialized */
1532 /* clear all flags for all channels */
1533 for(ChannelIdx = 0u; ChannelIdx < CE_MRU13_CH_NUM; ChannelIdx++)
1534 {
1535 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1536 }
1537 }
1538 }
1539 #endif
1540 #endif
1541
1542 #ifdef CE_MRU14_ENABLED
1543 #if (!defined MRU_IP_SKIP_CE_MRU14_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU14_Int0_IRQHandler)1544 ISR(Mru_Ip_CE_MRU14_Int0_IRQHandler)
1545 {
1546 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU14_INSTANCE];
1547 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU14_ID];
1548 uint8 ChannelIdx;
1549
1550 if(NULL_PTR != State)
1551 {
1552 /* the driver has been initialized */
1553 /* Processing IRQ */
1554 Mru_Ip_IrqHandler(MRU_IP_CE_MRU14_ID, MRU_IP_INT_GROUP_0);
1555 }
1556 else
1557 {
1558 /* the driver has not been initialized */
1559 /* clear all flags for all channels */
1560 for(ChannelIdx = 0u; ChannelIdx < CE_MRU14_CH_NUM; ChannelIdx++)
1561 {
1562 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1563 }
1564 }
1565 }
1566 #endif
1567 #if (!defined MRU_IP_SKIP_CE_MRU14_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU14_Int1_IRQHandler)1568 ISR(Mru_Ip_CE_MRU14_Int1_IRQHandler)
1569 {
1570 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU14_INSTANCE];
1571 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU14_ID];
1572 uint8 ChannelIdx;
1573
1574 if(NULL_PTR != State)
1575 {
1576 /* the driver has been initialized */
1577 /* Processing IRQ */
1578 Mru_Ip_IrqHandler(MRU_IP_CE_MRU14_ID, MRU_IP_INT_GROUP_1);
1579 }
1580 else
1581 {
1582 /* the driver has not been initialized */
1583 /* clear all flags for all channels */
1584 for(ChannelIdx = 0u; ChannelIdx < CE_MRU14_CH_NUM; ChannelIdx++)
1585 {
1586 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1587 }
1588 }
1589 }
1590 #endif
1591 #endif
1592
1593 #ifdef CE_MRU15_ENABLED
1594 #if (!defined MRU_IP_SKIP_CE_MRU15_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU15_Int0_IRQHandler)1595 ISR(Mru_Ip_CE_MRU15_Int0_IRQHandler)
1596 {
1597 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU15_INSTANCE];
1598 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU15_ID];
1599 uint8 ChannelIdx;
1600
1601 if(NULL_PTR != State)
1602 {
1603 /* the driver has been initialized */
1604 /* Processing IRQ */
1605 Mru_Ip_IrqHandler(MRU_IP_CE_MRU15_ID, MRU_IP_INT_GROUP_0);
1606 }
1607 else
1608 {
1609 /* the driver has not been initialized */
1610 /* clear all flags for all channels */
1611 for(ChannelIdx = 0u; ChannelIdx < CE_MRU15_CH_NUM; ChannelIdx++)
1612 {
1613 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1614 }
1615 }
1616 }
1617 #endif
1618 #if (!defined MRU_IP_SKIP_CE_MRU15_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU15_Int1_IRQHandler)1619 ISR(Mru_Ip_CE_MRU15_Int1_IRQHandler)
1620 {
1621 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU15_INSTANCE];
1622 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU15_ID];
1623 uint8 ChannelIdx;
1624
1625 if(NULL_PTR != State)
1626 {
1627 /* the driver has been initialized */
1628 /* Processing IRQ */
1629 Mru_Ip_IrqHandler(MRU_IP_CE_MRU15_ID, MRU_IP_INT_GROUP_1);
1630 }
1631 else
1632 {
1633 /* the driver has not been initialized */
1634 /* clear all flags for all channels */
1635 for(ChannelIdx = 0u; ChannelIdx < CE_MRU15_CH_NUM; ChannelIdx++)
1636 {
1637 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1638 }
1639 }
1640 }
1641 #endif
1642 #endif
1643
1644 #ifdef CE_MRU16_ENABLED
1645 #if (!defined MRU_IP_SKIP_CE_MRU16_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU16_Int0_IRQHandler)1646 ISR(Mru_Ip_CE_MRU16_Int0_IRQHandler)
1647 {
1648 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU16_INSTANCE];
1649 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU16_ID];
1650 uint8 ChannelIdx;
1651
1652 if(NULL_PTR != State)
1653 {
1654 /* the driver has been initialized */
1655 /* Processing IRQ */
1656 Mru_Ip_IrqHandler(MRU_IP_CE_MRU16_ID, MRU_IP_INT_GROUP_0);
1657 }
1658 else
1659 {
1660 /* the driver has not been initialized */
1661 /* clear all flags for all channels */
1662 for(ChannelIdx = 0u; ChannelIdx < CE_MRU16_CH_NUM; ChannelIdx++)
1663 {
1664 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1665 }
1666 }
1667 }
1668 #endif
1669 #if (!defined MRU_IP_SKIP_CE_MRU16_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU16_Int1_IRQHandler)1670 ISR(Mru_Ip_CE_MRU16_Int1_IRQHandler)
1671 {
1672 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU16_INSTANCE];
1673 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU16_ID];
1674 uint8 ChannelIdx;
1675
1676 if(NULL_PTR != State)
1677 {
1678 /* the driver has been initialized */
1679 /* Processing IRQ */
1680 Mru_Ip_IrqHandler(MRU_IP_CE_MRU16_ID, MRU_IP_INT_GROUP_1);
1681 }
1682 else
1683 {
1684 /* the driver has not been initialized */
1685 /* clear all flags for all channels */
1686 for(ChannelIdx = 0u; ChannelIdx < CE_MRU16_CH_NUM; ChannelIdx++)
1687 {
1688 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1689 }
1690 }
1691 }
1692 #endif
1693 #endif
1694
1695 #ifdef CE_MRU17_ENABLED
1696 #if (!defined MRU_IP_SKIP_CE_MRU17_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU17_Int0_IRQHandler)1697 ISR(Mru_Ip_CE_MRU17_Int0_IRQHandler)
1698 {
1699 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU17_INSTANCE];
1700 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU17_ID];
1701 uint8 ChannelIdx;
1702
1703 if(NULL_PTR != State)
1704 {
1705 /* the driver has been initialized */
1706 /* Processing IRQ */
1707 Mru_Ip_IrqHandler(MRU_IP_CE_MRU17_ID, MRU_IP_INT_GROUP_0);
1708 }
1709 else
1710 {
1711 /* the driver has not been initialized */
1712 /* clear all flags for all channels */
1713 for(ChannelIdx = 0u; ChannelIdx < CE_MRU17_CH_NUM; ChannelIdx++)
1714 {
1715 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1716 }
1717 }
1718 }
1719 #endif
1720 #if (!defined MRU_IP_SKIP_CE_MRU17_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU17_Int1_IRQHandler)1721 ISR(Mru_Ip_CE_MRU17_Int1_IRQHandler)
1722 {
1723 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU17_INSTANCE];
1724 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU17_ID];
1725 uint8 ChannelIdx;
1726
1727 if(NULL_PTR != State)
1728 {
1729 /* the driver has been initialized */
1730 /* Processing IRQ */
1731 Mru_Ip_IrqHandler(MRU_IP_CE_MRU17_ID, MRU_IP_INT_GROUP_1);
1732 }
1733 else
1734 {
1735 /* the driver has not been initialized */
1736 /* clear all flags for all channels */
1737 for(ChannelIdx = 0u; ChannelIdx < CE_MRU17_CH_NUM; ChannelIdx++)
1738 {
1739 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1740 }
1741 }
1742 }
1743 #endif
1744 #endif
1745
1746 #ifdef CE_MRU18_ENABLED
1747 #if (!defined MRU_IP_SKIP_CE_MRU18_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU18_Int0_IRQHandler)1748 ISR(Mru_Ip_CE_MRU18_Int0_IRQHandler)
1749 {
1750 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU18_INSTANCE];
1751 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU18_ID];
1752 uint8 ChannelIdx;
1753
1754 if(NULL_PTR != State)
1755 {
1756 /* the driver has been initialized */
1757 /* Processing IRQ */
1758 Mru_Ip_IrqHandler(MRU_IP_CE_MRU18_ID, MRU_IP_INT_GROUP_0);
1759 }
1760 else
1761 {
1762 /* the driver has not been initialized */
1763 /* clear all flags for all channels */
1764 for(ChannelIdx = 0u; ChannelIdx < CE_MRU18_CH_NUM; ChannelIdx++)
1765 {
1766 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1767 }
1768 }
1769 }
1770 #endif
1771 #if (!defined MRU_IP_SKIP_CE_MRU18_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU18_Int1_IRQHandler)1772 ISR(Mru_Ip_CE_MRU18_Int1_IRQHandler)
1773 {
1774 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU18_INSTANCE];
1775 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU18_ID];
1776 uint8 ChannelIdx;
1777
1778 if(NULL_PTR != State)
1779 {
1780 /* the driver has been initialized */
1781 /* Processing IRQ */
1782 Mru_Ip_IrqHandler(MRU_IP_CE_MRU18_ID, MRU_IP_INT_GROUP_1);
1783 }
1784 else
1785 {
1786 /* the driver has not been initialized */
1787 /* clear all flags for all channels */
1788 for(ChannelIdx = 0u; ChannelIdx < CE_MRU18_CH_NUM; ChannelIdx++)
1789 {
1790 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1791 }
1792 }
1793 }
1794 #endif
1795 #endif
1796
1797 #ifdef CE_MRU19_ENABLED
1798 #if (!defined MRU_IP_SKIP_CE_MRU19_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU19_Int0_IRQHandler)1799 ISR(Mru_Ip_CE_MRU19_Int0_IRQHandler)
1800 {
1801 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU19_INSTANCE];
1802 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU19_ID];
1803 uint8 ChannelIdx;
1804
1805 if(NULL_PTR != State)
1806 {
1807 /* the driver has been initialized */
1808 /* Processing IRQ */
1809 Mru_Ip_IrqHandler(MRU_IP_CE_MRU19_ID, MRU_IP_INT_GROUP_0);
1810 }
1811 else
1812 {
1813 /* the driver has not been initialized */
1814 /* clear all flags for all channels */
1815 for(ChannelIdx = 0u; ChannelIdx < CE_MRU19_CH_NUM; ChannelIdx++)
1816 {
1817 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1818 }
1819 }
1820 }
1821 #endif
1822 #if (!defined MRU_IP_SKIP_CE_MRU19_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU19_Int1_IRQHandler)1823 ISR(Mru_Ip_CE_MRU19_Int1_IRQHandler)
1824 {
1825 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU19_INSTANCE];
1826 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU19_ID];
1827 uint8 ChannelIdx;
1828
1829 if(NULL_PTR != State)
1830 {
1831 /* the driver has been initialized */
1832 /* Processing IRQ */
1833 Mru_Ip_IrqHandler(MRU_IP_CE_MRU19_ID, MRU_IP_INT_GROUP_1);
1834 }
1835 else
1836 {
1837 /* the driver has not been initialized */
1838 /* clear all flags for all channels */
1839 for(ChannelIdx = 0u; ChannelIdx < CE_MRU19_CH_NUM; ChannelIdx++)
1840 {
1841 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1842 }
1843 }
1844 }
1845 #endif
1846 #endif
1847
1848 #if ((defined CE_MRU6_ENABLED && (!defined MRU_IP_SKIP_CE_MRU6_INT0_HANDLER)) || (defined CE_MRU7_ENABLED && (!defined MRU_IP_SKIP_CE_MRU7_INT0_HANDLER)) || (defined CE_MRU8_ENABLED && (!defined MRU_IP_SKIP_CE_MRU8_INT0_HANDLER)) || \
1849 (defined CE_MRU9_ENABLED && (!defined MRU_IP_SKIP_CE_MRU9_INT0_HANDLER)) || (defined CE_MRU10_ENABLED && (!defined MRU_IP_SKIP_CE_MRU10_INT0_HANDLER)) || (defined CE_MRU11_ENABLED && (!defined MRU_IP_SKIP_CE_MRU11_INT0_HANDLER)))
ISR(Mru_Ip_CE_MRU6_TO_MRU11_Int0_IRQHandler)1850 ISR(Mru_Ip_CE_MRU6_TO_MRU11_Int0_IRQHandler)
1851 {
1852 #if defined CE_MRU6_ENABLED
1853 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU6_ID];
1854 #elif defined CE_MRU7_ENABLED
1855 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU7_ID];
1856 #elif defined CE_MRU8_ENABLED
1857 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU8_ID];
1858 #elif defined CE_MRU9_ENABLED
1859 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU9_ID];
1860 #elif defined CE_MRU10_ENABLED
1861 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU10_ID];
1862 #elif defined CE_MRU11_ENABLED
1863 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU11_ID];
1864 #endif
1865 uint8 ChannelIdx;
1866
1867 if(NULL_PTR != State)
1868 {
1869 /* the driver has been initialized */
1870 /* Processing IRQ */
1871 #if defined CE_MRU6_ENABLED
1872 Mru_Ip_IrqHandler(MRU_IP_CE_MRU6_ID, MRU_IP_INT_GROUP_0);
1873 #endif
1874 #if defined CE_MRU7_ENABLED
1875 Mru_Ip_IrqHandler(MRU_IP_CE_MRU7_ID, MRU_IP_INT_GROUP_0);
1876 #endif
1877 #if defined CE_MRU8_ENABLED
1878 Mru_Ip_IrqHandler(MRU_IP_CE_MRU8_ID, MRU_IP_INT_GROUP_0);
1879 #endif
1880 #if defined CE_MRU9_ENABLED
1881 Mru_Ip_IrqHandler(MRU_IP_CE_MRU9_ID, MRU_IP_INT_GROUP_0);
1882 #endif
1883 #if defined CE_MRU10_ENABLED
1884 Mru_Ip_IrqHandler(MRU_IP_CE_MRU10_ID, MRU_IP_INT_GROUP_0);
1885 #endif
1886 #if defined CE_MRU11_ENABLED
1887 Mru_Ip_IrqHandler(MRU_IP_CE_MRU11_ID, MRU_IP_INT_GROUP_0);
1888 #endif
1889 }
1890 else
1891 {
1892 /* the driver has not been initialized */
1893 /* clear all flags for all channels */
1894 for(ChannelIdx = 0u; ChannelIdx < CE_MRU_CHXCONFIG_COUNT; ChannelIdx++)
1895 {
1896 #if defined CE_MRU6_ENABLED
1897 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU6_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1898 #endif
1899 #if defined CE_MRU7_ENABLED
1900 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU7_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1901 #endif
1902 #if defined CE_MRU8_ENABLED
1903 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU8_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1904 #endif
1905 #if defined CE_MRU9_ENABLED
1906 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU9_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1907 #endif
1908 #if defined CE_MRU10_ENABLED
1909 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU10_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1910 #endif
1911 #if defined CE_MRU11_ENABLED
1912 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU11_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1913 #endif
1914 }
1915 }
1916 }
1917 #endif
1918 #if ((defined CE_MRU6_ENABLED && (!defined MRU_IP_SKIP_CE_MRU6_INT1_HANDLER)) || (defined CE_MRU7_ENABLED && (!defined MRU_IP_SKIP_CE_MRU7_INT1_HANDLER)) || (defined CE_MRU8_ENABLED && (!defined MRU_IP_SKIP_CE_MRU8_INT1_HANDLER)) || \
1919 (defined CE_MRU9_ENABLED && (!defined MRU_IP_SKIP_CE_MRU9_INT1_HANDLER)) || (defined CE_MRU10_ENABLED && (!defined MRU_IP_SKIP_CE_MRU10_INT1_HANDLER)) || (defined CE_MRU11_ENABLED && (!defined MRU_IP_SKIP_CE_MRU11_INT1_HANDLER)))
ISR(Mru_Ip_CE_MRU6_TO_MRU11_Int1_IRQHandler)1920 ISR(Mru_Ip_CE_MRU6_TO_MRU11_Int1_IRQHandler)
1921 {
1922 #if defined CE_MRU6_ENABLED
1923 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU6_ID];
1924 #elif defined CE_MRU7_ENABLED
1925 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU7_ID];
1926 #elif defined CE_MRU8_ENABLED
1927 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU8_ID];
1928 #elif defined CE_MRU9_ENABLED
1929 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU9_ID];
1930 #elif defined CE_MRU10_ENABLED
1931 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU10_ID];
1932 #elif defined CE_MRU11_ENABLED
1933 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU11_ID];
1934 #endif
1935 uint8 ChannelIdx;
1936
1937 if(NULL_PTR != State)
1938 {
1939 /* the driver has been initialized */
1940 /* Processing IRQ */
1941 #if defined CE_MRU6_ENABLED
1942 Mru_Ip_IrqHandler(MRU_IP_CE_MRU6_ID, MRU_IP_INT_GROUP_1);
1943 #endif
1944 #if defined CE_MRU7_ENABLED
1945 Mru_Ip_IrqHandler(MRU_IP_CE_MRU7_ID, MRU_IP_INT_GROUP_1);
1946 #endif
1947 #if defined CE_MRU8_ENABLED
1948 Mru_Ip_IrqHandler(MRU_IP_CE_MRU8_ID, MRU_IP_INT_GROUP_1);
1949 #endif
1950 #if defined CE_MRU9_ENABLED
1951 Mru_Ip_IrqHandler(MRU_IP_CE_MRU9_ID, MRU_IP_INT_GROUP_1);
1952 #endif
1953 #if defined CE_MRU10_ENABLED
1954 Mru_Ip_IrqHandler(MRU_IP_CE_MRU10_ID, MRU_IP_INT_GROUP_1);
1955 #endif
1956 #if defined CE_MRU11_ENABLED
1957 Mru_Ip_IrqHandler(MRU_IP_CE_MRU11_ID, MRU_IP_INT_GROUP_1);
1958 #endif
1959 }
1960 else
1961 {
1962 /* the driver has not been initialized */
1963 /* clear all flags for all channels */
1964 for(ChannelIdx = 0u; ChannelIdx < CE_MRU_CHXCONFIG_COUNT; ChannelIdx++)
1965 {
1966 #if defined CE_MRU6_ENABLED
1967 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU6_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1968 #endif
1969 #if defined CE_MRU7_ENABLED
1970 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU7_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1971 #endif
1972 #if defined CE_MRU8_ENABLED
1973 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU8_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1974 #endif
1975 #if defined CE_MRU9_ENABLED
1976 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU9_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1977 #endif
1978 #if defined CE_MRU10_ENABLED
1979 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU10_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1980 #endif
1981 #if defined CE_MRU11_ENABLED
1982 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU11_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1983 #endif
1984 }
1985 }
1986 }
1987 #endif
1988
1989 #define PLATFORM_STOP_SEC_CODE
1990 #include "Platform_MemMap.h"
1991
1992 #endif /* PLATFORM_IP_ENABLE_MRU == STD_ON)*/
1993 #endif /* PLATFORM_IP_ENABLE_MRU */
1994
1995 #ifdef __cplusplus
1996 }
1997 #endif
1998
1999 /** @} */
2000
2001
2002
2003
