1 /*
2 ** ###################################################################
3 **     Version:             rev. 1.0, 2015-09-23
4 **     Build:               b210913
5 **
6 **     Abstract:
7 **         Chip specific module features.
8 **
9 **     Copyright 2016 Freescale Semiconductor, Inc.
10 **     Copyright 2016-2021 NXP
11 **     All rights reserved.
12 **
13 **     SPDX-License-Identifier: BSD-3-Clause
14 **
15 **     http:                 www.nxp.com
16 **     mail:                 support@nxp.com
17 **
18 **     Revisions:
19 **     - rev. 1.0 (2015-09-23)
20 **         Initial version.
21 **
22 ** ###################################################################
23 */
24 
25 #ifndef _MKW21Z4_FEATURES_H_
26 #define _MKW21Z4_FEATURES_H_
27 
28 /* SOC module features */
29 
30 /* @brief ADC16 availability on the SoC. */
31 #define FSL_FEATURE_SOC_ADC16_COUNT (1)
32 /* @brief CMP availability on the SoC. */
33 #define FSL_FEATURE_SOC_CMP_COUNT (1)
34 /* @brief CMT availability on the SoC. */
35 #define FSL_FEATURE_SOC_CMT_COUNT (1)
36 /* @brief DAC availability on the SoC. */
37 #define FSL_FEATURE_SOC_DAC_COUNT (1)
38 /* @brief DCDC availability on the SoC. */
39 #define FSL_FEATURE_SOC_DCDC_COUNT (1)
40 /* @brief EDMA availability on the SoC. */
41 #define FSL_FEATURE_SOC_EDMA_COUNT (1)
42 /* @brief DMAMUX availability on the SoC. */
43 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
44 /* @brief DSPI availability on the SoC. */
45 #define FSL_FEATURE_SOC_DSPI_COUNT (2)
46 /* @brief FGPIO availability on the SoC. */
47 #define FSL_FEATURE_SOC_FGPIO_COUNT (3)
48 /* @brief FTFA availability on the SoC. */
49 #define FSL_FEATURE_SOC_FTFA_COUNT (1)
50 /* @brief GPIO availability on the SoC. */
51 #define FSL_FEATURE_SOC_GPIO_COUNT (3)
52 /* @brief I2C availability on the SoC. */
53 #define FSL_FEATURE_SOC_I2C_COUNT (2)
54 /* @brief LLWU availability on the SoC. */
55 #define FSL_FEATURE_SOC_LLWU_COUNT (1)
56 /* @brief LPTMR availability on the SoC. */
57 #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
58 /* @brief LPUART availability on the SoC. */
59 #define FSL_FEATURE_SOC_LPUART_COUNT (1)
60 /* @brief LTC availability on the SoC. */
61 #define FSL_FEATURE_SOC_LTC_COUNT (1)
62 /* @brief MCG availability on the SoC. */
63 #define FSL_FEATURE_SOC_MCG_COUNT (1)
64 /* @brief MCM availability on the SoC. */
65 #define FSL_FEATURE_SOC_MCM_COUNT (1)
66 /* @brief MTB availability on the SoC. */
67 #define FSL_FEATURE_SOC_MTB_COUNT (1)
68 /* @brief MTBDWT availability on the SoC. */
69 #define FSL_FEATURE_SOC_MTBDWT_COUNT (1)
70 /* @brief PIT availability on the SoC. */
71 #define FSL_FEATURE_SOC_PIT_COUNT (1)
72 /* @brief PMC availability on the SoC. */
73 #define FSL_FEATURE_SOC_PMC_COUNT (1)
74 /* @brief PORT availability on the SoC. */
75 #define FSL_FEATURE_SOC_PORT_COUNT (3)
76 /* @brief RCM availability on the SoC. */
77 #define FSL_FEATURE_SOC_RCM_COUNT (1)
78 /* @brief RFSYS availability on the SoC. */
79 #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
80 /* @brief ROM availability on the SoC. */
81 #define FSL_FEATURE_SOC_ROM_COUNT (1)
82 /* @brief RSIM availability on the SoC. */
83 #define FSL_FEATURE_SOC_RSIM_COUNT (1)
84 /* @brief RTC availability on the SoC. */
85 #define FSL_FEATURE_SOC_RTC_COUNT (1)
86 /* @brief SIM availability on the SoC. */
87 #define FSL_FEATURE_SOC_SIM_COUNT (1)
88 /* @brief SMC availability on the SoC. */
89 #define FSL_FEATURE_SOC_SMC_COUNT (1)
90 /* @brief TPM availability on the SoC. */
91 #define FSL_FEATURE_SOC_TPM_COUNT (3)
92 /* @brief TRNG availability on the SoC. */
93 #define FSL_FEATURE_SOC_TRNG_COUNT (1)
94 /* @brief TSI availability on the SoC. */
95 #define FSL_FEATURE_SOC_TSI_COUNT (1)
96 /* @brief VREF availability on the SoC. */
97 #define FSL_FEATURE_SOC_VREF_COUNT (1)
98 /* @brief XCVR availability on the SoC. */
99 #define FSL_FEATURE_SOC_XCVR_COUNT (1)
100 /* @brief ZLL availability on the SoC. */
101 #define FSL_FEATURE_SOC_ZLL_COUNT (1)
102 
103 /* ADC16 module features */
104 
105 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
106 #define FSL_FEATURE_ADC16_HAS_PGA (0)
107 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
108 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
109 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
110 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
111 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
112 #define FSL_FEATURE_ADC16_HAS_DMA (1)
113 /* @brief Has differential mode (bitfield SC1x[DIFF]). */
114 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
115 /* @brief Has FIFO (bit SC4[AFDEP]). */
116 #define FSL_FEATURE_ADC16_HAS_FIFO (0)
117 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */
118 #define FSL_FEATURE_ADC16_FIFO_SIZE (0)
119 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
120 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
121 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
122 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
123 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
124 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
125 /* @brief Has HW averaging (bit SC3[AVGE]). */
126 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
127 /* @brief Has offset correction (register OFS). */
128 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
129 /* @brief Maximum ADC resolution. */
130 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
131 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
132 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
133 
134 /* CMP module features */
135 
136 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
137 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1)
138 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */
139 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0)
140 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
141 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0)
142 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
143 #define FSL_FEATURE_CMP_HAS_DMA (1)
144 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
145 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0)
146 /* @brief Has DAC Test function in CMP (register DACTEST). */
147 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
148 
149 /* COP module features */
150 
151 /* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */
152 #define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1)
153 /* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */
154 #define FSL_FEATURE_COP_HAS_STOP_ENABLE (1)
155 /* @brief Has more clock sources like MCGIRC */
156 #define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1)
157 /* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */
158 #define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1)
159 
160 /* DAC module features */
161 
162 /* @brief Define the size of hardware buffer */
163 #define FSL_FEATURE_DAC_BUFFER_SIZE (2)
164 /* @brief Define whether the buffer supports watermark event detection or not. */
165 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
166 /* @brief Define whether the buffer supports watermark selection detection or not. */
167 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
168 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
169 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
170 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
171 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
172 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
173 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
174 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
175 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
176 /* @brief Define whether FIFO buffer mode is available or not. */
177 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0)
178 /* @brief Define whether swing buffer mode is available or not.. */
179 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0)
180 
181 /* DCDC module features */
182 
183 /* @brief Has VDD1P5 bits in DCDC REG3. */
184 #define FSL_FEATURE_DCDC_REG3_HAS_VDD1P5_BITS (1)
185 /* @brief Has VDD1P45 bits in DCDC REG3. */
186 #define FSL_FEATURE_DCDC_REG3_HAS_VDD1P45_BITS (0)
187 /* @brief Has BOOST mode: at least one of the bits DCDC_REG1[POSLIMIT_BOOST_IN], DCDC_REG3[DCDC_VDD1P45CTRL_TRG_BOOST] or DCDC_REG3[DCDC_VDD1P5CTRL_TRG_BOOST]. */
188 #define FSL_FEATURE_DCDC_HAS_BOOST_MODE (1)
189 
190 /* EDMA module features */
191 
192 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
193 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (4)
194 /* @brief Total number of DMA channels on all modules. */
195 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (4)
196 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
197 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
198 /* @brief Has DMA_Error interrupt vector. */
199 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0)
200 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
201 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4)
202 /* @brief Channel IRQ entry shared offset. */
203 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (0)
204 /* @brief If 8 bytes transfer supported. */
205 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (0)
206 /* @brief If 16 bytes transfer supported. */
207 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1)
208 
209 /* DMAMUX module features */
210 
211 /* @brief Number of DMA channels (related to number of register CHCFGn). */
212 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4)
213 /* @brief Total number of DMA channels on all modules. */
214 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (4)
215 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
216 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
217 /* @brief Register CHCFGn width. */
218 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8)
219 
220 /* FGPIO module features */
221 
222 /* No feature definitions */
223 
224 /* FLASH module features */
225 
226 #if defined(CPU_MKW21Z256VHT4)
227     /* @brief Is of type FTFA. */
228     #define FSL_FEATURE_FLASH_IS_FTFA (1)
229     /* @brief Is of type FTFE. */
230     #define FSL_FEATURE_FLASH_IS_FTFE (0)
231     /* @brief Is of type FTFL. */
232     #define FSL_FEATURE_FLASH_IS_FTFL (0)
233     /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
234     #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
235     /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
236     #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
237     /* @brief Has EEPROM region protection (register FEPROT). */
238     #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
239     /* @brief Has data flash region protection (register FDPROT). */
240     #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
241     /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
242     #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1)
243     /* @brief Has flash cache control in FMC module. */
244     #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
245     /* @brief Has flash cache control in MCM module. */
246     #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
247     /* @brief Has flash cache control in MSCM module. */
248     #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
249     /* @brief Has prefetch speculation control in flash, such as kv5x. */
250     #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
251     /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
252     #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
253     /* @brief P-Flash start address. */
254     #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
255     /* @brief P-Flash block count. */
256     #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
257     /* @brief P-Flash block size. */
258     #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072)
259     /* @brief P-Flash sector size. */
260     #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048)
261     /* @brief P-Flash write unit size. */
262     #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
263     /* @brief P-Flash data path width. */
264     #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8)
265     /* @brief P-Flash block swap feature. */
266     #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
267     /* @brief P-Flash protection region count. */
268     #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
269     /* @brief Has FlexNVM memory. */
270     #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
271     /* @brief Has FlexNVM alias. */
272     #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0)
273     /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
274     #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
275     /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */
276     #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000)
277     /* @brief FlexNVM block count. */
278     #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
279     /* @brief FlexNVM block size. */
280     #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
281     /* @brief FlexNVM sector size. */
282     #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
283     /* @brief FlexNVM write unit size. */
284     #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
285     /* @brief FlexNVM data path width. */
286     #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
287     /* @brief Has FlexRAM memory. */
288     #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
289     /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
290     #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
291     /* @brief FlexRAM size. */
292     #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
293     /* @brief Has 0x00 Read 1s Block command. */
294     #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
295     /* @brief Has 0x01 Read 1s Section command. */
296     #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
297     /* @brief Has 0x02 Program Check command. */
298     #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
299     /* @brief Has 0x03 Read Resource command. */
300     #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
301     /* @brief Has 0x06 Program Longword command. */
302     #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
303     /* @brief Has 0x07 Program Phrase command. */
304     #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
305     /* @brief Has 0x08 Erase Flash Block command. */
306     #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
307     /* @brief Has 0x09 Erase Flash Sector command. */
308     #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
309     /* @brief Has 0x0B Program Section command. */
310     #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
311     /* @brief Has 0x40 Read 1s All Blocks command. */
312     #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
313     /* @brief Has 0x41 Read Once command. */
314     #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
315     /* @brief Has 0x43 Program Once command. */
316     #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
317     /* @brief Has 0x44 Erase All Blocks command. */
318     #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
319     /* @brief Has 0x45 Verify Backdoor Access Key command. */
320     #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
321     /* @brief Has 0x46 Swap Control command. */
322     #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
323     /* @brief Has 0x49 Erase All Blocks Unsecure command. */
324     #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
325     /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
326     #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
327     /* @brief Has 0x4B Erase All Execute-only Segments command. */
328     #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
329     /* @brief Has 0x80 Program Partition command. */
330     #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
331     /* @brief Has 0x81 Set FlexRAM Function command. */
332     #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
333     /* @brief P-Flash Erase/Read 1st all block command address alignment. */
334     #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
335     /* @brief P-Flash Erase sector command address alignment. */
336     #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8)
337     /* @brief P-Flash Rrogram/Verify section command address alignment. */
338     #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8)
339     /* @brief P-Flash Read resource command address alignment. */
340     #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
341     /* @brief P-Flash Program check command address alignment. */
342     #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
343     /* @brief P-Flash Program check command address alignment. */
344     #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
345     /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
346     #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
347     /* @brief FlexNVM Erase sector command address alignment. */
348     #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
349     /* @brief FlexNVM Rrogram/Verify section command address alignment. */
350     #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
351     /* @brief FlexNVM Read resource command address alignment. */
352     #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
353     /* @brief FlexNVM Program check command address alignment. */
354     #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
355     /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
356     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU)
357     /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
358     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU)
359     /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
360     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU)
361     /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
362     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU)
363     /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
364     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU)
365     /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
366     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU)
367     /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
368     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU)
369     /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
370     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU)
371     /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
372     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU)
373     /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
374     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU)
375     /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
376     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU)
377     /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
378     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU)
379     /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
380     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU)
381     /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
382     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU)
383     /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
384     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU)
385     /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
386     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU)
387     /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
388     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
389     /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
390     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
391     /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
392     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
393     /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
394     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
395     /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
396     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
397     /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
398     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
399     /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
400     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
401     /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
402     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
403     /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
404     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
405     /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
406     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
407     /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
408     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
409     /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
410     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
411     /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
412     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
413     /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
414     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
415     /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
416     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
417     /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
418     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
419 #elif defined(CPU_MKW21Z512VHT4)
420     /* @brief Is of type FTFA. */
421     #define FSL_FEATURE_FLASH_IS_FTFA (1)
422     /* @brief Is of type FTFE. */
423     #define FSL_FEATURE_FLASH_IS_FTFE (0)
424     /* @brief Is of type FTFL. */
425     #define FSL_FEATURE_FLASH_IS_FTFL (0)
426     /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
427     #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
428     /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
429     #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
430     /* @brief Has EEPROM region protection (register FEPROT). */
431     #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
432     /* @brief Has data flash region protection (register FDPROT). */
433     #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
434     /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
435     #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1)
436     /* @brief Has flash cache control in FMC module. */
437     #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
438     /* @brief Has flash cache control in MCM module. */
439     #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
440     /* @brief Has flash cache control in MSCM module. */
441     #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
442     /* @brief Has prefetch speculation control in flash, such as kv5x. */
443     #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
444     /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
445     #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
446     /* @brief P-Flash start address. */
447     #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
448     /* @brief P-Flash block count. */
449     #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
450     /* @brief P-Flash block size. */
451     #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144)
452     /* @brief P-Flash sector size. */
453     #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048)
454     /* @brief P-Flash write unit size. */
455     #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
456     /* @brief P-Flash data path width. */
457     #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8)
458     /* @brief P-Flash block swap feature. */
459     #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
460     /* @brief P-Flash protection region count. */
461     #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
462     /* @brief Has FlexNVM memory. */
463     #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
464     /* @brief Has FlexNVM alias. */
465     #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0)
466     /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
467     #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
468     /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */
469     #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000)
470     /* @brief FlexNVM block count. */
471     #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
472     /* @brief FlexNVM block size. */
473     #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
474     /* @brief FlexNVM sector size. */
475     #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
476     /* @brief FlexNVM write unit size. */
477     #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
478     /* @brief FlexNVM data path width. */
479     #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
480     /* @brief Has FlexRAM memory. */
481     #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
482     /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
483     #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
484     /* @brief FlexRAM size. */
485     #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
486     /* @brief Has 0x00 Read 1s Block command. */
487     #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
488     /* @brief Has 0x01 Read 1s Section command. */
489     #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
490     /* @brief Has 0x02 Program Check command. */
491     #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
492     /* @brief Has 0x03 Read Resource command. */
493     #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
494     /* @brief Has 0x06 Program Longword command. */
495     #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
496     /* @brief Has 0x07 Program Phrase command. */
497     #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
498     /* @brief Has 0x08 Erase Flash Block command. */
499     #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
500     /* @brief Has 0x09 Erase Flash Sector command. */
501     #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
502     /* @brief Has 0x0B Program Section command. */
503     #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
504     /* @brief Has 0x40 Read 1s All Blocks command. */
505     #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
506     /* @brief Has 0x41 Read Once command. */
507     #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
508     /* @brief Has 0x43 Program Once command. */
509     #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
510     /* @brief Has 0x44 Erase All Blocks command. */
511     #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
512     /* @brief Has 0x45 Verify Backdoor Access Key command. */
513     #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
514     /* @brief Has 0x46 Swap Control command. */
515     #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
516     /* @brief Has 0x49 Erase All Blocks Unsecure command. */
517     #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
518     /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
519     #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
520     /* @brief Has 0x4B Erase All Execute-only Segments command. */
521     #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
522     /* @brief Has 0x80 Program Partition command. */
523     #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
524     /* @brief Has 0x81 Set FlexRAM Function command. */
525     #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
526     /* @brief P-Flash Erase/Read 1st all block command address alignment. */
527     #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
528     /* @brief P-Flash Erase sector command address alignment. */
529     #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8)
530     /* @brief P-Flash Rrogram/Verify section command address alignment. */
531     #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8)
532     /* @brief P-Flash Read resource command address alignment. */
533     #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
534     /* @brief P-Flash Program check command address alignment. */
535     #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
536     /* @brief P-Flash Program check command address alignment. */
537     #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
538     /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
539     #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
540     /* @brief FlexNVM Erase sector command address alignment. */
541     #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
542     /* @brief FlexNVM Rrogram/Verify section command address alignment. */
543     #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
544     /* @brief FlexNVM Read resource command address alignment. */
545     #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
546     /* @brief FlexNVM Program check command address alignment. */
547     #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
548     /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
549     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU)
550     /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
551     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU)
552     /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
553     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU)
554     /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
555     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU)
556     /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
557     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU)
558     /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
559     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU)
560     /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
561     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU)
562     /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
563     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU)
564     /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
565     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU)
566     /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
567     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU)
568     /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
569     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU)
570     /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
571     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU)
572     /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
573     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU)
574     /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
575     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU)
576     /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
577     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU)
578     /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
579     #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU)
580     /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
581     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
582     /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
583     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
584     /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
585     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
586     /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
587     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
588     /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
589     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
590     /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
591     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
592     /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
593     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
594     /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
595     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
596     /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
597     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
598     /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
599     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
600     /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
601     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
602     /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
603     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
604     /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
605     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
606     /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
607     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
608     /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
609     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
610     /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
611     #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
612 #endif /* defined(CPU_MKW21Z256VHT4) */
613 
614 /* GENFSK module features */
615 
616 /* No feature definitions */
617 
618 /* GPIO module features */
619 
620 /* @brief Has GPIO attribute checker register (GACR). */
621 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0)
622 
623 /* I2C module features */
624 
625 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
626 #define FSL_FEATURE_I2C_HAS_SMBUS (1)
627 /* @brief Maximum supported baud rate in kilobit per second. */
628 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
629 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
630 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
631 /* @brief Has DMA support (register bit C1[DMAEN]). */
632 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
633 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
634 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
635 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
636 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
637 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
638 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
639 /* @brief Maximum width of the glitch filter in number of bus clocks. */
640 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
641 /* @brief Has control of the drive capability of the I2C pins. */
642 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
643 /* @brief Has double buffering support (register S2). */
644 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1)
645 /* @brief Has double buffer enable. */
646 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (1)
647 
648 /* LLWU module features */
649 
650 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
651 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
652 /* @brief Has pins 8-15 connected to LLWU device. */
653 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
654 /* @brief Maximum number of internal modules connected to LLWU device. */
655 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
656 /* @brief Number of digital filters. */
657 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
658 /* @brief Has MF register. */
659 #define FSL_FEATURE_LLWU_HAS_MF (0)
660 /* @brief Has PF register. */
661 #define FSL_FEATURE_LLWU_HAS_PF (0)
662 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
663 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
664 /* @brief Has no internal module wakeup flag register. */
665 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
666 /* @brief Has external pin 0 connected to LLWU device. */
667 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
668 /* @brief Index of port of external pin. */
669 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX)
670 /* @brief Number of external pin port on specified port. */
671 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16)
672 /* @brief Has external pin 1 connected to LLWU device. */
673 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
674 /* @brief Index of port of external pin. */
675 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX)
676 /* @brief Number of external pin port on specified port. */
677 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17)
678 /* @brief Has external pin 2 connected to LLWU device. */
679 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
680 /* @brief Index of port of external pin. */
681 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX)
682 /* @brief Number of external pin port on specified port. */
683 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18)
684 /* @brief Has external pin 3 connected to LLWU device. */
685 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
686 /* @brief Index of port of external pin. */
687 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX)
688 /* @brief Number of external pin port on specified port. */
689 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19)
690 /* @brief Has external pin 4 connected to LLWU device. */
691 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
692 /* @brief Index of port of external pin. */
693 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
694 /* @brief Number of external pin port on specified port. */
695 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16)
696 /* @brief Has external pin 5 connected to LLWU device. */
697 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
698 /* @brief Index of port of external pin. */
699 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX)
700 /* @brief Number of external pin port on specified port. */
701 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17)
702 /* @brief Has external pin 6 connected to LLWU device. */
703 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
704 /* @brief Index of port of external pin. */
705 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX)
706 /* @brief Number of external pin port on specified port. */
707 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18)
708 /* @brief Has external pin 7 connected to LLWU device. */
709 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
710 /* @brief Index of port of external pin. */
711 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX)
712 /* @brief Number of external pin port on specified port. */
713 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19)
714 /* @brief Has external pin 8 connected to LLWU device. */
715 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
716 /* @brief Index of port of external pin. */
717 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX)
718 /* @brief Number of external pin port on specified port. */
719 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0)
720 /* @brief Has external pin 9 connected to LLWU device. */
721 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (0)
722 /* @brief Index of port of external pin. */
723 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (0)
724 /* @brief Number of external pin port on specified port. */
725 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0)
726 /* @brief Has external pin 10 connected to LLWU device. */
727 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
728 /* @brief Index of port of external pin. */
729 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
730 /* @brief Number of external pin port on specified port. */
731 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2)
732 /* @brief Has external pin 11 connected to LLWU device. */
733 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
734 /* @brief Index of port of external pin. */
735 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
736 /* @brief Number of external pin port on specified port. */
737 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3)
738 /* @brief Has external pin 12 connected to LLWU device. */
739 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
740 /* @brief Index of port of external pin. */
741 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX)
742 /* @brief Number of external pin port on specified port. */
743 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4)
744 /* @brief Has external pin 13 connected to LLWU device. */
745 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
746 /* @brief Index of port of external pin. */
747 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX)
748 /* @brief Number of external pin port on specified port. */
749 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5)
750 /* @brief Has external pin 14 connected to LLWU device. */
751 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
752 /* @brief Index of port of external pin. */
753 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX)
754 /* @brief Number of external pin port on specified port. */
755 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6)
756 /* @brief Has external pin 15 connected to LLWU device. */
757 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
758 /* @brief Index of port of external pin. */
759 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX)
760 /* @brief Number of external pin port on specified port. */
761 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7)
762 /* @brief Has external pin 16 connected to LLWU device. */
763 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
764 /* @brief Index of port of external pin. */
765 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
766 /* @brief Number of external pin port on specified port. */
767 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
768 /* @brief Has external pin 17 connected to LLWU device. */
769 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
770 /* @brief Index of port of external pin. */
771 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
772 /* @brief Number of external pin port on specified port. */
773 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
774 /* @brief Has external pin 18 connected to LLWU device. */
775 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
776 /* @brief Index of port of external pin. */
777 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
778 /* @brief Number of external pin port on specified port. */
779 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
780 /* @brief Has external pin 19 connected to LLWU device. */
781 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
782 /* @brief Index of port of external pin. */
783 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
784 /* @brief Number of external pin port on specified port. */
785 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
786 /* @brief Has external pin 20 connected to LLWU device. */
787 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
788 /* @brief Index of port of external pin. */
789 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
790 /* @brief Number of external pin port on specified port. */
791 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
792 /* @brief Has external pin 21 connected to LLWU device. */
793 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
794 /* @brief Index of port of external pin. */
795 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
796 /* @brief Number of external pin port on specified port. */
797 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
798 /* @brief Has external pin 22 connected to LLWU device. */
799 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
800 /* @brief Index of port of external pin. */
801 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
802 /* @brief Number of external pin port on specified port. */
803 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
804 /* @brief Has external pin 23 connected to LLWU device. */
805 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
806 /* @brief Index of port of external pin. */
807 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
808 /* @brief Number of external pin port on specified port. */
809 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
810 /* @brief Has external pin 24 connected to LLWU device. */
811 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
812 /* @brief Index of port of external pin. */
813 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
814 /* @brief Number of external pin port on specified port. */
815 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
816 /* @brief Has external pin 25 connected to LLWU device. */
817 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
818 /* @brief Index of port of external pin. */
819 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
820 /* @brief Number of external pin port on specified port. */
821 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
822 /* @brief Has external pin 26 connected to LLWU device. */
823 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
824 /* @brief Index of port of external pin. */
825 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
826 /* @brief Number of external pin port on specified port. */
827 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
828 /* @brief Has external pin 27 connected to LLWU device. */
829 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
830 /* @brief Index of port of external pin. */
831 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
832 /* @brief Number of external pin port on specified port. */
833 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
834 /* @brief Has external pin 28 connected to LLWU device. */
835 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
836 /* @brief Index of port of external pin. */
837 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
838 /* @brief Number of external pin port on specified port. */
839 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
840 /* @brief Has external pin 29 connected to LLWU device. */
841 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
842 /* @brief Index of port of external pin. */
843 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
844 /* @brief Number of external pin port on specified port. */
845 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
846 /* @brief Has external pin 30 connected to LLWU device. */
847 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
848 /* @brief Index of port of external pin. */
849 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
850 /* @brief Number of external pin port on specified port. */
851 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
852 /* @brief Has external pin 31 connected to LLWU device. */
853 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
854 /* @brief Index of port of external pin. */
855 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
856 /* @brief Number of external pin port on specified port. */
857 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
858 /* @brief Has internal module 0 connected to LLWU device. */
859 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
860 /* @brief Has internal module 1 connected to LLWU device. */
861 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
862 /* @brief Has internal module 2 connected to LLWU device. */
863 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
864 /* @brief Has internal module 3 connected to LLWU device. */
865 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
866 /* @brief Has internal module 4 connected to LLWU device. */
867 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
868 /* @brief Has internal module 5 connected to LLWU device. */
869 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
870 /* @brief Has internal module 6 connected to LLWU device. */
871 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
872 /* @brief Has internal module 7 connected to LLWU device. */
873 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
874 /* @brief Has Version ID Register (LLWU_VERID). */
875 #define FSL_FEATURE_LLWU_HAS_VERID (0)
876 /* @brief Has Parameter Register (LLWU_PARAM). */
877 #define FSL_FEATURE_LLWU_HAS_PARAM (0)
878 /* @brief Width of registers of the LLWU. */
879 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
880 /* @brief Has DMA Enable register (LLWU_DE). */
881 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
882 
883 /* LPTMR module features */
884 
885 /* @brief Has shared interrupt handler with another LPTMR module. */
886 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
887 /* @brief Whether LPTMR counter is 32 bits width. */
888 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0)
889 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
890 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0)
891 
892 /* LPUART module features */
893 
894 /* @brief LPUART0 and LPUART1 has shared interrupt vector. */
895 #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0)
896 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
897 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
898 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
899 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
900 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
901 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
902 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
903 #define FSL_FEATURE_LPUART_HAS_FIFO (0)
904 /* @brief Has 32-bit register MODIR */
905 #define FSL_FEATURE_LPUART_HAS_MODIR (1)
906 /* @brief Hardware flow control (RTS, CTS) is supported. */
907 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
908 /* @brief Infrared (modulation) is supported. */
909 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
910 /* @brief 2 bits long stop bit is available. */
911 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
912 /* @brief If 10-bit mode is supported. */
913 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
914 /* @brief If 7-bit mode is supported. */
915 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0)
916 /* @brief Baud rate fine adjustment is available. */
917 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
918 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
919 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
920 /* @brief Baud rate oversampling is available. */
921 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
922 /* @brief Baud rate oversampling is available. */
923 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
924 /* @brief Peripheral type. */
925 #define FSL_FEATURE_LPUART_IS_SCI (1)
926 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
927 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0)
928 /* @brief Supports two match addresses to filter incoming frames. */
929 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
930 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
931 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
932 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
933 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
934 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
935 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
936 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
937 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
938 /* @brief Has improved smart card (ISO7816 protocol) support. */
939 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
940 /* @brief Has local operation network (CEA709.1-B protocol) support. */
941 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
942 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
943 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
944 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
945 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
946 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
947 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
948 /* @brief Has separate DMA RX and TX requests. */
949 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
950 /* @brief Has separate RX and TX interrupts. */
951 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
952 /* @brief Has LPAURT_PARAM. */
953 #define FSL_FEATURE_LPUART_HAS_PARAM (0)
954 /* @brief Has LPUART_VERID. */
955 #define FSL_FEATURE_LPUART_HAS_VERID (0)
956 /* @brief Has LPUART_GLOBAL. */
957 #define FSL_FEATURE_LPUART_HAS_GLOBAL (0)
958 /* @brief Has LPUART_PINCFG. */
959 #define FSL_FEATURE_LPUART_HAS_PINCFG (0)
960 
961 /* LTC module features */
962 
963 /* @brief LTC module supports DES algorithm. */
964 #define FSL_FEATURE_LTC_HAS_DES (0)
965 /* @brief LTC module supports PKHA algorithm. */
966 #define FSL_FEATURE_LTC_HAS_PKHA (0)
967 /* @brief LTC module supports SHA algorithm. */
968 #define FSL_FEATURE_LTC_HAS_SHA (0)
969 /* @brief LTC module supports AES GCM mode. */
970 #define FSL_FEATURE_LTC_HAS_GCM (0)
971 /* @brief LTC module supports DPAMS registers. */
972 #define FSL_FEATURE_LTC_HAS_DPAMS (0)
973 /* @brief LTC module supports AES with 24 bytes key. */
974 #define FSL_FEATURE_LTC_HAS_AES192 (0)
975 /* @brief LTC module supports AES with 32 bytes key. */
976 #define FSL_FEATURE_LTC_HAS_AES256 (0)
977 
978 /* MCG module features */
979 
980 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
981 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0)
982 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
983 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0)
984 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
985 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0)
986 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */
987 #define FSL_FEATURE_MCG_PLL_REF_MIN (0)
988 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */
989 #define FSL_FEATURE_MCG_PLL_REF_MAX (0)
990 /* @brief The PLL clock is divided by 2 before VCO divider. */
991 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0)
992 /* @brief FRDIV supports 1280. */
993 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
994 /* @brief FRDIV supports 1536. */
995 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
996 /* @brief MCGFFCLK divider. */
997 #define FSL_FEATURE_MCG_FFCLK_DIV (1)
998 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
999 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
1000 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
1001 #define FSL_FEATURE_MCG_HAS_RTC_32K (1)
1002 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
1003 #define FSL_FEATURE_MCG_HAS_PLL1 (0)
1004 /* @brief Has 48MHz internal oscillator. */
1005 #define FSL_FEATURE_MCG_HAS_IRC_48M (0)
1006 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
1007 #define FSL_FEATURE_MCG_HAS_OSC1 (0)
1008 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
1009 #define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
1010 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
1011 #define FSL_FEATURE_MCG_HAS_LOLRE (0)
1012 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
1013 #define FSL_FEATURE_MCG_USE_OSCSEL (1)
1014 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
1015 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
1016 /* @brief TBD */
1017 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
1018 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */
1019 #define FSL_FEATURE_MCG_HAS_PLL (0)
1020 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
1021 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (0)
1022 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
1023 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (0)
1024 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
1025 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
1026 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
1027 #define FSL_FEATURE_MCG_HAS_FLL (1)
1028 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
1029 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
1030 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
1031 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
1032 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
1033 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0)
1034 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
1035 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
1036 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
1037 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
1038 /* @brief Has external clock monitor (register bit C6[CME]). */
1039 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
1040 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
1041 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
1042 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
1043 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
1044 /* @brief Has PEI mode or PBI mode. */
1045 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
1046 /* @brief Reset clock mode is BLPI. */
1047 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
1048 
1049 /* interrupt module features */
1050 
1051 /* @brief Lowest interrupt request number. */
1052 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
1053 /* @brief Highest interrupt request number. */
1054 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (31)
1055 
1056 /* PIT module features */
1057 
1058 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
1059 #define FSL_FEATURE_PIT_TIMER_COUNT (2)
1060 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
1061 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
1062 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
1063 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
1064 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
1065 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1)
1066 /* @brief Has timer enable control. */
1067 #define FSL_FEATURE_PIT_HAS_MDIS (1)
1068 
1069 /* PMC module features */
1070 
1071 /* @brief Has Bandgap Enable In VLPx Operation support. */
1072 #define FSL_FEATURE_PMC_HAS_BGEN (0)
1073 /* @brief Has Bandgap Buffer Enable. */
1074 #define FSL_FEATURE_PMC_HAS_BGBE (1)
1075 /* @brief Has Bandgap Buffer Drive Select. */
1076 #define FSL_FEATURE_PMC_HAS_BGBDS (0)
1077 /* @brief Has Low-Voltage Detect Voltage Select support. */
1078 #define FSL_FEATURE_PMC_HAS_LVDV (1)
1079 /* @brief Has Low-Voltage Warning Voltage Select support. */
1080 #define FSL_FEATURE_PMC_HAS_LVWV (1)
1081 /* @brief Has LPO. */
1082 #define FSL_FEATURE_PMC_HAS_LPO (0)
1083 /* @brief Has VLPx option PMC_REGSC[VLPO]. */
1084 #define FSL_FEATURE_PMC_HAS_VLPO (1)
1085 /* @brief Has acknowledge isolation support. */
1086 #define FSL_FEATURE_PMC_HAS_ACKISO (1)
1087 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */
1088 #define FSL_FEATURE_PMC_HAS_REGFPM (0)
1089 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */
1090 #define FSL_FEATURE_PMC_HAS_REGONS (1)
1091 /* @brief Has PMC_HVDSC1. */
1092 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0)
1093 /* @brief Has PMC_PARAM. */
1094 #define FSL_FEATURE_PMC_HAS_PARAM (0)
1095 /* @brief Has PMC_VERID. */
1096 #define FSL_FEATURE_PMC_HAS_VERID (0)
1097 
1098 /* PORT module features */
1099 
1100 /* @brief Has control lock (register bit PCR[LK]). */
1101 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
1102 /* @brief Has open drain control (register bit PCR[ODE]). */
1103 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
1104 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
1105 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
1106 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
1107 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
1108 /* @brief Has pull resistor selection available. */
1109 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
1110 /* @brief Has pull resistor enable (register bit PCR[PE]). */
1111 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
1112 /* @brief Has slew rate control (register bit PCR[SRE]). */
1113 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
1114 /* @brief Has passive filter (register bit field PCR[PFE]). */
1115 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
1116 /* @brief Has drive strength control (register bit PCR[DSE]). */
1117 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
1118 /* @brief Has separate drive strength register (HDRVE). */
1119 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
1120 /* @brief Has glitch filter (register IOFLT). */
1121 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
1122 /* @brief Defines width of PCR[MUX] field. */
1123 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
1124 /* @brief Has dedicated interrupt vector. */
1125 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
1126 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
1127 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0)
1128 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */
1129 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
1130 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
1131 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
1132 
1133 /* RADIO module features */
1134 
1135 /* @brief Zigbee availability. */
1136 #define FSL_FEATURE_RADIO_HAS_ZIGBEE (1)
1137 /* @brief Bluetooth availability. */
1138 #define FSL_FEATURE_RADIO_HAS_BLE (0)
1139 /* @brief ANT availability */
1140 #define FSL_FEATURE_RADIO_HAS_ANT (1)
1141 /* @brief Generic FSK module availability */
1142 #define FSL_FEATURE_RADIO_HAS_GENFSK (1)
1143 /* @brief Major version of the radio submodule */
1144 #define FSL_FEATURE_RADIO_VERSION_MAJOR (2)
1145 /* @brief Minor version of the radio submodule */
1146 #define FSL_FEATURE_RADIO_VERSION_MINOR (0)
1147 
1148 /* RCM module features */
1149 
1150 /* @brief Has Loss-of-Lock Reset support. */
1151 #define FSL_FEATURE_RCM_HAS_LOL (0)
1152 /* @brief Has Loss-of-Clock Reset support. */
1153 #define FSL_FEATURE_RCM_HAS_LOC (1)
1154 /* @brief Has JTAG generated Reset support. */
1155 #define FSL_FEATURE_RCM_HAS_JTAG (0)
1156 /* @brief Has EzPort generated Reset support. */
1157 #define FSL_FEATURE_RCM_HAS_EZPORT (0)
1158 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
1159 #define FSL_FEATURE_RCM_HAS_EZPMS (0)
1160 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
1161 #define FSL_FEATURE_RCM_HAS_BOOTROM (0)
1162 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
1163 #define FSL_FEATURE_RCM_HAS_SSRS (0)
1164 /* @brief Has Version ID Register (RCM_VERID). */
1165 #define FSL_FEATURE_RCM_HAS_VERID (0)
1166 /* @brief Has Parameter Register (RCM_PARAM). */
1167 #define FSL_FEATURE_RCM_HAS_PARAM (0)
1168 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */
1169 #define FSL_FEATURE_RCM_HAS_SRIE (0)
1170 /* @brief Width of registers of the RCM. */
1171 #define FSL_FEATURE_RCM_REG_WIDTH (8)
1172 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */
1173 #define FSL_FEATURE_RCM_HAS_CORE1 (0)
1174 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */
1175 #define FSL_FEATURE_RCM_HAS_MDM_AP (1)
1176 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */
1177 #define FSL_FEATURE_RCM_HAS_WAKEUP (1)
1178 
1179 /* RSIM module features */
1180 
1181 /* No feature definitions */
1182 
1183 /* RTC module features */
1184 
1185 /* @brief Has wakeup pin. */
1186 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
1187 /* @brief Has wakeup pin selection (bit field CR[WPS]). */
1188 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
1189 /* @brief Has low power features (registers MER, MCLR and MCHR). */
1190 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
1191 /* @brief Has read/write access control (registers WAR and RAR). */
1192 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0)
1193 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
1194 #define FSL_FEATURE_RTC_HAS_SECURITY (0)
1195 /* @brief Has RTC_CLKIN available. */
1196 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
1197 /* @brief Has prescaler adjust for LPO. */
1198 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
1199 /* @brief Has Clock Pin Enable field. */
1200 #define FSL_FEATURE_RTC_HAS_CPE (0)
1201 /* @brief Has Timer Seconds Interrupt Configuration field. */
1202 #define FSL_FEATURE_RTC_HAS_TSIC (0)
1203 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
1204 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
1205 /* @brief Has Tamper Interrupt Register (register TIR). */
1206 #define FSL_FEATURE_RTC_HAS_TIR (0)
1207 /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */
1208 #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0)
1209 /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */
1210 #define FSL_FEATURE_RTC_HAS_TIR_SIE (0)
1211 /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */
1212 #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0)
1213 /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */
1214 #define FSL_FEATURE_RTC_HAS_SR_TIDF (0)
1215 /* @brief Has Tamper Detect Register (register TDR). */
1216 #define FSL_FEATURE_RTC_HAS_TDR (0)
1217 /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */
1218 #define FSL_FEATURE_RTC_HAS_TDR_TPF (0)
1219 /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */
1220 #define FSL_FEATURE_RTC_HAS_TDR_STF (0)
1221 /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */
1222 #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0)
1223 /* @brief Has Tamper Time Seconds Register (register TTSR). */
1224 #define FSL_FEATURE_RTC_HAS_TTSR (0)
1225 /* @brief Has Pin Configuration Register (register PCR). */
1226 #define FSL_FEATURE_RTC_HAS_PCR (0)
1227 
1228 /* SIM module features */
1229 
1230 /* @brief Has USB FS divider. */
1231 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
1232 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
1233 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
1234 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
1235 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
1236 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
1237 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1)
1238 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
1239 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
1240 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
1241 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
1242 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
1243 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0)
1244 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
1245 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
1246 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
1247 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
1248 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
1249 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
1250 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
1251 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
1252 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
1253 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
1254 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
1255 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
1256 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
1257 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
1258 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
1259 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1)
1260 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
1261 #define FSL_FEATURE_SIM_OPT_UART_COUNT (0)
1262 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
1263 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
1264 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
1265 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
1266 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
1267 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
1268 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
1269 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1)
1270 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
1271 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
1272 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
1273 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
1274 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
1275 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1)
1276 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
1277 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1)
1278 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
1279 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
1280 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
1281 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
1282 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
1283 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0)
1284 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
1285 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0)
1286 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
1287 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0)
1288 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
1289 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0)
1290 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
1291 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0)
1292 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
1293 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0)
1294 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
1295 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0)
1296 /* @brief Has FTM module(s) configuration. */
1297 #define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
1298 /* @brief Number of FTM modules. */
1299 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
1300 /* @brief Number of FTM triggers with selectable source. */
1301 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
1302 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
1303 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
1304 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
1305 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
1306 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
1307 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
1308 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
1309 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
1310 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
1311 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
1312 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
1313 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
1314 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
1315 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
1316 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
1317 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
1318 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
1319 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
1320 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
1321 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
1322 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
1323 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
1324 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
1325 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
1326 /* @brief Has TPM module(s) configuration. */
1327 #define FSL_FEATURE_SIM_OPT_HAS_TPM (1)
1328 /* @brief The highest TPM module index. */
1329 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2)
1330 /* @brief Has TPM module with index 0. */
1331 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1)
1332 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
1333 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1)
1334 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
1335 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1)
1336 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1337 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1)
1338 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
1339 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1)
1340 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1341 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1)
1342 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
1343 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1)
1344 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
1345 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1)
1346 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
1347 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0)
1348 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
1349 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0)
1350 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
1351 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
1352 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
1353 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
1354 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
1355 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
1356 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
1357 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
1358 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
1359 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
1360 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
1361 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
1362 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
1363 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
1364 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
1365 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
1366 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
1367 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
1368 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
1369 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
1370 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
1371 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1)
1372 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
1373 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
1374 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
1375 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
1376 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
1377 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
1378 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
1379 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1)
1380 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
1381 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
1382 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
1383 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
1384 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
1385 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1)
1386 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
1387 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0)
1388 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
1389 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
1390 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
1391 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
1392 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
1393 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
1394 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
1395 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
1396 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
1397 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
1398 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
1399 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
1400 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
1401 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
1402 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
1403 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
1404 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
1405 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
1406 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
1407 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
1408 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
1409 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
1410 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
1411 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3)
1412 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
1413 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
1414 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
1415 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
1416 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
1417 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
1418 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
1419 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
1420 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
1421 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
1422 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
1423 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
1424 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
1425 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
1426 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
1427 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
1428 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
1429 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
1430 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
1431 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
1432 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
1433 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
1434 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
1435 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
1436 /* @brief Has device die ID (register bit field SDID[DIEID]). */
1437 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
1438 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
1439 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1)
1440 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
1441 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
1442 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
1443 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
1444 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
1445 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
1446 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
1447 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1)
1448 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
1449 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
1450 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
1451 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
1452 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
1453 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
1454 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
1455 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
1456 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
1457 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
1458 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
1459 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
1460 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
1461 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1)
1462 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
1463 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1)
1464 /* @brief Has miscellanious control register (register MCR). */
1465 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
1466 /* @brief Has COP watchdog (registers COPC and SRVCOP). */
1467 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1)
1468 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
1469 #define FSL_FEATURE_SIM_HAS_COP_STOP (1)
1470 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
1471 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
1472 /* @brief Has UIDH registers. */
1473 #define FSL_FEATURE_SIM_HAS_UIDH (0)
1474 /* @brief Has UIDM registers. */
1475 #define FSL_FEATURE_SIM_HAS_UIDM (0)
1476 
1477 /* SMC module features */
1478 
1479 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
1480 #define FSL_FEATURE_SMC_HAS_PSTOPO (1)
1481 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
1482 #define FSL_FEATURE_SMC_HAS_LPOPO (0)
1483 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
1484 #define FSL_FEATURE_SMC_HAS_PORPO (1)
1485 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
1486 #define FSL_FEATURE_SMC_HAS_LPWUI (0)
1487 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
1488 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1)
1489 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
1490 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
1491 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
1492 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
1493 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
1494 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1)
1495 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
1496 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
1497 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
1498 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
1499 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
1500 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
1501 /* @brief Has stop submode. */
1502 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
1503 /* @brief Has stop submode 0(VLLS0). */
1504 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
1505 /* @brief Has stop submode 1(VLLS1). */
1506 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1)
1507 /* @brief Has stop submode 2(VLLS2). */
1508 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
1509 /* @brief Has SMC_PARAM. */
1510 #define FSL_FEATURE_SMC_HAS_PARAM (0)
1511 /* @brief Has SMC_VERID. */
1512 #define FSL_FEATURE_SMC_HAS_VERID (0)
1513 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
1514 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1)
1515 /* @brief Has tamper reset (register bit SRS[TAMPER]). */
1516 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
1517 /* @brief Has security violation reset (register bit SRS[SECVIO]). */
1518 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
1519 /* @brief Width of SMC registers. */
1520 #define FSL_FEATURE_SMC_REG_WIDTH (8)
1521 
1522 /* DSPI module features */
1523 
1524 /* @brief Receive/transmit FIFO size in number of items. */
1525 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4)
1526 /* @brief Maximum transfer data width in bits. */
1527 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
1528 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
1529 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (4)
1530 /* @brief Number of chip select pins. */
1531 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (3)
1532 /* @brief Number of CTAR registers. */
1533 #define FSL_FEATURE_DSPI_CTAR_COUNT (2)
1534 /* @brief Has chip select strobe capability on the PCS5 pin. */
1535 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0)
1536 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
1537 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
1538 /* @brief Has 16-bit data transfer support. */
1539 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
1540 /* @brief Has separate DMA RX and TX requests. */
1541 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
1542 
1543 /* SysTick module features */
1544 
1545 /* @brief Systick has external reference clock. */
1546 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1)
1547 /* @brief Systick external reference clock is core clock divided by this value. */
1548 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16)
1549 
1550 /* TPM module features */
1551 
1552 /* @brief Bus clock is the source clock for the module. */
1553 #define FSL_FEATURE_TPM_BUS_CLOCK (0)
1554 /* @brief Number of channels. */
1555 #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \
1556     (((x) == TPM0) ? (4) : \
1557     (((x) == TPM1) ? (2) : \
1558     (((x) == TPM2) ? (2) : (-1))))
1559 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
1560 #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
1561 /* @brief Has TPM_PARAM. */
1562 #define FSL_FEATURE_TPM_HAS_PARAM (0)
1563 /* @brief Has TPM_VERID. */
1564 #define FSL_FEATURE_TPM_HAS_VERID (0)
1565 /* @brief Has TPM_GLOBAL. */
1566 #define FSL_FEATURE_TPM_HAS_GLOBAL (0)
1567 /* @brief Has TPM_TRIG. */
1568 #define FSL_FEATURE_TPM_HAS_TRIG (0)
1569 /* @brief Whether TRIG register has effect. */
1570 #define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (0)
1571 /* @brief Has counter pause on trigger. */
1572 #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
1573 /* @brief Has external trigger selection. */
1574 #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
1575 /* @brief Has TPM_COMBINE register. */
1576 #define FSL_FEATURE_TPM_HAS_COMBINE (1)
1577 /* @brief Whether COMBINE register has effect. */
1578 #define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) \
1579     (((x) == TPM0) ? (0) : \
1580     (((x) == TPM1) ? (1) : \
1581     (((x) == TPM2) ? (1) : (-1))))
1582 /* @brief Has TPM_POL. */
1583 #define FSL_FEATURE_TPM_HAS_POL (1)
1584 /* @brief Whether POL register has effect. */
1585 #define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1)
1586 /* @brief Has TPM_FILTER register. */
1587 #define FSL_FEATURE_TPM_HAS_FILTER (1)
1588 /* @brief Whether FILTER register has effect. */
1589 #define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) \
1590     (((x) == TPM0) ? (0) : \
1591     (((x) == TPM1) ? (1) : \
1592     (((x) == TPM2) ? (1) : (-1))))
1593 /* @brief Has TPM_QDCTRL register. */
1594 #define FSL_FEATURE_TPM_HAS_QDCTRL (1)
1595 /* @brief Whether QDCTRL register has effect. */
1596 #define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) \
1597     (((x) == TPM0) ? (0) : \
1598     (((x) == TPM1) ? (1) : \
1599     (((x) == TPM2) ? (1) : (-1))))
1600 /* @brief Is affected by errata with ID 050050 (Incorrect duty output when EPWM mode is set to PS=0 during write 1 to CnV register). */
1601 #define FSL_FEATURE_TPM_HAS_ERRATA_050050 (0)
1602 /* @brief Whether 32 bits counter has effect. */
1603 #define FSL_FEATURE_TPM_HAS_32BIT_COUNTERn(x) (0)
1604 
1605 /* TRNG module features */
1606 
1607 /* No feature definitions */
1608 
1609 /* TSI module features */
1610 
1611 /* @brief TSI module version. */
1612 #define FSL_FEATURE_TSI_VERSION (4)
1613 /* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */
1614 #define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0)
1615 /* @brief Number of TSI channels. */
1616 #define FSL_FEATURE_TSI_CHANNEL_COUNT (16)
1617 
1618 /* VREF module features */
1619 
1620 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */
1621 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
1622 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
1623 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
1624 /* @brief If high/low buffer mode supported */
1625 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
1626 /* @brief Module has also low reference (registers VREFL/VREFH) */
1627 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
1628 /* @brief Has VREF_TRM4. */
1629 #define FSL_FEATURE_VREF_HAS_TRM4 (0)
1630 
1631 /* XCVR_ANALOG module features */
1632 
1633 /* No feature definitions */
1634 
1635 /* XCVR_PHY module features */
1636 
1637 /* No feature definitions */
1638 
1639 /* ZLL module features */
1640 
1641 /* No feature definitions */
1642 
1643 #endif /* _MKW21Z4_FEATURES_H_ */
1644 
1645