1 /* 2 ** ################################################################### 3 ** Version: rev. 0.3, 2015-06-08 4 ** Build: b210910 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2021 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 0.1 (2015-02-24) 20 ** Initial version. 21 ** - rev. 0.2 (2015-05-25) 22 ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 23 ** - rev. 0.3 (2015-06-08) 24 ** FTM features BUS_CLOCK and FAST_CLOCK removed. 25 ** 26 ** ################################################################### 27 */ 28 29 #ifndef _MKV58F24_FEATURES_H_ 30 #define _MKV58F24_FEATURES_H_ 31 32 /* SOC module features */ 33 34 #if defined(CPU_MKV58F1M0VLL24) || defined(CPU_MKV58F512VLL24) 35 /* @brief ADC16 availability on the SoC. */ 36 #define FSL_FEATURE_SOC_ADC16_COUNT (1) 37 /* @brief AIPS availability on the SoC. */ 38 #define FSL_FEATURE_SOC_AIPS_COUNT (2) 39 /* @brief AOI availability on the SoC. */ 40 #define FSL_FEATURE_SOC_AOI_COUNT (1) 41 /* @brief AXBS availability on the SoC. */ 42 #define FSL_FEATURE_SOC_AXBS_COUNT (1) 43 /* @brief FLEXCAN availability on the SoC. */ 44 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (3) 45 /* @brief MMCAU availability on the SoC. */ 46 #define FSL_FEATURE_SOC_MMCAU_COUNT (1) 47 /* @brief CMP availability on the SoC. */ 48 #define FSL_FEATURE_SOC_CMP_COUNT (4) 49 /* @brief CRC availability on the SoC. */ 50 #define FSL_FEATURE_SOC_CRC_COUNT (1) 51 /* @brief DAC availability on the SoC. */ 52 #define FSL_FEATURE_SOC_DAC_COUNT (1) 53 /* @brief EDMA availability on the SoC. */ 54 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 55 /* @brief DMAMUX availability on the SoC. */ 56 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 57 /* @brief DSPI availability on the SoC. */ 58 #define FSL_FEATURE_SOC_DSPI_COUNT (3) 59 /* @brief ENC availability on the SoC. */ 60 #define FSL_FEATURE_SOC_ENC_COUNT (1) 61 /* @brief ENET availability on the SoC. */ 62 #define FSL_FEATURE_SOC_ENET_COUNT (1) 63 /* @brief EWM availability on the SoC. */ 64 #define FSL_FEATURE_SOC_EWM_COUNT (1) 65 /* @brief FB availability on the SoC. */ 66 #define FSL_FEATURE_SOC_FB_COUNT (1) 67 /* @brief FMC availability on the SoC. */ 68 #define FSL_FEATURE_SOC_FMC_COUNT (1) 69 /* @brief FTFE availability on the SoC. */ 70 #define FSL_FEATURE_SOC_FTFE_COUNT (1) 71 /* @brief FTM availability on the SoC. */ 72 #define FSL_FEATURE_SOC_FTM_COUNT (4) 73 /* @brief GPIO availability on the SoC. */ 74 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 75 /* @brief HSADC availability on the SoC. */ 76 #define FSL_FEATURE_SOC_HSADC_COUNT (2) 77 /* @brief I2C availability on the SoC. */ 78 #define FSL_FEATURE_SOC_I2C_COUNT (2) 79 /* @brief LLWU availability on the SoC. */ 80 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 81 /* @brief LPTMR availability on the SoC. */ 82 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 83 /* @brief MCG availability on the SoC. */ 84 #define FSL_FEATURE_SOC_MCG_COUNT (1) 85 /* @brief MCM availability on the SoC. */ 86 #define FSL_FEATURE_SOC_MCM_COUNT (1) 87 /* @brief SYSMPU availability on the SoC. */ 88 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1) 89 /* @brief MSCM availability on the SoC. */ 90 #define FSL_FEATURE_SOC_MSCM_COUNT (1) 91 /* @brief OSC availability on the SoC. */ 92 #define FSL_FEATURE_SOC_OSC_COUNT (1) 93 /* @brief PDB availability on the SoC. */ 94 #define FSL_FEATURE_SOC_PDB_COUNT (2) 95 /* @brief PIT availability on the SoC. */ 96 #define FSL_FEATURE_SOC_PIT_COUNT (1) 97 /* @brief PMC availability on the SoC. */ 98 #define FSL_FEATURE_SOC_PMC_COUNT (1) 99 /* @brief PORT availability on the SoC. */ 100 #define FSL_FEATURE_SOC_PORT_COUNT (5) 101 /* @brief PWM availability on the SoC. */ 102 #define FSL_FEATURE_SOC_PWM_COUNT (2) 103 /* @brief RCM availability on the SoC. */ 104 #define FSL_FEATURE_SOC_RCM_COUNT (1) 105 /* @brief RFSYS availability on the SoC. */ 106 #define FSL_FEATURE_SOC_RFSYS_COUNT (1) 107 /* @brief RFVBAT availability on the SoC. */ 108 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) 109 /* @brief SIM availability on the SoC. */ 110 #define FSL_FEATURE_SOC_SIM_COUNT (1) 111 /* @brief SMC availability on the SoC. */ 112 #define FSL_FEATURE_SOC_SMC_COUNT (1) 113 /* @brief TRNG availability on the SoC. */ 114 #define FSL_FEATURE_SOC_TRNG_COUNT (1) 115 /* @brief UART availability on the SoC. */ 116 #define FSL_FEATURE_SOC_UART_COUNT (5) 117 /* @brief WDOG availability on the SoC. */ 118 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 119 /* @brief XBARA availability on the SoC. */ 120 #define FSL_FEATURE_SOC_XBARA_COUNT (1) 121 /* @brief XBARB availability on the SoC. */ 122 #define FSL_FEATURE_SOC_XBARB_COUNT (1) 123 #elif defined(CPU_MKV58F1M0VLQ24) || defined(CPU_MKV58F1M0VMD24) || defined(CPU_MKV58F512VLQ24) || defined(CPU_MKV58F512VMD24) 124 /* @brief ADC16 availability on the SoC. */ 125 #define FSL_FEATURE_SOC_ADC16_COUNT (1) 126 /* @brief AIPS availability on the SoC. */ 127 #define FSL_FEATURE_SOC_AIPS_COUNT (2) 128 /* @brief AOI availability on the SoC. */ 129 #define FSL_FEATURE_SOC_AOI_COUNT (1) 130 /* @brief AXBS availability on the SoC. */ 131 #define FSL_FEATURE_SOC_AXBS_COUNT (1) 132 /* @brief FLEXCAN availability on the SoC. */ 133 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (3) 134 /* @brief MMCAU availability on the SoC. */ 135 #define FSL_FEATURE_SOC_MMCAU_COUNT (1) 136 /* @brief CMP availability on the SoC. */ 137 #define FSL_FEATURE_SOC_CMP_COUNT (4) 138 /* @brief CRC availability on the SoC. */ 139 #define FSL_FEATURE_SOC_CRC_COUNT (1) 140 /* @brief DAC availability on the SoC. */ 141 #define FSL_FEATURE_SOC_DAC_COUNT (1) 142 /* @brief EDMA availability on the SoC. */ 143 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 144 /* @brief DMAMUX availability on the SoC. */ 145 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 146 /* @brief DSPI availability on the SoC. */ 147 #define FSL_FEATURE_SOC_DSPI_COUNT (3) 148 /* @brief ENC availability on the SoC. */ 149 #define FSL_FEATURE_SOC_ENC_COUNT (1) 150 /* @brief ENET availability on the SoC. */ 151 #define FSL_FEATURE_SOC_ENET_COUNT (1) 152 /* @brief EWM availability on the SoC. */ 153 #define FSL_FEATURE_SOC_EWM_COUNT (1) 154 /* @brief FB availability on the SoC. */ 155 #define FSL_FEATURE_SOC_FB_COUNT (1) 156 /* @brief FMC availability on the SoC. */ 157 #define FSL_FEATURE_SOC_FMC_COUNT (1) 158 /* @brief FTFE availability on the SoC. */ 159 #define FSL_FEATURE_SOC_FTFE_COUNT (1) 160 /* @brief FTM availability on the SoC. */ 161 #define FSL_FEATURE_SOC_FTM_COUNT (4) 162 /* @brief GPIO availability on the SoC. */ 163 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 164 /* @brief HSADC availability on the SoC. */ 165 #define FSL_FEATURE_SOC_HSADC_COUNT (2) 166 /* @brief I2C availability on the SoC. */ 167 #define FSL_FEATURE_SOC_I2C_COUNT (2) 168 /* @brief LLWU availability on the SoC. */ 169 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 170 /* @brief LPTMR availability on the SoC. */ 171 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 172 /* @brief MCG availability on the SoC. */ 173 #define FSL_FEATURE_SOC_MCG_COUNT (1) 174 /* @brief MCM availability on the SoC. */ 175 #define FSL_FEATURE_SOC_MCM_COUNT (1) 176 /* @brief SYSMPU availability on the SoC. */ 177 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1) 178 /* @brief MSCM availability on the SoC. */ 179 #define FSL_FEATURE_SOC_MSCM_COUNT (1) 180 /* @brief OSC availability on the SoC. */ 181 #define FSL_FEATURE_SOC_OSC_COUNT (1) 182 /* @brief PDB availability on the SoC. */ 183 #define FSL_FEATURE_SOC_PDB_COUNT (2) 184 /* @brief PIT availability on the SoC. */ 185 #define FSL_FEATURE_SOC_PIT_COUNT (1) 186 /* @brief PMC availability on the SoC. */ 187 #define FSL_FEATURE_SOC_PMC_COUNT (1) 188 /* @brief PORT availability on the SoC. */ 189 #define FSL_FEATURE_SOC_PORT_COUNT (5) 190 /* @brief PWM availability on the SoC. */ 191 #define FSL_FEATURE_SOC_PWM_COUNT (2) 192 /* @brief RCM availability on the SoC. */ 193 #define FSL_FEATURE_SOC_RCM_COUNT (1) 194 /* @brief RFSYS availability on the SoC. */ 195 #define FSL_FEATURE_SOC_RFSYS_COUNT (1) 196 /* @brief RFVBAT availability on the SoC. */ 197 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) 198 /* @brief SIM availability on the SoC. */ 199 #define FSL_FEATURE_SOC_SIM_COUNT (1) 200 /* @brief SMC availability on the SoC. */ 201 #define FSL_FEATURE_SOC_SMC_COUNT (1) 202 /* @brief TRNG availability on the SoC. */ 203 #define FSL_FEATURE_SOC_TRNG_COUNT (1) 204 /* @brief UART availability on the SoC. */ 205 #define FSL_FEATURE_SOC_UART_COUNT (6) 206 /* @brief WDOG availability on the SoC. */ 207 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 208 /* @brief XBARA availability on the SoC. */ 209 #define FSL_FEATURE_SOC_XBARA_COUNT (1) 210 /* @brief XBARB availability on the SoC. */ 211 #define FSL_FEATURE_SOC_XBARB_COUNT (1) 212 #endif 213 214 /* ADC16 module features */ 215 216 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ 217 #define FSL_FEATURE_ADC16_HAS_PGA (0) 218 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ 219 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) 220 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ 221 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) 222 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ 223 #define FSL_FEATURE_ADC16_HAS_DMA (1) 224 /* @brief Has differential mode (bitfield SC1x[DIFF]). */ 225 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) 226 /* @brief Has FIFO (bit SC4[AFDEP]). */ 227 #define FSL_FEATURE_ADC16_HAS_FIFO (0) 228 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ 229 #define FSL_FEATURE_ADC16_FIFO_SIZE (0) 230 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ 231 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) 232 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ 233 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) 234 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ 235 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) 236 /* @brief Has HW averaging (bit SC3[AVGE]). */ 237 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) 238 /* @brief Has offset correction (register OFS). */ 239 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) 240 /* @brief Maximum ADC resolution. */ 241 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) 242 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ 243 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) 244 245 /* AOI module features */ 246 247 /* @brief Maximum value of AOI0 input mux. */ 248 #define FSL_FEATURE_AOI_MODULE_INPUTS (4) 249 /* @brief Number of AOI0 events (related to number of registers AOI0_BFCRT01n/AOI0_BFCRT23n). */ 250 #define FSL_FEATURE_AOI_EVENT_COUNT (4) 251 252 /* FLEXCAN module features */ 253 254 /* @brief Message buffer size */ 255 #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (16) 256 /* @brief Has doze mode support (register bit field MCR[DOZE]). */ 257 #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) 258 /* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ 259 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1) 260 /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ 261 #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) 262 /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ 263 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) 264 /* @brief Instance has extended bit timing register (register CBT). */ 265 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) 266 /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 267 #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) 268 /* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 269 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) 270 /* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */ 271 #define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1) 272 /* @brief Has bitfield name BUF31TO0M. */ 273 #define FSL_FEATURE_FLEXCAN_HAS_BUF31TO0M (1) 274 /* @brief Number of interrupt vectors. */ 275 #define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6) 276 /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ 277 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) 278 279 /* CMP module features */ 280 281 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ 282 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) 283 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ 284 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) 285 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ 286 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) 287 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ 288 #define FSL_FEATURE_CMP_HAS_DMA (1) 289 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ 290 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) 291 /* @brief Has DAC Test function in CMP (register DACTEST). */ 292 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) 293 294 /* CRC module features */ 295 296 /* @brief Has data register with name CRC */ 297 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 298 299 /* DAC module features */ 300 301 /* @brief Define the size of hardware buffer */ 302 #define FSL_FEATURE_DAC_BUFFER_SIZE (16) 303 /* @brief Define whether the buffer supports watermark event detection or not. */ 304 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) 305 /* @brief Define whether the buffer supports watermark selection detection or not. */ 306 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) 307 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ 308 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) 309 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ 310 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) 311 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ 312 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) 313 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ 314 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) 315 /* @brief Define whether FIFO buffer mode is available or not. */ 316 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (1) 317 /* @brief Define whether swing buffer mode is available or not.. */ 318 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1) 319 320 /* EDMA module features */ 321 322 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 323 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (32) 324 /* @brief Total number of DMA channels on all modules. */ 325 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32) 326 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 327 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (2) 328 /* @brief Has DMA_Error interrupt vector. */ 329 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 330 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ 331 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32) 332 /* @brief Channel IRQ entry shared offset. */ 333 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (16) 334 /* @brief If 8 bytes transfer supported. */ 335 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (0) 336 /* @brief If 16 bytes transfer supported. */ 337 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) 338 339 /* DMAMUX module features */ 340 341 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 342 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32) 343 /* @brief Total number of DMA channels on all modules. */ 344 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (32) 345 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 346 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 347 /* @brief Register CHCFGn width. */ 348 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8) 349 350 /* ENC module features */ 351 352 /* @brief Has no simultaneous PHASEA and PHASEB change interrupt (register bit field CTRL2[SABIE] and CTRL2[SABIRQ]). */ 353 #define FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT (0) 354 /* @brief Has register CTRL3. */ 355 #define FSL_FEATURE_ENC_HAS_CTRL3 (0) 356 /* @brief Has register LASTEDGE or LASTEDGEH. */ 357 #define FSL_FEATURE_ENC_HAS_LASTEDGE (0) 358 /* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ 359 #define FSL_FEATURE_ENC_HAS_POSDPER (0) 360 361 /* ENET module features */ 362 363 /* @brief Support Interrupt Coalesce */ 364 #define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (0) 365 /* @brief Queue Size. */ 366 #define FSL_FEATURE_ENET_QUEUE (1) 367 /* @brief Has AVB Support. */ 368 #define FSL_FEATURE_ENET_HAS_AVB (0) 369 /* @brief Has Timer Pulse Width control. */ 370 #define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (0) 371 /* @brief Has Extend MDIO Support. */ 372 #define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1) 373 /* @brief Has Additional 1588 Timer Channel Interrupt. */ 374 #define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (1) 375 /* @brief Support Interrupt Coalesce for each instance */ 376 #define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (0) 377 /* @brief Queue Size for each instance. */ 378 #define FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) (1) 379 /* @brief Has AVB Support for each instance. */ 380 #define FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(x) (0) 381 /* @brief Has Timer Pulse Width control for each instance. */ 382 #define FSL_FEATURE_ENET_INSTANCE_HAS_TIMER_PWCONTROLn(x) (0) 383 /* @brief Has Extend MDIO Support for each instance. */ 384 #define FSL_FEATURE_ENET_INSTANCE_HAS_EXTEND_MDIOn(x) (1) 385 /* @brief Has Additional 1588 Timer Channel Interrupt for each instance. */ 386 #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) 387 /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ 388 #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) 389 /* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ 390 #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) 391 /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ 392 #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) 393 /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ 394 #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) 395 396 /* EWM module features */ 397 398 /* @brief Has clock select (register CLKCTRL). */ 399 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) 400 /* @brief Has clock prescaler (register CLKPRESCALER). */ 401 #define FSL_FEATURE_EWM_HAS_PRESCALER (1) 402 403 /* FLEXBUS module features */ 404 405 /* No feature definitions */ 406 407 /* FLASH module features */ 408 409 #if defined(CPU_MKV58F1M0VLL24) || defined(CPU_MKV58F1M0VLQ24) || defined(CPU_MKV58F1M0VMD24) 410 /* @brief Is of type FTFA. */ 411 #define FSL_FEATURE_FLASH_IS_FTFA (0) 412 /* @brief Is of type FTFE. */ 413 #define FSL_FEATURE_FLASH_IS_FTFE (1) 414 /* @brief Is of type FTFL. */ 415 #define FSL_FEATURE_FLASH_IS_FTFL (0) 416 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 417 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) 418 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 419 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 420 /* @brief Has EEPROM region protection (register FEPROT). */ 421 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 422 /* @brief Has data flash region protection (register FDPROT). */ 423 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 424 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 425 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 426 /* @brief Has flash cache control in FMC module. */ 427 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 428 /* @brief Has flash cache control in MCM module. */ 429 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 430 /* @brief Has flash cache control in MSCM module. */ 431 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 432 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 433 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (1) 434 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 435 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 436 /* @brief P-Flash start address. */ 437 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x10000000) 438 /* @brief P-Flash block count. */ 439 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 440 /* @brief P-Flash block size. */ 441 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (1048576) 442 /* @brief P-Flash sector size. */ 443 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (8192) 444 /* @brief P-Flash write unit size. */ 445 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) 446 /* @brief P-Flash data path width. */ 447 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (32) 448 /* @brief P-Flash block swap feature. */ 449 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 450 /* @brief P-Flash protection region count. */ 451 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 452 /* @brief Has FlexNVM memory. */ 453 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 454 /* @brief Has FlexNVM alias. */ 455 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 456 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 457 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 458 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 459 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 460 /* @brief FlexNVM block count. */ 461 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 462 /* @brief FlexNVM block size. */ 463 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 464 /* @brief FlexNVM sector size. */ 465 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 466 /* @brief FlexNVM write unit size. */ 467 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 468 /* @brief FlexNVM data path width. */ 469 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 470 /* @brief Has FlexRAM memory. */ 471 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) 472 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 473 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x18000000) 474 /* @brief FlexRAM size. */ 475 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096) 476 /* @brief Has 0x00 Read 1s Block command. */ 477 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 478 /* @brief Has 0x01 Read 1s Section command. */ 479 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 480 /* @brief Has 0x02 Program Check command. */ 481 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 482 /* @brief Has 0x03 Read Resource command. */ 483 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 484 /* @brief Has 0x06 Program Longword command. */ 485 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) 486 /* @brief Has 0x07 Program Phrase command. */ 487 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) 488 /* @brief Has 0x08 Erase Flash Block command. */ 489 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 490 /* @brief Has 0x09 Erase Flash Sector command. */ 491 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 492 /* @brief Has 0x0B Program Section command. */ 493 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) 494 /* @brief Has 0x40 Read 1s All Blocks command. */ 495 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 496 /* @brief Has 0x41 Read Once command. */ 497 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 498 /* @brief Has 0x43 Program Once command. */ 499 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 500 /* @brief Has 0x44 Erase All Blocks command. */ 501 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 502 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 503 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 504 /* @brief Has 0x46 Swap Control command. */ 505 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 506 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 507 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) 508 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 509 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 510 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 511 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 512 /* @brief Has 0x80 Program Partition command. */ 513 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 514 /* @brief Has 0x81 Set FlexRAM Function command. */ 515 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 516 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 517 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (32) 518 /* @brief P-Flash Erase sector command address alignment. */ 519 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (32) 520 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 521 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (32) 522 /* @brief P-Flash Read resource command address alignment. */ 523 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) 524 /* @brief P-Flash Program check command address alignment. */ 525 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 526 /* @brief P-Flash Program check command address alignment. */ 527 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 528 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 529 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 530 /* @brief FlexNVM Erase sector command address alignment. */ 531 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 532 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 533 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 534 /* @brief FlexNVM Read resource command address alignment. */ 535 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 536 /* @brief FlexNVM Program check command address alignment. */ 537 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 538 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 539 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 540 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 541 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 542 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 543 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 544 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 545 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 546 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 547 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 548 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 549 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 550 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 551 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 552 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 553 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 554 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 555 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 556 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 557 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 558 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 559 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 560 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 561 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 562 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 563 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 564 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 565 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 566 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 567 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 568 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 569 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 570 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 571 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 572 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 573 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 574 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 575 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000) 576 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 577 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) 578 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 579 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) 580 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 581 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) 582 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 583 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) 584 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 585 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) 586 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 587 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) 588 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 589 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) 590 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 591 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 592 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 593 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 594 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 595 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 596 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 597 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 598 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 599 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 600 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 601 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) 602 #elif defined(CPU_MKV58F512VLL24) || defined(CPU_MKV58F512VLQ24) || defined(CPU_MKV58F512VMD24) 603 /* @brief Is of type FTFA. */ 604 #define FSL_FEATURE_FLASH_IS_FTFA (0) 605 /* @brief Is of type FTFE. */ 606 #define FSL_FEATURE_FLASH_IS_FTFE (1) 607 /* @brief Is of type FTFL. */ 608 #define FSL_FEATURE_FLASH_IS_FTFL (0) 609 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 610 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) 611 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 612 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 613 /* @brief Has EEPROM region protection (register FEPROT). */ 614 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 615 /* @brief Has data flash region protection (register FDPROT). */ 616 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 617 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 618 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 619 /* @brief Has flash cache control in FMC module. */ 620 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 621 /* @brief Has flash cache control in MCM module. */ 622 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 623 /* @brief Has flash cache control in MSCM module. */ 624 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 625 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 626 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (1) 627 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 628 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 629 /* @brief P-Flash start address. */ 630 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x10000000) 631 /* @brief P-Flash block count. */ 632 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 633 /* @brief P-Flash block size. */ 634 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288) 635 /* @brief P-Flash sector size. */ 636 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (8192) 637 /* @brief P-Flash write unit size. */ 638 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) 639 /* @brief P-Flash data path width. */ 640 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (32) 641 /* @brief P-Flash block swap feature. */ 642 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 643 /* @brief P-Flash protection region count. */ 644 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 645 /* @brief Has FlexNVM memory. */ 646 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 647 /* @brief Has FlexNVM alias. */ 648 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 649 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 650 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 651 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 652 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 653 /* @brief FlexNVM block count. */ 654 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 655 /* @brief FlexNVM block size. */ 656 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 657 /* @brief FlexNVM sector size. */ 658 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 659 /* @brief FlexNVM write unit size. */ 660 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 661 /* @brief FlexNVM data path width. */ 662 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 663 /* @brief Has FlexRAM memory. */ 664 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) 665 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 666 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x18000000) 667 /* @brief FlexRAM size. */ 668 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096) 669 /* @brief Has 0x00 Read 1s Block command. */ 670 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 671 /* @brief Has 0x01 Read 1s Section command. */ 672 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 673 /* @brief Has 0x02 Program Check command. */ 674 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 675 /* @brief Has 0x03 Read Resource command. */ 676 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 677 /* @brief Has 0x06 Program Longword command. */ 678 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) 679 /* @brief Has 0x07 Program Phrase command. */ 680 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) 681 /* @brief Has 0x08 Erase Flash Block command. */ 682 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 683 /* @brief Has 0x09 Erase Flash Sector command. */ 684 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 685 /* @brief Has 0x0B Program Section command. */ 686 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) 687 /* @brief Has 0x40 Read 1s All Blocks command. */ 688 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 689 /* @brief Has 0x41 Read Once command. */ 690 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 691 /* @brief Has 0x43 Program Once command. */ 692 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 693 /* @brief Has 0x44 Erase All Blocks command. */ 694 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 695 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 696 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 697 /* @brief Has 0x46 Swap Control command. */ 698 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 699 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 700 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) 701 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 702 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 703 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 704 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 705 /* @brief Has 0x80 Program Partition command. */ 706 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 707 /* @brief Has 0x81 Set FlexRAM Function command. */ 708 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 709 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 710 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (32) 711 /* @brief P-Flash Erase sector command address alignment. */ 712 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (32) 713 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 714 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (32) 715 /* @brief P-Flash Read resource command address alignment. */ 716 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) 717 /* @brief P-Flash Program check command address alignment. */ 718 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 719 /* @brief P-Flash Program check command address alignment. */ 720 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 721 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 722 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 723 /* @brief FlexNVM Erase sector command address alignment. */ 724 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 725 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 726 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 727 /* @brief FlexNVM Read resource command address alignment. */ 728 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 729 /* @brief FlexNVM Program check command address alignment. */ 730 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 731 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 732 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 733 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 734 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 735 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 736 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 737 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 738 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 739 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 740 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 741 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 742 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 743 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 744 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 745 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 746 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 747 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 748 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 749 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 750 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 751 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 752 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 753 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 754 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 755 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 756 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 757 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 758 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 759 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 760 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 761 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 762 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 763 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 764 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 765 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 766 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 767 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 768 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000) 769 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 770 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) 771 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 772 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) 773 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 774 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) 775 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 776 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) 777 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 778 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) 779 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 780 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) 781 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 782 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) 783 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 784 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 785 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 786 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 787 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 788 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 789 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 790 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 791 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 792 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 793 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 794 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) 795 #endif /* defined(CPU_MKV58F1M0VLL24) || defined(CPU_MKV58F1M0VLQ24) || defined(CPU_MKV58F1M0VMD24) */ 796 797 /* FTM module features */ 798 799 /* @brief Number of channels. */ 800 #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ 801 (((x) == FTM0) ? (8) : \ 802 (((x) == FTM1) ? (2) : \ 803 (((x) == FTM2) ? (2) : \ 804 (((x) == FTM3) ? (8) : (-1))))) 805 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 806 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) 807 /* @brief Has extended deadtime value. */ 808 #define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0) 809 /* @brief Enable pwm output for the module. */ 810 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0) 811 /* @brief Has half-cycle reload for the module. */ 812 #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0) 813 /* @brief Has reload interrupt. */ 814 #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0) 815 /* @brief Has reload initialization trigger. */ 816 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0) 817 /* @brief Has DMA support, bitfield CnSC[DMA]. */ 818 #define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1) 819 /* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */ 820 #define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (0) 821 /* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */ 822 #define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0) 823 /* @brief Has no QDCTRL. */ 824 #define FSL_FEATURE_FTM_HAS_NO_QDCTRL (0) 825 /* @brief If instance has only TPM function. */ 826 #define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0) 827 828 /* GPIO module features */ 829 830 /* @brief Has GPIO attribute checker register (GACR). */ 831 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) 832 833 /* I2C module features */ 834 835 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ 836 #define FSL_FEATURE_I2C_HAS_SMBUS (1) 837 /* @brief Maximum supported baud rate in kilobit per second. */ 838 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (100) 839 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ 840 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) 841 /* @brief Has DMA support (register bit C1[DMAEN]). */ 842 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) 843 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ 844 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) 845 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ 846 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) 847 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ 848 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) 849 /* @brief Maximum width of the glitch filter in number of bus clocks. */ 850 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) 851 /* @brief Has control of the drive capability of the I2C pins. */ 852 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) 853 /* @brief Has double buffering support (register S2). */ 854 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) 855 /* @brief Has double buffer enable. */ 856 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) 857 858 /* LLWU module features */ 859 860 #if defined(CPU_MKV58F1M0VLL24) || defined(CPU_MKV58F512VLL24) 861 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 862 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (22) 863 /* @brief Has pins 8-15 connected to LLWU device. */ 864 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 865 /* @brief Maximum number of internal modules connected to LLWU device. */ 866 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (4) 867 /* @brief Number of digital filters. */ 868 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 869 /* @brief Has MF register. */ 870 #define FSL_FEATURE_LLWU_HAS_MF (1) 871 /* @brief Has PF register. */ 872 #define FSL_FEATURE_LLWU_HAS_PF (1) 873 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 874 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 875 /* @brief Has no internal module wakeup flag register. */ 876 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 877 /* @brief Has external pin 0 connected to LLWU device. */ 878 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 879 /* @brief Index of port of external pin. */ 880 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) 881 /* @brief Number of external pin port on specified port. */ 882 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) 883 /* @brief Has external pin 1 connected to LLWU device. */ 884 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) 885 /* @brief Index of port of external pin. */ 886 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX) 887 /* @brief Number of external pin port on specified port. */ 888 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) 889 /* @brief Has external pin 2 connected to LLWU device. */ 890 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) 891 /* @brief Index of port of external pin. */ 892 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX) 893 /* @brief Number of external pin port on specified port. */ 894 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4) 895 /* @brief Has external pin 3 connected to LLWU device. */ 896 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 897 /* @brief Index of port of external pin. */ 898 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 899 /* @brief Number of external pin port on specified port. */ 900 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 901 /* @brief Has external pin 4 connected to LLWU device. */ 902 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 903 /* @brief Index of port of external pin. */ 904 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 905 /* @brief Number of external pin port on specified port. */ 906 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) 907 /* @brief Has external pin 5 connected to LLWU device. */ 908 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 909 /* @brief Index of port of external pin. */ 910 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 911 /* @brief Number of external pin port on specified port. */ 912 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 913 /* @brief Has external pin 6 connected to LLWU device. */ 914 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 915 /* @brief Index of port of external pin. */ 916 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 917 /* @brief Number of external pin port on specified port. */ 918 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 919 /* @brief Has external pin 7 connected to LLWU device. */ 920 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 921 /* @brief Index of port of external pin. */ 922 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 923 /* @brief Number of external pin port on specified port. */ 924 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 925 /* @brief Has external pin 8 connected to LLWU device. */ 926 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 927 /* @brief Index of port of external pin. */ 928 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 929 /* @brief Number of external pin port on specified port. */ 930 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 931 /* @brief Has external pin 9 connected to LLWU device. */ 932 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 933 /* @brief Index of port of external pin. */ 934 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 935 /* @brief Number of external pin port on specified port. */ 936 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 937 /* @brief Has external pin 10 connected to LLWU device. */ 938 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 939 /* @brief Index of port of external pin. */ 940 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 941 /* @brief Number of external pin port on specified port. */ 942 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 943 /* @brief Has external pin 11 connected to LLWU device. */ 944 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 945 /* @brief Index of port of external pin. */ 946 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) 947 /* @brief Number of external pin port on specified port. */ 948 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) 949 /* @brief Has external pin 12 connected to LLWU device. */ 950 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 951 /* @brief Index of port of external pin. */ 952 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 953 /* @brief Number of external pin port on specified port. */ 954 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 955 /* @brief Has external pin 13 connected to LLWU device. */ 956 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 957 /* @brief Index of port of external pin. */ 958 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 959 /* @brief Number of external pin port on specified port. */ 960 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 961 /* @brief Has external pin 14 connected to LLWU device. */ 962 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 963 /* @brief Index of port of external pin. */ 964 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 965 /* @brief Number of external pin port on specified port. */ 966 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 967 /* @brief Has external pin 15 connected to LLWU device. */ 968 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 969 /* @brief Index of port of external pin. */ 970 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 971 /* @brief Number of external pin port on specified port. */ 972 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 973 /* @brief Has external pin 16 connected to LLWU device. */ 974 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1) 975 /* @brief Index of port of external pin. */ 976 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOE_IDX) 977 /* @brief Number of external pin port on specified port. */ 978 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (6) 979 /* @brief Has external pin 17 connected to LLWU device. */ 980 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 981 /* @brief Index of port of external pin. */ 982 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 983 /* @brief Number of external pin port on specified port. */ 984 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 985 /* @brief Has external pin 18 connected to LLWU device. */ 986 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 987 /* @brief Index of port of external pin. */ 988 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 989 /* @brief Number of external pin port on specified port. */ 990 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 991 /* @brief Has external pin 19 connected to LLWU device. */ 992 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1) 993 /* @brief Index of port of external pin. */ 994 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOE_IDX) 995 /* @brief Number of external pin port on specified port. */ 996 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (17) 997 /* @brief Has external pin 20 connected to LLWU device. */ 998 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1) 999 /* @brief Index of port of external pin. */ 1000 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOE_IDX) 1001 /* @brief Number of external pin port on specified port. */ 1002 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (18) 1003 /* @brief Has external pin 21 connected to LLWU device. */ 1004 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1) 1005 /* @brief Index of port of external pin. */ 1006 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX) 1007 /* @brief Number of external pin port on specified port. */ 1008 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (25) 1009 /* @brief Has external pin 22 connected to LLWU device. */ 1010 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 1011 /* @brief Index of port of external pin. */ 1012 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 1013 /* @brief Number of external pin port on specified port. */ 1014 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 1015 /* @brief Has external pin 23 connected to LLWU device. */ 1016 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 1017 /* @brief Index of port of external pin. */ 1018 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 1019 /* @brief Number of external pin port on specified port. */ 1020 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 1021 /* @brief Has external pin 24 connected to LLWU device. */ 1022 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 1023 /* @brief Index of port of external pin. */ 1024 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 1025 /* @brief Number of external pin port on specified port. */ 1026 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 1027 /* @brief Has external pin 25 connected to LLWU device. */ 1028 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 1029 /* @brief Index of port of external pin. */ 1030 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 1031 /* @brief Number of external pin port on specified port. */ 1032 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 1033 /* @brief Has external pin 26 connected to LLWU device. */ 1034 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 1035 /* @brief Index of port of external pin. */ 1036 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 1037 /* @brief Number of external pin port on specified port. */ 1038 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 1039 /* @brief Has external pin 27 connected to LLWU device. */ 1040 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 1041 /* @brief Index of port of external pin. */ 1042 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 1043 /* @brief Number of external pin port on specified port. */ 1044 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 1045 /* @brief Has external pin 28 connected to LLWU device. */ 1046 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 1047 /* @brief Index of port of external pin. */ 1048 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 1049 /* @brief Number of external pin port on specified port. */ 1050 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 1051 /* @brief Has external pin 29 connected to LLWU device. */ 1052 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 1053 /* @brief Index of port of external pin. */ 1054 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 1055 /* @brief Number of external pin port on specified port. */ 1056 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 1057 /* @brief Has external pin 30 connected to LLWU device. */ 1058 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 1059 /* @brief Index of port of external pin. */ 1060 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 1061 /* @brief Number of external pin port on specified port. */ 1062 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 1063 /* @brief Has external pin 31 connected to LLWU device. */ 1064 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 1065 /* @brief Index of port of external pin. */ 1066 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 1067 /* @brief Number of external pin port on specified port. */ 1068 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 1069 /* @brief Has internal module 0 connected to LLWU device. */ 1070 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 1071 /* @brief Has internal module 1 connected to LLWU device. */ 1072 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 1073 /* @brief Has internal module 2 connected to LLWU device. */ 1074 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 1075 /* @brief Has internal module 3 connected to LLWU device. */ 1076 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) 1077 /* @brief Has internal module 4 connected to LLWU device. */ 1078 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) 1079 /* @brief Has internal module 5 connected to LLWU device. */ 1080 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (0) 1081 /* @brief Has internal module 6 connected to LLWU device. */ 1082 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 1083 /* @brief Has internal module 7 connected to LLWU device. */ 1084 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (0) 1085 /* @brief Has Version ID Register (LLWU_VERID). */ 1086 #define FSL_FEATURE_LLWU_HAS_VERID (0) 1087 /* @brief Has Parameter Register (LLWU_PARAM). */ 1088 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 1089 /* @brief Width of registers of the LLWU. */ 1090 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 1091 /* @brief Has DMA Enable register (LLWU_DE). */ 1092 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 1093 #elif defined(CPU_MKV58F1M0VLQ24) || defined(CPU_MKV58F1M0VMD24) || defined(CPU_MKV58F512VLQ24) || defined(CPU_MKV58F512VMD24) 1094 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 1095 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (26) 1096 /* @brief Has pins 8-15 connected to LLWU device. */ 1097 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 1098 /* @brief Maximum number of internal modules connected to LLWU device. */ 1099 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (4) 1100 /* @brief Number of digital filters. */ 1101 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 1102 /* @brief Has MF register. */ 1103 #define FSL_FEATURE_LLWU_HAS_MF (1) 1104 /* @brief Has PF register. */ 1105 #define FSL_FEATURE_LLWU_HAS_PF (1) 1106 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 1107 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 1108 /* @brief Has no internal module wakeup flag register. */ 1109 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 1110 /* @brief Has external pin 0 connected to LLWU device. */ 1111 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 1112 /* @brief Index of port of external pin. */ 1113 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) 1114 /* @brief Number of external pin port on specified port. */ 1115 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) 1116 /* @brief Has external pin 1 connected to LLWU device. */ 1117 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) 1118 /* @brief Index of port of external pin. */ 1119 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX) 1120 /* @brief Number of external pin port on specified port. */ 1121 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) 1122 /* @brief Has external pin 2 connected to LLWU device. */ 1123 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) 1124 /* @brief Index of port of external pin. */ 1125 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX) 1126 /* @brief Number of external pin port on specified port. */ 1127 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4) 1128 /* @brief Has external pin 3 connected to LLWU device. */ 1129 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 1130 /* @brief Index of port of external pin. */ 1131 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 1132 /* @brief Number of external pin port on specified port. */ 1133 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 1134 /* @brief Has external pin 4 connected to LLWU device. */ 1135 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 1136 /* @brief Index of port of external pin. */ 1137 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 1138 /* @brief Number of external pin port on specified port. */ 1139 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) 1140 /* @brief Has external pin 5 connected to LLWU device. */ 1141 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 1142 /* @brief Index of port of external pin. */ 1143 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 1144 /* @brief Number of external pin port on specified port. */ 1145 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 1146 /* @brief Has external pin 6 connected to LLWU device. */ 1147 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 1148 /* @brief Index of port of external pin. */ 1149 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 1150 /* @brief Number of external pin port on specified port. */ 1151 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 1152 /* @brief Has external pin 7 connected to LLWU device. */ 1153 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 1154 /* @brief Index of port of external pin. */ 1155 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 1156 /* @brief Number of external pin port on specified port. */ 1157 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 1158 /* @brief Has external pin 8 connected to LLWU device. */ 1159 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 1160 /* @brief Index of port of external pin. */ 1161 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 1162 /* @brief Number of external pin port on specified port. */ 1163 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 1164 /* @brief Has external pin 9 connected to LLWU device. */ 1165 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 1166 /* @brief Index of port of external pin. */ 1167 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 1168 /* @brief Number of external pin port on specified port. */ 1169 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 1170 /* @brief Has external pin 10 connected to LLWU device. */ 1171 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 1172 /* @brief Index of port of external pin. */ 1173 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 1174 /* @brief Number of external pin port on specified port. */ 1175 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 1176 /* @brief Has external pin 11 connected to LLWU device. */ 1177 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 1178 /* @brief Index of port of external pin. */ 1179 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) 1180 /* @brief Number of external pin port on specified port. */ 1181 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) 1182 /* @brief Has external pin 12 connected to LLWU device. */ 1183 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 1184 /* @brief Index of port of external pin. */ 1185 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 1186 /* @brief Number of external pin port on specified port. */ 1187 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 1188 /* @brief Has external pin 13 connected to LLWU device. */ 1189 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 1190 /* @brief Index of port of external pin. */ 1191 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 1192 /* @brief Number of external pin port on specified port. */ 1193 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 1194 /* @brief Has external pin 14 connected to LLWU device. */ 1195 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 1196 /* @brief Index of port of external pin. */ 1197 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 1198 /* @brief Number of external pin port on specified port. */ 1199 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 1200 /* @brief Has external pin 15 connected to LLWU device. */ 1201 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 1202 /* @brief Index of port of external pin. */ 1203 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 1204 /* @brief Number of external pin port on specified port. */ 1205 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 1206 /* @brief Has external pin 16 connected to LLWU device. */ 1207 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1) 1208 /* @brief Index of port of external pin. */ 1209 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOE_IDX) 1210 /* @brief Number of external pin port on specified port. */ 1211 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (6) 1212 /* @brief Has external pin 17 connected to LLWU device. */ 1213 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1) 1214 /* @brief Index of port of external pin. */ 1215 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOE_IDX) 1216 /* @brief Number of external pin port on specified port. */ 1217 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (9) 1218 /* @brief Has external pin 18 connected to LLWU device. */ 1219 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1) 1220 /* @brief Index of port of external pin. */ 1221 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOE_IDX) 1222 /* @brief Number of external pin port on specified port. */ 1223 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (10) 1224 /* @brief Has external pin 19 connected to LLWU device. */ 1225 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1) 1226 /* @brief Index of port of external pin. */ 1227 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOE_IDX) 1228 /* @brief Number of external pin port on specified port. */ 1229 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (17) 1230 /* @brief Has external pin 20 connected to LLWU device. */ 1231 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1) 1232 /* @brief Index of port of external pin. */ 1233 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOE_IDX) 1234 /* @brief Number of external pin port on specified port. */ 1235 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (18) 1236 /* @brief Has external pin 21 connected to LLWU device. */ 1237 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1) 1238 /* @brief Index of port of external pin. */ 1239 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX) 1240 /* @brief Number of external pin port on specified port. */ 1241 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (25) 1242 /* @brief Has external pin 22 connected to LLWU device. */ 1243 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1) 1244 /* @brief Index of port of external pin. */ 1245 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOA_IDX) 1246 /* @brief Number of external pin port on specified port. */ 1247 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (10) 1248 /* @brief Has external pin 23 connected to LLWU device. */ 1249 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1) 1250 /* @brief Index of port of external pin. */ 1251 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOA_IDX) 1252 /* @brief Number of external pin port on specified port. */ 1253 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (11) 1254 /* @brief Has external pin 24 connected to LLWU device. */ 1255 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (1) 1256 /* @brief Index of port of external pin. */ 1257 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (GPIOD_IDX) 1258 /* @brief Number of external pin port on specified port. */ 1259 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (8) 1260 /* @brief Has external pin 25 connected to LLWU device. */ 1261 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (1) 1262 /* @brief Index of port of external pin. */ 1263 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (GPIOD_IDX) 1264 /* @brief Number of external pin port on specified port. */ 1265 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (11) 1266 /* @brief Has external pin 26 connected to LLWU device. */ 1267 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 1268 /* @brief Index of port of external pin. */ 1269 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 1270 /* @brief Number of external pin port on specified port. */ 1271 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 1272 /* @brief Has external pin 27 connected to LLWU device. */ 1273 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 1274 /* @brief Index of port of external pin. */ 1275 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 1276 /* @brief Number of external pin port on specified port. */ 1277 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 1278 /* @brief Has external pin 28 connected to LLWU device. */ 1279 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 1280 /* @brief Index of port of external pin. */ 1281 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 1282 /* @brief Number of external pin port on specified port. */ 1283 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 1284 /* @brief Has external pin 29 connected to LLWU device. */ 1285 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 1286 /* @brief Index of port of external pin. */ 1287 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 1288 /* @brief Number of external pin port on specified port. */ 1289 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 1290 /* @brief Has external pin 30 connected to LLWU device. */ 1291 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 1292 /* @brief Index of port of external pin. */ 1293 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 1294 /* @brief Number of external pin port on specified port. */ 1295 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 1296 /* @brief Has external pin 31 connected to LLWU device. */ 1297 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 1298 /* @brief Index of port of external pin. */ 1299 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 1300 /* @brief Number of external pin port on specified port. */ 1301 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 1302 /* @brief Has internal module 0 connected to LLWU device. */ 1303 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 1304 /* @brief Has internal module 1 connected to LLWU device. */ 1305 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 1306 /* @brief Has internal module 2 connected to LLWU device. */ 1307 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 1308 /* @brief Has internal module 3 connected to LLWU device. */ 1309 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) 1310 /* @brief Has internal module 4 connected to LLWU device. */ 1311 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) 1312 /* @brief Has internal module 5 connected to LLWU device. */ 1313 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (0) 1314 /* @brief Has internal module 6 connected to LLWU device. */ 1315 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 1316 /* @brief Has internal module 7 connected to LLWU device. */ 1317 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (0) 1318 /* @brief Has Version ID Register (LLWU_VERID). */ 1319 #define FSL_FEATURE_LLWU_HAS_VERID (0) 1320 /* @brief Has Parameter Register (LLWU_PARAM). */ 1321 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 1322 /* @brief Width of registers of the LLWU. */ 1323 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 1324 /* @brief Has DMA Enable register (LLWU_DE). */ 1325 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 1326 #endif /* defined(CPU_MKV58F1M0VLL24) || defined(CPU_MKV58F512VLL24) */ 1327 1328 /* LPTMR module features */ 1329 1330 /* @brief Has shared interrupt handler with another LPTMR module. */ 1331 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 1332 /* @brief Whether LPTMR counter is 32 bits width. */ 1333 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) 1334 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 1335 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) 1336 1337 /* MCG module features */ 1338 1339 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ 1340 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1) 1341 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ 1342 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (7) 1343 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ 1344 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (16) 1345 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */ 1346 #define FSL_FEATURE_MCG_PLL_REF_MIN (8000000) 1347 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */ 1348 #define FSL_FEATURE_MCG_PLL_REF_MAX (16000000) 1349 /* @brief The PLL clock is divided by 2 before VCO divider. */ 1350 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (1) 1351 /* @brief FRDIV supports 1280. */ 1352 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) 1353 /* @brief FRDIV supports 1536. */ 1354 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) 1355 /* @brief MCGFFCLK divider. */ 1356 #define FSL_FEATURE_MCG_FFCLK_DIV (1) 1357 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ 1358 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) 1359 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ 1360 #define FSL_FEATURE_MCG_HAS_RTC_32K (0) 1361 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ 1362 #define FSL_FEATURE_MCG_HAS_PLL1 (0) 1363 /* @brief Has 48MHz internal oscillator. */ 1364 #define FSL_FEATURE_MCG_HAS_IRC_48M (0) 1365 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ 1366 #define FSL_FEATURE_MCG_HAS_OSC1 (0) 1367 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ 1368 #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) 1369 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ 1370 #define FSL_FEATURE_MCG_HAS_LOLRE (1) 1371 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ 1372 #define FSL_FEATURE_MCG_USE_OSCSEL (0) 1373 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ 1374 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) 1375 /* @brief TBD */ 1376 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) 1377 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ 1378 #define FSL_FEATURE_MCG_HAS_PLL (1) 1379 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ 1380 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1) 1381 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ 1382 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (1) 1383 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ 1384 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) 1385 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ 1386 #define FSL_FEATURE_MCG_HAS_FLL (1) 1387 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ 1388 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) 1389 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ 1390 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) 1391 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ 1392 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) 1393 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ 1394 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) 1395 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ 1396 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) 1397 /* @brief Has external clock monitor (register bit C6[CME]). */ 1398 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) 1399 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ 1400 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) 1401 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ 1402 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) 1403 /* @brief Has PEI mode or PBI mode. */ 1404 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) 1405 /* @brief Reset clock mode is BLPI. */ 1406 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0) 1407 1408 /* MSCM module features */ 1409 1410 /* @brief Number of configuration information for processors. */ 1411 #define FSL_FEATURE_MSCM_HAS_CP_COUNT (2) 1412 /* @brief Has data cache. */ 1413 #define FSL_FEATURE_MSCM_HAS_DATACACHE (0) 1414 1415 /* interrupt module features */ 1416 1417 /* @brief Lowest interrupt request number. */ 1418 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 1419 /* @brief Highest interrupt request number. */ 1420 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (120) 1421 1422 /* OSC module features */ 1423 1424 /* @brief Has OSC1 external oscillator. */ 1425 #define FSL_FEATURE_OSC_HAS_OSC1 (0) 1426 /* @brief Has OSC0 external oscillator. */ 1427 #define FSL_FEATURE_OSC_HAS_OSC0 (0) 1428 /* @brief Has OSC external oscillator (without index). */ 1429 #define FSL_FEATURE_OSC_HAS_OSC (0) 1430 /* @brief Number of OSC external oscillators. */ 1431 #define FSL_FEATURE_OSC_OSC_COUNT (0) 1432 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ 1433 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (1) 1434 1435 /* PDB module features */ 1436 1437 /* @brief Has DAC support. */ 1438 #define FSL_FEATURE_PDB_HAS_DAC (1) 1439 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1440 #define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) 1441 /* @brief PDB channel number). */ 1442 #define FSL_FEATURE_PDB_CHANNEL_COUNT (2) 1443 /* @brief Channel pre-trigger nunmber (related to number of registers CHmDLYn). */ 1444 #define FSL_FEATURE_PDB_CHANNEL_PRE_TRIGGER_COUNT (2) 1445 /* @brief DAC interval trigger number). */ 1446 #define FSL_FEATURE_PDB_DAC_INTERVAL_TRIGGER_COUNT (1) 1447 /* @brief Pulse out number). */ 1448 #define FSL_FEATURE_PDB_PULSE_OUT_COUNT (2) 1449 1450 /* PIT module features */ 1451 1452 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 1453 #define FSL_FEATURE_PIT_TIMER_COUNT (4) 1454 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 1455 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) 1456 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 1457 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) 1458 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1459 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) 1460 /* @brief Has timer enable control. */ 1461 #define FSL_FEATURE_PIT_HAS_MDIS (1) 1462 1463 /* PMC module features */ 1464 1465 /* @brief Has Bandgap Enable In VLPx Operation support. */ 1466 #define FSL_FEATURE_PMC_HAS_BGEN (1) 1467 /* @brief Has Bandgap Buffer Enable. */ 1468 #define FSL_FEATURE_PMC_HAS_BGBE (1) 1469 /* @brief Has Bandgap Buffer Drive Select. */ 1470 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 1471 /* @brief Has Low-Voltage Detect Voltage Select support. */ 1472 #define FSL_FEATURE_PMC_HAS_LVDV (1) 1473 /* @brief Has Low-Voltage Warning Voltage Select support. */ 1474 #define FSL_FEATURE_PMC_HAS_LVWV (1) 1475 /* @brief Has LPO. */ 1476 #define FSL_FEATURE_PMC_HAS_LPO (0) 1477 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 1478 #define FSL_FEATURE_PMC_HAS_VLPO (0) 1479 /* @brief Has acknowledge isolation support. */ 1480 #define FSL_FEATURE_PMC_HAS_ACKISO (1) 1481 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 1482 #define FSL_FEATURE_PMC_HAS_REGFPM (0) 1483 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 1484 #define FSL_FEATURE_PMC_HAS_REGONS (1) 1485 /* @brief Has PMC_HVDSC1. */ 1486 #define FSL_FEATURE_PMC_HAS_HVDSC1 (1) 1487 /* @brief Has PMC_PARAM. */ 1488 #define FSL_FEATURE_PMC_HAS_PARAM (0) 1489 /* @brief Has PMC_VERID. */ 1490 #define FSL_FEATURE_PMC_HAS_VERID (0) 1491 1492 /* PORT module features */ 1493 1494 /* @brief Has control lock (register bit PCR[LK]). */ 1495 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) 1496 /* @brief Has open drain control (register bit PCR[ODE]). */ 1497 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) 1498 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 1499 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) 1500 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 1501 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 1502 /* @brief Has pull resistor selection available. */ 1503 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 1504 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 1505 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 1506 /* @brief Has slew rate control (register bit PCR[SRE]). */ 1507 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) 1508 /* @brief Has passive filter (register bit field PCR[PFE]). */ 1509 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 1510 /* @brief Has drive strength control (register bit PCR[DSE]). */ 1511 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 1512 /* @brief Has separate drive strength register (HDRVE). */ 1513 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 1514 /* @brief Has glitch filter (register IOFLT). */ 1515 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 1516 /* @brief Defines width of PCR[MUX] field. */ 1517 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) 1518 /* @brief Has dedicated interrupt vector. */ 1519 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 1520 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 1521 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) 1522 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 1523 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 1524 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 1525 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 1526 1527 /* PWM module features */ 1528 1529 /* @brief If EflexPWM has module A channels (outputs). */ 1530 #define FSL_FEATURE_PWM_HAS_CHANNELA (1) 1531 /* @brief If EflexPWM has module B channels (outputs). */ 1532 #define FSL_FEATURE_PWM_HAS_CHANNELB (1) 1533 /* @brief If EflexPWM has module X channels (outputs). */ 1534 #define FSL_FEATURE_PWM_HAS_CHANNELX (1) 1535 /* @brief Number of submodules in each EflexPWM module. */ 1536 #define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U) 1537 1538 /* RCM module features */ 1539 1540 /* @brief Has Loss-of-Lock Reset support. */ 1541 #define FSL_FEATURE_RCM_HAS_LOL (1) 1542 /* @brief Has Loss-of-Clock Reset support. */ 1543 #define FSL_FEATURE_RCM_HAS_LOC (1) 1544 /* @brief Has JTAG generated Reset support. */ 1545 #define FSL_FEATURE_RCM_HAS_JTAG (1) 1546 /* @brief Has EzPort generated Reset support. */ 1547 #define FSL_FEATURE_RCM_HAS_EZPORT (0) 1548 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 1549 #define FSL_FEATURE_RCM_HAS_EZPMS (0) 1550 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 1551 #define FSL_FEATURE_RCM_HAS_BOOTROM (0) 1552 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 1553 #define FSL_FEATURE_RCM_HAS_SSRS (1) 1554 /* @brief Has Version ID Register (RCM_VERID). */ 1555 #define FSL_FEATURE_RCM_HAS_VERID (0) 1556 /* @brief Has Parameter Register (RCM_PARAM). */ 1557 #define FSL_FEATURE_RCM_HAS_PARAM (0) 1558 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 1559 #define FSL_FEATURE_RCM_HAS_SRIE (0) 1560 /* @brief Width of registers of the RCM. */ 1561 #define FSL_FEATURE_RCM_REG_WIDTH (8) 1562 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 1563 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 1564 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ 1565 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 1566 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 1567 #define FSL_FEATURE_RCM_HAS_WAKEUP (1) 1568 1569 /* SIM module features */ 1570 1571 /* @brief Has USB FS divider. */ 1572 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) 1573 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ 1574 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) 1575 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ 1576 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) 1577 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ 1578 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) 1579 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ 1580 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) 1581 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ 1582 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) 1583 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ 1584 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) 1585 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ 1586 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) 1587 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ 1588 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) 1589 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ 1590 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) 1591 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ 1592 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) 1593 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ 1594 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) 1595 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ 1596 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) 1597 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ 1598 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) 1599 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ 1600 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0) 1601 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ 1602 #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) 1603 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ 1604 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) 1605 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ 1606 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) 1607 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ 1608 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) 1609 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ 1610 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) 1611 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ 1612 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) 1613 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ 1614 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) 1615 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ 1616 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) 1617 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ 1618 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) 1619 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ 1620 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) 1621 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ 1622 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) 1623 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ 1624 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) 1625 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ 1626 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) 1627 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ 1628 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) 1629 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ 1630 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) 1631 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ 1632 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) 1633 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ 1634 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) 1635 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ 1636 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) 1637 /* @brief Has FTM module(s) configuration. */ 1638 #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) 1639 /* @brief Number of FTM modules. */ 1640 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) 1641 /* @brief Number of FTM triggers with selectable source. */ 1642 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (3) 1643 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ 1644 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) 1645 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ 1646 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) 1647 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ 1648 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) 1649 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ 1650 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) 1651 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ 1652 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) 1653 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ 1654 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) 1655 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ 1656 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4) 1657 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ 1658 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) 1659 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ 1660 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) 1661 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ 1662 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) 1663 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ 1664 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) 1665 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ 1666 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) 1667 /* @brief Has TPM module(s) configuration. */ 1668 #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) 1669 /* @brief The highest TPM module index. */ 1670 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) 1671 /* @brief Has TPM module with index 0. */ 1672 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) 1673 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ 1674 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) 1675 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ 1676 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) 1677 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1678 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) 1679 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ 1680 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) 1681 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1682 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) 1683 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ 1684 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) 1685 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ 1686 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) 1687 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ 1688 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) 1689 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ 1690 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) 1691 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ 1692 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) 1693 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ 1694 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) 1695 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ 1696 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) 1697 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ 1698 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) 1699 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ 1700 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1) 1701 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ 1702 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1) 1703 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ 1704 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) 1705 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ 1706 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) 1707 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ 1708 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) 1709 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ 1710 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) 1711 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ 1712 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) 1713 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ 1714 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) 1715 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ 1716 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) 1717 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ 1718 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) 1719 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ 1720 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) 1721 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ 1722 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) 1723 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ 1724 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (0) 1725 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register ADCOPT). */ 1726 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (2) 1727 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register ADCOPT). */ 1728 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) 1729 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register ADCOPT). */ 1730 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) 1731 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register ADCOPT). */ 1732 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) 1733 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ 1734 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (2) 1735 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ 1736 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (2) 1737 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ 1738 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) 1739 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ 1740 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (2) 1741 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ 1742 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (2) 1743 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ 1744 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) 1745 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ 1746 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) 1747 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ 1748 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) 1749 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ 1750 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) 1751 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ 1752 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) 1753 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ 1754 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) 1755 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ 1756 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) 1757 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ 1758 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) 1759 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ 1760 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) 1761 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ 1762 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) 1763 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ 1764 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) 1765 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ 1766 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1) 1767 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ 1768 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) 1769 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ 1770 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) 1771 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ 1772 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) 1773 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ 1774 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) 1775 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ 1776 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) 1777 /* @brief Has device die ID (register bit field SDID[DIEID]). */ 1778 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) 1779 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ 1780 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) 1781 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ 1782 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) 1783 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ 1784 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) 1785 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ 1786 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) 1787 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ 1788 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) 1789 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ 1790 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) 1791 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ 1792 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) 1793 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ 1794 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) 1795 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ 1796 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) 1797 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ 1798 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) 1799 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ 1800 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) 1801 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ 1802 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) 1803 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ 1804 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) 1805 /* @brief Has miscellanious control register (register MCR). */ 1806 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) 1807 /* @brief Has COP watchdog (registers COPC and SRVCOP). */ 1808 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) 1809 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ 1810 #define FSL_FEATURE_SIM_HAS_COP_STOP (0) 1811 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ 1812 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) 1813 /* @brief Has UIDH registers. */ 1814 #define FSL_FEATURE_SIM_HAS_UIDH (1) 1815 /* @brief Has UIDM registers. */ 1816 #define FSL_FEATURE_SIM_HAS_UIDM (0) 1817 1818 /* SMC module features */ 1819 1820 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 1821 #define FSL_FEATURE_SMC_HAS_PSTOPO (1) 1822 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 1823 #define FSL_FEATURE_SMC_HAS_LPOPO (1) 1824 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 1825 #define FSL_FEATURE_SMC_HAS_PORPO (1) 1826 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 1827 #define FSL_FEATURE_SMC_HAS_LPWUI (0) 1828 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 1829 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) 1830 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 1831 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) 1832 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 1833 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1) 1834 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 1835 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1) 1836 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 1837 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) 1838 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 1839 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (0) 1840 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 1841 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) 1842 /* @brief Has stop submode. */ 1843 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) 1844 /* @brief Has stop submode 0(VLLS0). */ 1845 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) 1846 /* @brief Has stop submode 1(VLLS1). */ 1847 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1) 1848 /* @brief Has stop submode 2(VLLS2). */ 1849 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) 1850 /* @brief Has SMC_PARAM. */ 1851 #define FSL_FEATURE_SMC_HAS_PARAM (0) 1852 /* @brief Has SMC_VERID. */ 1853 #define FSL_FEATURE_SMC_HAS_VERID (0) 1854 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 1855 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 1856 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 1857 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) 1858 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 1859 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) 1860 /* @brief Width of SMC registers. */ 1861 #define FSL_FEATURE_SMC_REG_WIDTH (8) 1862 1863 /* DSPI module features */ 1864 1865 /* @brief Receive/transmit FIFO size in number of items. */ 1866 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) 1867 /* @brief Maximum transfer data width in bits. */ 1868 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) 1869 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ 1870 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) 1871 /* @brief Number of chip select pins. */ 1872 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) 1873 /* @brief Number of CTAR registers. */ 1874 #define FSL_FEATURE_DSPI_CTAR_COUNT (2) 1875 /* @brief Has chip select strobe capability on the PCS5 pin. */ 1876 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) 1877 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 1878 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 1879 /* @brief Has 16-bit data transfer support. */ 1880 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) 1881 /* @brief Has separate DMA RX and TX requests. */ 1882 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1883 1884 /* SYSMPU module features */ 1885 1886 /* @brief Specifies number of descriptors available. */ 1887 #define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (12) 1888 /* @brief Has process identifier support. */ 1889 #define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1) 1890 /* @brief Total number of MPU slave. */ 1891 #define FSL_FEATURE_SYSMPU_SLAVE_COUNT (5) 1892 /* @brief Total number of MPU master. */ 1893 #define FSL_FEATURE_SYSMPU_MASTER_COUNT (4) 1894 1895 /* SCB module features */ 1896 1897 /* @brief L1 ICACHE line size in byte. */ 1898 #define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32) 1899 /* @brief L1 DCACHE line size in byte. */ 1900 #define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32) 1901 1902 /* SysTick module features */ 1903 1904 /* @brief Systick has external reference clock. */ 1905 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) 1906 /* @brief Systick external reference clock is core clock divided by this value. */ 1907 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) 1908 1909 /* UART module features */ 1910 1911 #if defined(CPU_MKV58F1M0VLL24) || defined(CPU_MKV58F512VLL24) 1912 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 1913 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) 1914 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 1915 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 1916 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 1917 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 1918 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1919 #define FSL_FEATURE_UART_HAS_FIFO (1) 1920 /* @brief Hardware flow control (RTS, CTS) is supported. */ 1921 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) 1922 /* @brief Infrared (modulation) is supported. */ 1923 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) 1924 /* @brief 2 bits long stop bit is available. */ 1925 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 1926 /* @brief If 10-bit mode is supported. */ 1927 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) 1928 /* @brief Baud rate fine adjustment is available. */ 1929 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) 1930 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 1931 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 1932 /* @brief Baud rate oversampling is available. */ 1933 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) 1934 /* @brief Baud rate oversampling is available. */ 1935 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) 1936 /* @brief Peripheral type. */ 1937 #define FSL_FEATURE_UART_IS_SCI (0) 1938 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1939 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ 1940 (((x) == UART0) ? (8) : \ 1941 (((x) == UART1) ? (8) : \ 1942 (((x) == UART2) ? (1) : \ 1943 (((x) == UART3) ? (1) : \ 1944 (((x) == UART4) ? (1) : (-1)))))) 1945 /* @brief Supports two match addresses to filter incoming frames. */ 1946 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) 1947 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 1948 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 1949 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 1950 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) 1951 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 1952 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) 1953 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 1954 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) 1955 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1956 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1) 1957 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1958 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1959 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1960 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 1961 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 1962 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) 1963 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1964 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) 1965 /* @brief Has separate DMA RX and TX requests. */ 1966 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1967 #elif defined(CPU_MKV58F1M0VLQ24) || defined(CPU_MKV58F1M0VMD24) || defined(CPU_MKV58F512VLQ24) || defined(CPU_MKV58F512VMD24) 1968 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 1969 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) 1970 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 1971 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 1972 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 1973 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 1974 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1975 #define FSL_FEATURE_UART_HAS_FIFO (1) 1976 /* @brief Hardware flow control (RTS, CTS) is supported. */ 1977 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) 1978 /* @brief Infrared (modulation) is supported. */ 1979 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) 1980 /* @brief 2 bits long stop bit is available. */ 1981 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 1982 /* @brief If 10-bit mode is supported. */ 1983 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) 1984 /* @brief Baud rate fine adjustment is available. */ 1985 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) 1986 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 1987 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 1988 /* @brief Baud rate oversampling is available. */ 1989 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) 1990 /* @brief Baud rate oversampling is available. */ 1991 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) 1992 /* @brief Peripheral type. */ 1993 #define FSL_FEATURE_UART_IS_SCI (0) 1994 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1995 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ 1996 (((x) == UART0) ? (8) : \ 1997 (((x) == UART1) ? (8) : \ 1998 (((x) == UART2) ? (1) : \ 1999 (((x) == UART3) ? (1) : \ 2000 (((x) == UART4) ? (1) : \ 2001 (((x) == UART5) ? (1) : (-1))))))) 2002 /* @brief Supports two match addresses to filter incoming frames. */ 2003 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) 2004 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 2005 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 2006 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 2007 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) 2008 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 2009 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) 2010 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 2011 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) 2012 /* @brief Has improved smart card (ISO7816 protocol) support. */ 2013 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1) 2014 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 2015 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 2016 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 2017 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 2018 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 2019 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) 2020 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 2021 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) 2022 /* @brief Has separate DMA RX and TX requests. */ 2023 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 2024 #endif /* defined(CPU_MKV58F1M0VLL24) || defined(CPU_MKV58F512VLL24) */ 2025 2026 /* WDOG module features */ 2027 2028 /* @brief Watchdog is available. */ 2029 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 2030 /* @brief Has Wait mode support. */ 2031 #define FSL_FEATURE_WDOG_HAS_WAITEN (1) 2032 2033 /* XBARA module features */ 2034 2035 /* @brief Number of interrupt requests. */ 2036 #define FSL_FEATURE_XBARA_INTERRUPT_COUNT (4) 2037 2038 /* XBARB module features */ 2039 2040 /* @brief Number of interrupt requests. */ 2041 #define FSL_FEATURE_XBARB_INTERRUPT_COUNT (0) 2042 2043 #endif /* _MKV58F24_FEATURES_H_ */ 2044 2045
