1 /* 2 ** ################################################################### 3 ** Version: rev. 0.3, 2015-06-08 4 ** Build: b210910 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2021 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 0.1 (2015-02-24) 20 ** Initial version. 21 ** - rev. 0.2 (2015-05-25) 22 ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 23 ** - rev. 0.3 (2015-06-08) 24 ** FTM features BUS_CLOCK and FAST_CLOCK removed. 25 ** 26 ** ################################################################### 27 */ 28 29 #ifndef _MKV56F24_FEATURES_H_ 30 #define _MKV56F24_FEATURES_H_ 31 32 /* SOC module features */ 33 34 #if defined(CPU_MKV56F1M0VLL24) || defined(CPU_MKV56F512VLL24) 35 /* @brief ADC16 availability on the SoC. */ 36 #define FSL_FEATURE_SOC_ADC16_COUNT (1) 37 /* @brief AIPS availability on the SoC. */ 38 #define FSL_FEATURE_SOC_AIPS_COUNT (2) 39 /* @brief AOI availability on the SoC. */ 40 #define FSL_FEATURE_SOC_AOI_COUNT (1) 41 /* @brief AXBS availability on the SoC. */ 42 #define FSL_FEATURE_SOC_AXBS_COUNT (1) 43 /* @brief FLEXCAN availability on the SoC. */ 44 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) 45 /* @brief MMCAU availability on the SoC. */ 46 #define FSL_FEATURE_SOC_MMCAU_COUNT (1) 47 /* @brief CMP availability on the SoC. */ 48 #define FSL_FEATURE_SOC_CMP_COUNT (4) 49 /* @brief CRC availability on the SoC. */ 50 #define FSL_FEATURE_SOC_CRC_COUNT (1) 51 /* @brief DAC availability on the SoC. */ 52 #define FSL_FEATURE_SOC_DAC_COUNT (1) 53 /* @brief EDMA availability on the SoC. */ 54 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 55 /* @brief DMAMUX availability on the SoC. */ 56 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 57 /* @brief DSPI availability on the SoC. */ 58 #define FSL_FEATURE_SOC_DSPI_COUNT (3) 59 /* @brief ENC availability on the SoC. */ 60 #define FSL_FEATURE_SOC_ENC_COUNT (1) 61 /* @brief EWM availability on the SoC. */ 62 #define FSL_FEATURE_SOC_EWM_COUNT (1) 63 /* @brief FB availability on the SoC. */ 64 #define FSL_FEATURE_SOC_FB_COUNT (1) 65 /* @brief FMC availability on the SoC. */ 66 #define FSL_FEATURE_SOC_FMC_COUNT (1) 67 /* @brief FTFE availability on the SoC. */ 68 #define FSL_FEATURE_SOC_FTFE_COUNT (1) 69 /* @brief FTM availability on the SoC. */ 70 #define FSL_FEATURE_SOC_FTM_COUNT (4) 71 /* @brief GPIO availability on the SoC. */ 72 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 73 /* @brief HSADC availability on the SoC. */ 74 #define FSL_FEATURE_SOC_HSADC_COUNT (2) 75 /* @brief I2C availability on the SoC. */ 76 #define FSL_FEATURE_SOC_I2C_COUNT (2) 77 /* @brief LLWU availability on the SoC. */ 78 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 79 /* @brief LPTMR availability on the SoC. */ 80 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 81 /* @brief MCG availability on the SoC. */ 82 #define FSL_FEATURE_SOC_MCG_COUNT (1) 83 /* @brief MCM availability on the SoC. */ 84 #define FSL_FEATURE_SOC_MCM_COUNT (1) 85 /* @brief SYSMPU availability on the SoC. */ 86 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1) 87 /* @brief MSCM availability on the SoC. */ 88 #define FSL_FEATURE_SOC_MSCM_COUNT (1) 89 /* @brief OSC availability on the SoC. */ 90 #define FSL_FEATURE_SOC_OSC_COUNT (1) 91 /* @brief PDB availability on the SoC. */ 92 #define FSL_FEATURE_SOC_PDB_COUNT (2) 93 /* @brief PIT availability on the SoC. */ 94 #define FSL_FEATURE_SOC_PIT_COUNT (1) 95 /* @brief PMC availability on the SoC. */ 96 #define FSL_FEATURE_SOC_PMC_COUNT (1) 97 /* @brief PORT availability on the SoC. */ 98 #define FSL_FEATURE_SOC_PORT_COUNT (5) 99 /* @brief PWM availability on the SoC. */ 100 #define FSL_FEATURE_SOC_PWM_COUNT (2) 101 /* @brief RCM availability on the SoC. */ 102 #define FSL_FEATURE_SOC_RCM_COUNT (1) 103 /* @brief RFSYS availability on the SoC. */ 104 #define FSL_FEATURE_SOC_RFSYS_COUNT (1) 105 /* @brief RFVBAT availability on the SoC. */ 106 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) 107 /* @brief SIM availability on the SoC. */ 108 #define FSL_FEATURE_SOC_SIM_COUNT (1) 109 /* @brief SMC availability on the SoC. */ 110 #define FSL_FEATURE_SOC_SMC_COUNT (1) 111 /* @brief TRNG availability on the SoC. */ 112 #define FSL_FEATURE_SOC_TRNG_COUNT (1) 113 /* @brief UART availability on the SoC. */ 114 #define FSL_FEATURE_SOC_UART_COUNT (5) 115 /* @brief WDOG availability on the SoC. */ 116 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 117 /* @brief XBARA availability on the SoC. */ 118 #define FSL_FEATURE_SOC_XBARA_COUNT (1) 119 /* @brief XBARB availability on the SoC. */ 120 #define FSL_FEATURE_SOC_XBARB_COUNT (1) 121 #elif defined(CPU_MKV56F1M0VLQ24) || defined(CPU_MKV56F1M0VMD24) || defined(CPU_MKV56F512VLQ24) || defined(CPU_MKV56F512VMD24) 122 /* @brief ADC16 availability on the SoC. */ 123 #define FSL_FEATURE_SOC_ADC16_COUNT (1) 124 /* @brief AIPS availability on the SoC. */ 125 #define FSL_FEATURE_SOC_AIPS_COUNT (2) 126 /* @brief AOI availability on the SoC. */ 127 #define FSL_FEATURE_SOC_AOI_COUNT (1) 128 /* @brief AXBS availability on the SoC. */ 129 #define FSL_FEATURE_SOC_AXBS_COUNT (1) 130 /* @brief FLEXCAN availability on the SoC. */ 131 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) 132 /* @brief MMCAU availability on the SoC. */ 133 #define FSL_FEATURE_SOC_MMCAU_COUNT (1) 134 /* @brief CMP availability on the SoC. */ 135 #define FSL_FEATURE_SOC_CMP_COUNT (4) 136 /* @brief CRC availability on the SoC. */ 137 #define FSL_FEATURE_SOC_CRC_COUNT (1) 138 /* @brief DAC availability on the SoC. */ 139 #define FSL_FEATURE_SOC_DAC_COUNT (1) 140 /* @brief EDMA availability on the SoC. */ 141 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 142 /* @brief DMAMUX availability on the SoC. */ 143 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 144 /* @brief DSPI availability on the SoC. */ 145 #define FSL_FEATURE_SOC_DSPI_COUNT (3) 146 /* @brief ENC availability on the SoC. */ 147 #define FSL_FEATURE_SOC_ENC_COUNT (1) 148 /* @brief EWM availability on the SoC. */ 149 #define FSL_FEATURE_SOC_EWM_COUNT (1) 150 /* @brief FB availability on the SoC. */ 151 #define FSL_FEATURE_SOC_FB_COUNT (1) 152 /* @brief FMC availability on the SoC. */ 153 #define FSL_FEATURE_SOC_FMC_COUNT (1) 154 /* @brief FTFE availability on the SoC. */ 155 #define FSL_FEATURE_SOC_FTFE_COUNT (1) 156 /* @brief FTM availability on the SoC. */ 157 #define FSL_FEATURE_SOC_FTM_COUNT (4) 158 /* @brief GPIO availability on the SoC. */ 159 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 160 /* @brief HSADC availability on the SoC. */ 161 #define FSL_FEATURE_SOC_HSADC_COUNT (2) 162 /* @brief I2C availability on the SoC. */ 163 #define FSL_FEATURE_SOC_I2C_COUNT (2) 164 /* @brief LLWU availability on the SoC. */ 165 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 166 /* @brief LPTMR availability on the SoC. */ 167 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 168 /* @brief MCG availability on the SoC. */ 169 #define FSL_FEATURE_SOC_MCG_COUNT (1) 170 /* @brief MCM availability on the SoC. */ 171 #define FSL_FEATURE_SOC_MCM_COUNT (1) 172 /* @brief SYSMPU availability on the SoC. */ 173 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1) 174 /* @brief MSCM availability on the SoC. */ 175 #define FSL_FEATURE_SOC_MSCM_COUNT (1) 176 /* @brief OSC availability on the SoC. */ 177 #define FSL_FEATURE_SOC_OSC_COUNT (1) 178 /* @brief PDB availability on the SoC. */ 179 #define FSL_FEATURE_SOC_PDB_COUNT (2) 180 /* @brief PIT availability on the SoC. */ 181 #define FSL_FEATURE_SOC_PIT_COUNT (1) 182 /* @brief PMC availability on the SoC. */ 183 #define FSL_FEATURE_SOC_PMC_COUNT (1) 184 /* @brief PORT availability on the SoC. */ 185 #define FSL_FEATURE_SOC_PORT_COUNT (5) 186 /* @brief PWM availability on the SoC. */ 187 #define FSL_FEATURE_SOC_PWM_COUNT (2) 188 /* @brief RCM availability on the SoC. */ 189 #define FSL_FEATURE_SOC_RCM_COUNT (1) 190 /* @brief RFSYS availability on the SoC. */ 191 #define FSL_FEATURE_SOC_RFSYS_COUNT (1) 192 /* @brief RFVBAT availability on the SoC. */ 193 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) 194 /* @brief SIM availability on the SoC. */ 195 #define FSL_FEATURE_SOC_SIM_COUNT (1) 196 /* @brief SMC availability on the SoC. */ 197 #define FSL_FEATURE_SOC_SMC_COUNT (1) 198 /* @brief TRNG availability on the SoC. */ 199 #define FSL_FEATURE_SOC_TRNG_COUNT (1) 200 /* @brief UART availability on the SoC. */ 201 #define FSL_FEATURE_SOC_UART_COUNT (6) 202 /* @brief WDOG availability on the SoC. */ 203 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 204 /* @brief XBARA availability on the SoC. */ 205 #define FSL_FEATURE_SOC_XBARA_COUNT (1) 206 /* @brief XBARB availability on the SoC. */ 207 #define FSL_FEATURE_SOC_XBARB_COUNT (1) 208 #endif 209 210 /* ADC16 module features */ 211 212 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ 213 #define FSL_FEATURE_ADC16_HAS_PGA (0) 214 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ 215 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) 216 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ 217 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) 218 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ 219 #define FSL_FEATURE_ADC16_HAS_DMA (1) 220 /* @brief Has differential mode (bitfield SC1x[DIFF]). */ 221 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) 222 /* @brief Has FIFO (bit SC4[AFDEP]). */ 223 #define FSL_FEATURE_ADC16_HAS_FIFO (0) 224 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ 225 #define FSL_FEATURE_ADC16_FIFO_SIZE (0) 226 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ 227 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) 228 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ 229 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) 230 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ 231 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) 232 /* @brief Has HW averaging (bit SC3[AVGE]). */ 233 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) 234 /* @brief Has offset correction (register OFS). */ 235 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) 236 /* @brief Maximum ADC resolution. */ 237 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) 238 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ 239 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) 240 241 /* AOI module features */ 242 243 /* @brief Maximum value of AOI0 input mux. */ 244 #define FSL_FEATURE_AOI_MODULE_INPUTS (4) 245 /* @brief Number of AOI0 events (related to number of registers AOI0_BFCRT01n/AOI0_BFCRT23n). */ 246 #define FSL_FEATURE_AOI_EVENT_COUNT (4) 247 248 /* FLEXCAN module features */ 249 250 /* @brief Message buffer size */ 251 #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (16) 252 /* @brief Has doze mode support (register bit field MCR[DOZE]). */ 253 #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) 254 /* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ 255 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1) 256 /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ 257 #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) 258 /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ 259 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) 260 /* @brief Instance has extended bit timing register (register CBT). */ 261 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) 262 /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 263 #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) 264 /* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 265 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) 266 /* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */ 267 #define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1) 268 /* @brief Has bitfield name BUF31TO0M. */ 269 #define FSL_FEATURE_FLEXCAN_HAS_BUF31TO0M (1) 270 /* @brief Number of interrupt vectors. */ 271 #define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6) 272 /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ 273 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) 274 275 /* CMP module features */ 276 277 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ 278 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) 279 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ 280 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) 281 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ 282 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) 283 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ 284 #define FSL_FEATURE_CMP_HAS_DMA (1) 285 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ 286 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) 287 /* @brief Has DAC Test function in CMP (register DACTEST). */ 288 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) 289 290 /* CRC module features */ 291 292 /* @brief Has data register with name CRC */ 293 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 294 295 /* DAC module features */ 296 297 /* @brief Define the size of hardware buffer */ 298 #define FSL_FEATURE_DAC_BUFFER_SIZE (16) 299 /* @brief Define whether the buffer supports watermark event detection or not. */ 300 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) 301 /* @brief Define whether the buffer supports watermark selection detection or not. */ 302 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) 303 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ 304 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) 305 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ 306 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) 307 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ 308 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) 309 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ 310 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) 311 /* @brief Define whether FIFO buffer mode is available or not. */ 312 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (1) 313 /* @brief Define whether swing buffer mode is available or not.. */ 314 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1) 315 316 /* EDMA module features */ 317 318 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 319 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (32) 320 /* @brief Total number of DMA channels on all modules. */ 321 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32) 322 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 323 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (2) 324 /* @brief Has DMA_Error interrupt vector. */ 325 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 326 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ 327 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32) 328 /* @brief Channel IRQ entry shared offset. */ 329 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (16) 330 /* @brief If 8 bytes transfer supported. */ 331 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (0) 332 /* @brief If 16 bytes transfer supported. */ 333 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) 334 335 /* DMAMUX module features */ 336 337 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 338 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32) 339 /* @brief Total number of DMA channels on all modules. */ 340 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (32) 341 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 342 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 343 /* @brief Register CHCFGn width. */ 344 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8) 345 346 /* ENC module features */ 347 348 /* @brief Has no simultaneous PHASEA and PHASEB change interrupt (register bit field CTRL2[SABIE] and CTRL2[SABIRQ]). */ 349 #define FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT (0) 350 /* @brief Has register CTRL3. */ 351 #define FSL_FEATURE_ENC_HAS_CTRL3 (0) 352 /* @brief Has register LASTEDGE or LASTEDGEH. */ 353 #define FSL_FEATURE_ENC_HAS_LASTEDGE (0) 354 /* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ 355 #define FSL_FEATURE_ENC_HAS_POSDPER (0) 356 357 /* EWM module features */ 358 359 /* @brief Has clock select (register CLKCTRL). */ 360 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) 361 /* @brief Has clock prescaler (register CLKPRESCALER). */ 362 #define FSL_FEATURE_EWM_HAS_PRESCALER (1) 363 364 /* FLEXBUS module features */ 365 366 /* No feature definitions */ 367 368 /* FLASH module features */ 369 370 #if defined(CPU_MKV56F1M0VLL24) || defined(CPU_MKV56F1M0VLQ24) || defined(CPU_MKV56F1M0VMD24) 371 /* @brief Is of type FTFA. */ 372 #define FSL_FEATURE_FLASH_IS_FTFA (0) 373 /* @brief Is of type FTFE. */ 374 #define FSL_FEATURE_FLASH_IS_FTFE (1) 375 /* @brief Is of type FTFL. */ 376 #define FSL_FEATURE_FLASH_IS_FTFL (0) 377 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 378 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) 379 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 380 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 381 /* @brief Has EEPROM region protection (register FEPROT). */ 382 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 383 /* @brief Has data flash region protection (register FDPROT). */ 384 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 385 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 386 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 387 /* @brief Has flash cache control in FMC module. */ 388 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 389 /* @brief Has flash cache control in MCM module. */ 390 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 391 /* @brief Has flash cache control in MSCM module. */ 392 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 393 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 394 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (1) 395 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 396 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 397 /* @brief P-Flash start address. */ 398 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x10000000) 399 /* @brief P-Flash block count. */ 400 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 401 /* @brief P-Flash block size. */ 402 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (1048576) 403 /* @brief P-Flash sector size. */ 404 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (8192) 405 /* @brief P-Flash write unit size. */ 406 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) 407 /* @brief P-Flash data path width. */ 408 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (32) 409 /* @brief P-Flash block swap feature. */ 410 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 411 /* @brief P-Flash protection region count. */ 412 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 413 /* @brief Has FlexNVM memory. */ 414 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 415 /* @brief Has FlexNVM alias. */ 416 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 417 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 418 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 419 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 420 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 421 /* @brief FlexNVM block count. */ 422 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 423 /* @brief FlexNVM block size. */ 424 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 425 /* @brief FlexNVM sector size. */ 426 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 427 /* @brief FlexNVM write unit size. */ 428 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 429 /* @brief FlexNVM data path width. */ 430 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 431 /* @brief Has FlexRAM memory. */ 432 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) 433 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 434 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x18000000) 435 /* @brief FlexRAM size. */ 436 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096) 437 /* @brief Has 0x00 Read 1s Block command. */ 438 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 439 /* @brief Has 0x01 Read 1s Section command. */ 440 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 441 /* @brief Has 0x02 Program Check command. */ 442 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 443 /* @brief Has 0x03 Read Resource command. */ 444 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 445 /* @brief Has 0x06 Program Longword command. */ 446 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) 447 /* @brief Has 0x07 Program Phrase command. */ 448 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) 449 /* @brief Has 0x08 Erase Flash Block command. */ 450 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 451 /* @brief Has 0x09 Erase Flash Sector command. */ 452 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 453 /* @brief Has 0x0B Program Section command. */ 454 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) 455 /* @brief Has 0x40 Read 1s All Blocks command. */ 456 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 457 /* @brief Has 0x41 Read Once command. */ 458 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 459 /* @brief Has 0x43 Program Once command. */ 460 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 461 /* @brief Has 0x44 Erase All Blocks command. */ 462 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 463 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 464 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 465 /* @brief Has 0x46 Swap Control command. */ 466 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 467 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 468 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) 469 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 470 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 471 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 472 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 473 /* @brief Has 0x80 Program Partition command. */ 474 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 475 /* @brief Has 0x81 Set FlexRAM Function command. */ 476 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 477 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 478 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (32) 479 /* @brief P-Flash Erase sector command address alignment. */ 480 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (32) 481 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 482 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (32) 483 /* @brief P-Flash Read resource command address alignment. */ 484 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) 485 /* @brief P-Flash Program check command address alignment. */ 486 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 487 /* @brief P-Flash Program check command address alignment. */ 488 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 489 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 490 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 491 /* @brief FlexNVM Erase sector command address alignment. */ 492 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 493 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 494 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 495 /* @brief FlexNVM Read resource command address alignment. */ 496 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 497 /* @brief FlexNVM Program check command address alignment. */ 498 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 499 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 500 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 501 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 502 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 503 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 504 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 505 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 506 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 507 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 508 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 509 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 510 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 511 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 512 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 513 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 514 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 515 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 516 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 517 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 518 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 519 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 520 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 521 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 522 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 523 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 524 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 525 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 526 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 527 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 528 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 529 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 530 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 531 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 532 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 533 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 534 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 535 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 536 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000) 537 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 538 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) 539 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 540 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) 541 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 542 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) 543 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 544 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) 545 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 546 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) 547 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 548 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) 549 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 550 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) 551 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 552 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 553 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 554 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 555 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 556 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 557 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 558 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 559 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 560 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 561 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 562 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) 563 #elif defined(CPU_MKV56F512VLL24) || defined(CPU_MKV56F512VLQ24) || defined(CPU_MKV56F512VMD24) 564 /* @brief Is of type FTFA. */ 565 #define FSL_FEATURE_FLASH_IS_FTFA (0) 566 /* @brief Is of type FTFE. */ 567 #define FSL_FEATURE_FLASH_IS_FTFE (1) 568 /* @brief Is of type FTFL. */ 569 #define FSL_FEATURE_FLASH_IS_FTFL (0) 570 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 571 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) 572 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 573 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 574 /* @brief Has EEPROM region protection (register FEPROT). */ 575 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 576 /* @brief Has data flash region protection (register FDPROT). */ 577 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 578 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 579 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 580 /* @brief Has flash cache control in FMC module. */ 581 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 582 /* @brief Has flash cache control in MCM module. */ 583 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 584 /* @brief Has flash cache control in MSCM module. */ 585 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 586 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 587 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (1) 588 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 589 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 590 /* @brief P-Flash start address. */ 591 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x10000000) 592 /* @brief P-Flash block count. */ 593 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 594 /* @brief P-Flash block size. */ 595 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288) 596 /* @brief P-Flash sector size. */ 597 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (8192) 598 /* @brief P-Flash write unit size. */ 599 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) 600 /* @brief P-Flash data path width. */ 601 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (32) 602 /* @brief P-Flash block swap feature. */ 603 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 604 /* @brief P-Flash protection region count. */ 605 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 606 /* @brief Has FlexNVM memory. */ 607 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 608 /* @brief Has FlexNVM alias. */ 609 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 610 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 611 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 612 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 613 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 614 /* @brief FlexNVM block count. */ 615 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 616 /* @brief FlexNVM block size. */ 617 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 618 /* @brief FlexNVM sector size. */ 619 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 620 /* @brief FlexNVM write unit size. */ 621 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 622 /* @brief FlexNVM data path width. */ 623 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 624 /* @brief Has FlexRAM memory. */ 625 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) 626 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 627 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x18000000) 628 /* @brief FlexRAM size. */ 629 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096) 630 /* @brief Has 0x00 Read 1s Block command. */ 631 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 632 /* @brief Has 0x01 Read 1s Section command. */ 633 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 634 /* @brief Has 0x02 Program Check command. */ 635 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 636 /* @brief Has 0x03 Read Resource command. */ 637 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 638 /* @brief Has 0x06 Program Longword command. */ 639 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) 640 /* @brief Has 0x07 Program Phrase command. */ 641 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) 642 /* @brief Has 0x08 Erase Flash Block command. */ 643 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 644 /* @brief Has 0x09 Erase Flash Sector command. */ 645 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 646 /* @brief Has 0x0B Program Section command. */ 647 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) 648 /* @brief Has 0x40 Read 1s All Blocks command. */ 649 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 650 /* @brief Has 0x41 Read Once command. */ 651 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 652 /* @brief Has 0x43 Program Once command. */ 653 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 654 /* @brief Has 0x44 Erase All Blocks command. */ 655 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 656 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 657 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 658 /* @brief Has 0x46 Swap Control command. */ 659 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 660 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 661 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) 662 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 663 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 664 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 665 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 666 /* @brief Has 0x80 Program Partition command. */ 667 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 668 /* @brief Has 0x81 Set FlexRAM Function command. */ 669 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 670 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 671 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (32) 672 /* @brief P-Flash Erase sector command address alignment. */ 673 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (32) 674 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 675 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (32) 676 /* @brief P-Flash Read resource command address alignment. */ 677 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) 678 /* @brief P-Flash Program check command address alignment. */ 679 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 680 /* @brief P-Flash Program check command address alignment. */ 681 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 682 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 683 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 684 /* @brief FlexNVM Erase sector command address alignment. */ 685 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 686 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 687 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 688 /* @brief FlexNVM Read resource command address alignment. */ 689 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 690 /* @brief FlexNVM Program check command address alignment. */ 691 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 692 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 693 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 694 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 695 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 696 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 697 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 698 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 699 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 700 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 701 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 702 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 703 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 704 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 705 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 706 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 707 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 708 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 709 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 710 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 711 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 712 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 713 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 714 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 715 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 716 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 717 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 718 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 719 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 720 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 721 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 722 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 723 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 724 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 725 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 726 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 727 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 728 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 729 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000) 730 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 731 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) 732 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 733 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) 734 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 735 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) 736 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 737 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) 738 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 739 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) 740 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 741 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) 742 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 743 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) 744 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 745 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 746 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 747 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 748 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 749 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 750 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 751 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 752 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 753 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 754 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 755 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) 756 #endif /* defined(CPU_MKV56F1M0VLL24) || defined(CPU_MKV56F1M0VLQ24) || defined(CPU_MKV56F1M0VMD24) */ 757 758 /* FTM module features */ 759 760 /* @brief Number of channels. */ 761 #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ 762 (((x) == FTM0) ? (8) : \ 763 (((x) == FTM1) ? (2) : \ 764 (((x) == FTM2) ? (2) : \ 765 (((x) == FTM3) ? (8) : (-1))))) 766 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 767 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) 768 /* @brief Has extended deadtime value. */ 769 #define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0) 770 /* @brief Enable pwm output for the module. */ 771 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0) 772 /* @brief Has half-cycle reload for the module. */ 773 #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0) 774 /* @brief Has reload interrupt. */ 775 #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0) 776 /* @brief Has reload initialization trigger. */ 777 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0) 778 /* @brief Has DMA support, bitfield CnSC[DMA]. */ 779 #define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1) 780 /* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */ 781 #define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (0) 782 /* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */ 783 #define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0) 784 /* @brief Has no QDCTRL. */ 785 #define FSL_FEATURE_FTM_HAS_NO_QDCTRL (0) 786 /* @brief If instance has only TPM function. */ 787 #define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0) 788 789 /* GPIO module features */ 790 791 /* @brief Has GPIO attribute checker register (GACR). */ 792 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) 793 794 /* I2C module features */ 795 796 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ 797 #define FSL_FEATURE_I2C_HAS_SMBUS (1) 798 /* @brief Maximum supported baud rate in kilobit per second. */ 799 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (100) 800 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ 801 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) 802 /* @brief Has DMA support (register bit C1[DMAEN]). */ 803 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) 804 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ 805 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) 806 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ 807 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) 808 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ 809 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) 810 /* @brief Maximum width of the glitch filter in number of bus clocks. */ 811 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) 812 /* @brief Has control of the drive capability of the I2C pins. */ 813 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) 814 /* @brief Has double buffering support (register S2). */ 815 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) 816 /* @brief Has double buffer enable. */ 817 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) 818 819 /* LLWU module features */ 820 821 #if defined(CPU_MKV56F1M0VLL24) || defined(CPU_MKV56F512VLL24) 822 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 823 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (22) 824 /* @brief Has pins 8-15 connected to LLWU device. */ 825 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 826 /* @brief Maximum number of internal modules connected to LLWU device. */ 827 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (4) 828 /* @brief Number of digital filters. */ 829 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 830 /* @brief Has MF register. */ 831 #define FSL_FEATURE_LLWU_HAS_MF (1) 832 /* @brief Has PF register. */ 833 #define FSL_FEATURE_LLWU_HAS_PF (1) 834 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 835 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 836 /* @brief Has no internal module wakeup flag register. */ 837 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 838 /* @brief Has external pin 0 connected to LLWU device. */ 839 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 840 /* @brief Index of port of external pin. */ 841 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) 842 /* @brief Number of external pin port on specified port. */ 843 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) 844 /* @brief Has external pin 1 connected to LLWU device. */ 845 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) 846 /* @brief Index of port of external pin. */ 847 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX) 848 /* @brief Number of external pin port on specified port. */ 849 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) 850 /* @brief Has external pin 2 connected to LLWU device. */ 851 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) 852 /* @brief Index of port of external pin. */ 853 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX) 854 /* @brief Number of external pin port on specified port. */ 855 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4) 856 /* @brief Has external pin 3 connected to LLWU device. */ 857 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 858 /* @brief Index of port of external pin. */ 859 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 860 /* @brief Number of external pin port on specified port. */ 861 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 862 /* @brief Has external pin 4 connected to LLWU device. */ 863 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 864 /* @brief Index of port of external pin. */ 865 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 866 /* @brief Number of external pin port on specified port. */ 867 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) 868 /* @brief Has external pin 5 connected to LLWU device. */ 869 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 870 /* @brief Index of port of external pin. */ 871 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 872 /* @brief Number of external pin port on specified port. */ 873 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 874 /* @brief Has external pin 6 connected to LLWU device. */ 875 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 876 /* @brief Index of port of external pin. */ 877 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 878 /* @brief Number of external pin port on specified port. */ 879 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 880 /* @brief Has external pin 7 connected to LLWU device. */ 881 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 882 /* @brief Index of port of external pin. */ 883 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 884 /* @brief Number of external pin port on specified port. */ 885 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 886 /* @brief Has external pin 8 connected to LLWU device. */ 887 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 888 /* @brief Index of port of external pin. */ 889 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 890 /* @brief Number of external pin port on specified port. */ 891 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 892 /* @brief Has external pin 9 connected to LLWU device. */ 893 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 894 /* @brief Index of port of external pin. */ 895 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 896 /* @brief Number of external pin port on specified port. */ 897 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 898 /* @brief Has external pin 10 connected to LLWU device. */ 899 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 900 /* @brief Index of port of external pin. */ 901 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 902 /* @brief Number of external pin port on specified port. */ 903 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 904 /* @brief Has external pin 11 connected to LLWU device. */ 905 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 906 /* @brief Index of port of external pin. */ 907 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) 908 /* @brief Number of external pin port on specified port. */ 909 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) 910 /* @brief Has external pin 12 connected to LLWU device. */ 911 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 912 /* @brief Index of port of external pin. */ 913 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 914 /* @brief Number of external pin port on specified port. */ 915 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 916 /* @brief Has external pin 13 connected to LLWU device. */ 917 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 918 /* @brief Index of port of external pin. */ 919 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 920 /* @brief Number of external pin port on specified port. */ 921 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 922 /* @brief Has external pin 14 connected to LLWU device. */ 923 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 924 /* @brief Index of port of external pin. */ 925 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 926 /* @brief Number of external pin port on specified port. */ 927 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 928 /* @brief Has external pin 15 connected to LLWU device. */ 929 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 930 /* @brief Index of port of external pin. */ 931 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 932 /* @brief Number of external pin port on specified port. */ 933 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 934 /* @brief Has external pin 16 connected to LLWU device. */ 935 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1) 936 /* @brief Index of port of external pin. */ 937 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOE_IDX) 938 /* @brief Number of external pin port on specified port. */ 939 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (6) 940 /* @brief Has external pin 17 connected to LLWU device. */ 941 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 942 /* @brief Index of port of external pin. */ 943 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 944 /* @brief Number of external pin port on specified port. */ 945 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 946 /* @brief Has external pin 18 connected to LLWU device. */ 947 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 948 /* @brief Index of port of external pin. */ 949 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 950 /* @brief Number of external pin port on specified port. */ 951 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 952 /* @brief Has external pin 19 connected to LLWU device. */ 953 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1) 954 /* @brief Index of port of external pin. */ 955 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOE_IDX) 956 /* @brief Number of external pin port on specified port. */ 957 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (17) 958 /* @brief Has external pin 20 connected to LLWU device. */ 959 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1) 960 /* @brief Index of port of external pin. */ 961 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOE_IDX) 962 /* @brief Number of external pin port on specified port. */ 963 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (18) 964 /* @brief Has external pin 21 connected to LLWU device. */ 965 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1) 966 /* @brief Index of port of external pin. */ 967 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX) 968 /* @brief Number of external pin port on specified port. */ 969 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (25) 970 /* @brief Has external pin 22 connected to LLWU device. */ 971 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 972 /* @brief Index of port of external pin. */ 973 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 974 /* @brief Number of external pin port on specified port. */ 975 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 976 /* @brief Has external pin 23 connected to LLWU device. */ 977 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 978 /* @brief Index of port of external pin. */ 979 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 980 /* @brief Number of external pin port on specified port. */ 981 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 982 /* @brief Has external pin 24 connected to LLWU device. */ 983 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 984 /* @brief Index of port of external pin. */ 985 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 986 /* @brief Number of external pin port on specified port. */ 987 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 988 /* @brief Has external pin 25 connected to LLWU device. */ 989 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 990 /* @brief Index of port of external pin. */ 991 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 992 /* @brief Number of external pin port on specified port. */ 993 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 994 /* @brief Has external pin 26 connected to LLWU device. */ 995 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 996 /* @brief Index of port of external pin. */ 997 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 998 /* @brief Number of external pin port on specified port. */ 999 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 1000 /* @brief Has external pin 27 connected to LLWU device. */ 1001 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 1002 /* @brief Index of port of external pin. */ 1003 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 1004 /* @brief Number of external pin port on specified port. */ 1005 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 1006 /* @brief Has external pin 28 connected to LLWU device. */ 1007 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 1008 /* @brief Index of port of external pin. */ 1009 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 1010 /* @brief Number of external pin port on specified port. */ 1011 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 1012 /* @brief Has external pin 29 connected to LLWU device. */ 1013 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 1014 /* @brief Index of port of external pin. */ 1015 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 1016 /* @brief Number of external pin port on specified port. */ 1017 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 1018 /* @brief Has external pin 30 connected to LLWU device. */ 1019 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 1020 /* @brief Index of port of external pin. */ 1021 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 1022 /* @brief Number of external pin port on specified port. */ 1023 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 1024 /* @brief Has external pin 31 connected to LLWU device. */ 1025 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 1026 /* @brief Index of port of external pin. */ 1027 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 1028 /* @brief Number of external pin port on specified port. */ 1029 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 1030 /* @brief Has internal module 0 connected to LLWU device. */ 1031 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 1032 /* @brief Has internal module 1 connected to LLWU device. */ 1033 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 1034 /* @brief Has internal module 2 connected to LLWU device. */ 1035 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 1036 /* @brief Has internal module 3 connected to LLWU device. */ 1037 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) 1038 /* @brief Has internal module 4 connected to LLWU device. */ 1039 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) 1040 /* @brief Has internal module 5 connected to LLWU device. */ 1041 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (0) 1042 /* @brief Has internal module 6 connected to LLWU device. */ 1043 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 1044 /* @brief Has internal module 7 connected to LLWU device. */ 1045 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (0) 1046 /* @brief Has Version ID Register (LLWU_VERID). */ 1047 #define FSL_FEATURE_LLWU_HAS_VERID (0) 1048 /* @brief Has Parameter Register (LLWU_PARAM). */ 1049 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 1050 /* @brief Width of registers of the LLWU. */ 1051 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 1052 /* @brief Has DMA Enable register (LLWU_DE). */ 1053 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 1054 #elif defined(CPU_MKV56F1M0VLQ24) || defined(CPU_MKV56F1M0VMD24) || defined(CPU_MKV56F512VLQ24) || defined(CPU_MKV56F512VMD24) 1055 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 1056 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (26) 1057 /* @brief Has pins 8-15 connected to LLWU device. */ 1058 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 1059 /* @brief Maximum number of internal modules connected to LLWU device. */ 1060 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (4) 1061 /* @brief Number of digital filters. */ 1062 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 1063 /* @brief Has MF register. */ 1064 #define FSL_FEATURE_LLWU_HAS_MF (1) 1065 /* @brief Has PF register. */ 1066 #define FSL_FEATURE_LLWU_HAS_PF (1) 1067 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 1068 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 1069 /* @brief Has no internal module wakeup flag register. */ 1070 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 1071 /* @brief Has external pin 0 connected to LLWU device. */ 1072 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 1073 /* @brief Index of port of external pin. */ 1074 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) 1075 /* @brief Number of external pin port on specified port. */ 1076 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) 1077 /* @brief Has external pin 1 connected to LLWU device. */ 1078 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) 1079 /* @brief Index of port of external pin. */ 1080 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX) 1081 /* @brief Number of external pin port on specified port. */ 1082 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) 1083 /* @brief Has external pin 2 connected to LLWU device. */ 1084 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) 1085 /* @brief Index of port of external pin. */ 1086 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX) 1087 /* @brief Number of external pin port on specified port. */ 1088 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4) 1089 /* @brief Has external pin 3 connected to LLWU device. */ 1090 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 1091 /* @brief Index of port of external pin. */ 1092 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 1093 /* @brief Number of external pin port on specified port. */ 1094 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 1095 /* @brief Has external pin 4 connected to LLWU device. */ 1096 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 1097 /* @brief Index of port of external pin. */ 1098 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 1099 /* @brief Number of external pin port on specified port. */ 1100 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) 1101 /* @brief Has external pin 5 connected to LLWU device. */ 1102 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 1103 /* @brief Index of port of external pin. */ 1104 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 1105 /* @brief Number of external pin port on specified port. */ 1106 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 1107 /* @brief Has external pin 6 connected to LLWU device. */ 1108 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 1109 /* @brief Index of port of external pin. */ 1110 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 1111 /* @brief Number of external pin port on specified port. */ 1112 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 1113 /* @brief Has external pin 7 connected to LLWU device. */ 1114 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 1115 /* @brief Index of port of external pin. */ 1116 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 1117 /* @brief Number of external pin port on specified port. */ 1118 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 1119 /* @brief Has external pin 8 connected to LLWU device. */ 1120 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 1121 /* @brief Index of port of external pin. */ 1122 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 1123 /* @brief Number of external pin port on specified port. */ 1124 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 1125 /* @brief Has external pin 9 connected to LLWU device. */ 1126 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 1127 /* @brief Index of port of external pin. */ 1128 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 1129 /* @brief Number of external pin port on specified port. */ 1130 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 1131 /* @brief Has external pin 10 connected to LLWU device. */ 1132 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 1133 /* @brief Index of port of external pin. */ 1134 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 1135 /* @brief Number of external pin port on specified port. */ 1136 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 1137 /* @brief Has external pin 11 connected to LLWU device. */ 1138 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 1139 /* @brief Index of port of external pin. */ 1140 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) 1141 /* @brief Number of external pin port on specified port. */ 1142 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) 1143 /* @brief Has external pin 12 connected to LLWU device. */ 1144 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 1145 /* @brief Index of port of external pin. */ 1146 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 1147 /* @brief Number of external pin port on specified port. */ 1148 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 1149 /* @brief Has external pin 13 connected to LLWU device. */ 1150 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 1151 /* @brief Index of port of external pin. */ 1152 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 1153 /* @brief Number of external pin port on specified port. */ 1154 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 1155 /* @brief Has external pin 14 connected to LLWU device. */ 1156 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 1157 /* @brief Index of port of external pin. */ 1158 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 1159 /* @brief Number of external pin port on specified port. */ 1160 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 1161 /* @brief Has external pin 15 connected to LLWU device. */ 1162 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 1163 /* @brief Index of port of external pin. */ 1164 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 1165 /* @brief Number of external pin port on specified port. */ 1166 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 1167 /* @brief Has external pin 16 connected to LLWU device. */ 1168 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1) 1169 /* @brief Index of port of external pin. */ 1170 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOE_IDX) 1171 /* @brief Number of external pin port on specified port. */ 1172 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (6) 1173 /* @brief Has external pin 17 connected to LLWU device. */ 1174 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1) 1175 /* @brief Index of port of external pin. */ 1176 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOE_IDX) 1177 /* @brief Number of external pin port on specified port. */ 1178 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (9) 1179 /* @brief Has external pin 18 connected to LLWU device. */ 1180 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1) 1181 /* @brief Index of port of external pin. */ 1182 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOE_IDX) 1183 /* @brief Number of external pin port on specified port. */ 1184 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (10) 1185 /* @brief Has external pin 19 connected to LLWU device. */ 1186 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1) 1187 /* @brief Index of port of external pin. */ 1188 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOE_IDX) 1189 /* @brief Number of external pin port on specified port. */ 1190 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (17) 1191 /* @brief Has external pin 20 connected to LLWU device. */ 1192 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1) 1193 /* @brief Index of port of external pin. */ 1194 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOE_IDX) 1195 /* @brief Number of external pin port on specified port. */ 1196 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (18) 1197 /* @brief Has external pin 21 connected to LLWU device. */ 1198 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1) 1199 /* @brief Index of port of external pin. */ 1200 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX) 1201 /* @brief Number of external pin port on specified port. */ 1202 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (25) 1203 /* @brief Has external pin 22 connected to LLWU device. */ 1204 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1) 1205 /* @brief Index of port of external pin. */ 1206 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOA_IDX) 1207 /* @brief Number of external pin port on specified port. */ 1208 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (10) 1209 /* @brief Has external pin 23 connected to LLWU device. */ 1210 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1) 1211 /* @brief Index of port of external pin. */ 1212 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOA_IDX) 1213 /* @brief Number of external pin port on specified port. */ 1214 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (11) 1215 /* @brief Has external pin 24 connected to LLWU device. */ 1216 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (1) 1217 /* @brief Index of port of external pin. */ 1218 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (GPIOD_IDX) 1219 /* @brief Number of external pin port on specified port. */ 1220 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (8) 1221 /* @brief Has external pin 25 connected to LLWU device. */ 1222 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (1) 1223 /* @brief Index of port of external pin. */ 1224 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (GPIOD_IDX) 1225 /* @brief Number of external pin port on specified port. */ 1226 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (11) 1227 /* @brief Has external pin 26 connected to LLWU device. */ 1228 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 1229 /* @brief Index of port of external pin. */ 1230 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 1231 /* @brief Number of external pin port on specified port. */ 1232 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 1233 /* @brief Has external pin 27 connected to LLWU device. */ 1234 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 1235 /* @brief Index of port of external pin. */ 1236 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 1237 /* @brief Number of external pin port on specified port. */ 1238 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 1239 /* @brief Has external pin 28 connected to LLWU device. */ 1240 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 1241 /* @brief Index of port of external pin. */ 1242 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 1243 /* @brief Number of external pin port on specified port. */ 1244 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 1245 /* @brief Has external pin 29 connected to LLWU device. */ 1246 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 1247 /* @brief Index of port of external pin. */ 1248 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 1249 /* @brief Number of external pin port on specified port. */ 1250 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 1251 /* @brief Has external pin 30 connected to LLWU device. */ 1252 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 1253 /* @brief Index of port of external pin. */ 1254 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 1255 /* @brief Number of external pin port on specified port. */ 1256 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 1257 /* @brief Has external pin 31 connected to LLWU device. */ 1258 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 1259 /* @brief Index of port of external pin. */ 1260 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 1261 /* @brief Number of external pin port on specified port. */ 1262 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 1263 /* @brief Has internal module 0 connected to LLWU device. */ 1264 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 1265 /* @brief Has internal module 1 connected to LLWU device. */ 1266 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 1267 /* @brief Has internal module 2 connected to LLWU device. */ 1268 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 1269 /* @brief Has internal module 3 connected to LLWU device. */ 1270 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) 1271 /* @brief Has internal module 4 connected to LLWU device. */ 1272 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) 1273 /* @brief Has internal module 5 connected to LLWU device. */ 1274 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (0) 1275 /* @brief Has internal module 6 connected to LLWU device. */ 1276 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 1277 /* @brief Has internal module 7 connected to LLWU device. */ 1278 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (0) 1279 /* @brief Has Version ID Register (LLWU_VERID). */ 1280 #define FSL_FEATURE_LLWU_HAS_VERID (0) 1281 /* @brief Has Parameter Register (LLWU_PARAM). */ 1282 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 1283 /* @brief Width of registers of the LLWU. */ 1284 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 1285 /* @brief Has DMA Enable register (LLWU_DE). */ 1286 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 1287 #endif /* defined(CPU_MKV56F1M0VLL24) || defined(CPU_MKV56F512VLL24) */ 1288 1289 /* LPTMR module features */ 1290 1291 /* @brief Has shared interrupt handler with another LPTMR module. */ 1292 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 1293 /* @brief Whether LPTMR counter is 32 bits width. */ 1294 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) 1295 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 1296 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) 1297 1298 /* MCG module features */ 1299 1300 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ 1301 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1) 1302 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ 1303 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (7) 1304 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ 1305 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (16) 1306 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */ 1307 #define FSL_FEATURE_MCG_PLL_REF_MIN (8000000) 1308 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */ 1309 #define FSL_FEATURE_MCG_PLL_REF_MAX (16000000) 1310 /* @brief The PLL clock is divided by 2 before VCO divider. */ 1311 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (1) 1312 /* @brief FRDIV supports 1280. */ 1313 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) 1314 /* @brief FRDIV supports 1536. */ 1315 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) 1316 /* @brief MCGFFCLK divider. */ 1317 #define FSL_FEATURE_MCG_FFCLK_DIV (1) 1318 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ 1319 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) 1320 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ 1321 #define FSL_FEATURE_MCG_HAS_RTC_32K (0) 1322 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ 1323 #define FSL_FEATURE_MCG_HAS_PLL1 (0) 1324 /* @brief Has 48MHz internal oscillator. */ 1325 #define FSL_FEATURE_MCG_HAS_IRC_48M (0) 1326 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ 1327 #define FSL_FEATURE_MCG_HAS_OSC1 (0) 1328 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ 1329 #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) 1330 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ 1331 #define FSL_FEATURE_MCG_HAS_LOLRE (1) 1332 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ 1333 #define FSL_FEATURE_MCG_USE_OSCSEL (0) 1334 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ 1335 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) 1336 /* @brief TBD */ 1337 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) 1338 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ 1339 #define FSL_FEATURE_MCG_HAS_PLL (1) 1340 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ 1341 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1) 1342 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ 1343 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (1) 1344 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ 1345 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) 1346 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ 1347 #define FSL_FEATURE_MCG_HAS_FLL (1) 1348 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ 1349 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) 1350 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ 1351 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) 1352 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ 1353 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) 1354 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ 1355 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) 1356 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ 1357 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) 1358 /* @brief Has external clock monitor (register bit C6[CME]). */ 1359 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) 1360 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ 1361 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) 1362 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ 1363 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) 1364 /* @brief Has PEI mode or PBI mode. */ 1365 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) 1366 /* @brief Reset clock mode is BLPI. */ 1367 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0) 1368 1369 /* MSCM module features */ 1370 1371 /* @brief Number of configuration information for processors. */ 1372 #define FSL_FEATURE_MSCM_HAS_CP_COUNT (2) 1373 /* @brief Has data cache. */ 1374 #define FSL_FEATURE_MSCM_HAS_DATACACHE (0) 1375 1376 /* interrupt module features */ 1377 1378 /* @brief Lowest interrupt request number. */ 1379 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 1380 /* @brief Highest interrupt request number. */ 1381 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (114) 1382 1383 /* OSC module features */ 1384 1385 /* @brief Has OSC1 external oscillator. */ 1386 #define FSL_FEATURE_OSC_HAS_OSC1 (0) 1387 /* @brief Has OSC0 external oscillator. */ 1388 #define FSL_FEATURE_OSC_HAS_OSC0 (0) 1389 /* @brief Has OSC external oscillator (without index). */ 1390 #define FSL_FEATURE_OSC_HAS_OSC (0) 1391 /* @brief Number of OSC external oscillators. */ 1392 #define FSL_FEATURE_OSC_OSC_COUNT (0) 1393 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ 1394 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (1) 1395 1396 /* PDB module features */ 1397 1398 /* @brief Has DAC support. */ 1399 #define FSL_FEATURE_PDB_HAS_DAC (1) 1400 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1401 #define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) 1402 /* @brief PDB channel number). */ 1403 #define FSL_FEATURE_PDB_CHANNEL_COUNT (2) 1404 /* @brief Channel pre-trigger nunmber (related to number of registers CHmDLYn). */ 1405 #define FSL_FEATURE_PDB_CHANNEL_PRE_TRIGGER_COUNT (2) 1406 /* @brief DAC interval trigger number). */ 1407 #define FSL_FEATURE_PDB_DAC_INTERVAL_TRIGGER_COUNT (1) 1408 /* @brief Pulse out number). */ 1409 #define FSL_FEATURE_PDB_PULSE_OUT_COUNT (2) 1410 1411 /* PIT module features */ 1412 1413 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 1414 #define FSL_FEATURE_PIT_TIMER_COUNT (4) 1415 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 1416 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) 1417 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 1418 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) 1419 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1420 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) 1421 /* @brief Has timer enable control. */ 1422 #define FSL_FEATURE_PIT_HAS_MDIS (1) 1423 1424 /* PMC module features */ 1425 1426 /* @brief Has Bandgap Enable In VLPx Operation support. */ 1427 #define FSL_FEATURE_PMC_HAS_BGEN (1) 1428 /* @brief Has Bandgap Buffer Enable. */ 1429 #define FSL_FEATURE_PMC_HAS_BGBE (1) 1430 /* @brief Has Bandgap Buffer Drive Select. */ 1431 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 1432 /* @brief Has Low-Voltage Detect Voltage Select support. */ 1433 #define FSL_FEATURE_PMC_HAS_LVDV (1) 1434 /* @brief Has Low-Voltage Warning Voltage Select support. */ 1435 #define FSL_FEATURE_PMC_HAS_LVWV (1) 1436 /* @brief Has LPO. */ 1437 #define FSL_FEATURE_PMC_HAS_LPO (0) 1438 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 1439 #define FSL_FEATURE_PMC_HAS_VLPO (0) 1440 /* @brief Has acknowledge isolation support. */ 1441 #define FSL_FEATURE_PMC_HAS_ACKISO (1) 1442 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 1443 #define FSL_FEATURE_PMC_HAS_REGFPM (0) 1444 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 1445 #define FSL_FEATURE_PMC_HAS_REGONS (1) 1446 /* @brief Has PMC_HVDSC1. */ 1447 #define FSL_FEATURE_PMC_HAS_HVDSC1 (1) 1448 /* @brief Has PMC_PARAM. */ 1449 #define FSL_FEATURE_PMC_HAS_PARAM (0) 1450 /* @brief Has PMC_VERID. */ 1451 #define FSL_FEATURE_PMC_HAS_VERID (0) 1452 1453 /* PORT module features */ 1454 1455 /* @brief Has control lock (register bit PCR[LK]). */ 1456 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) 1457 /* @brief Has open drain control (register bit PCR[ODE]). */ 1458 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) 1459 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 1460 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) 1461 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 1462 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 1463 /* @brief Has pull resistor selection available. */ 1464 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 1465 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 1466 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 1467 /* @brief Has slew rate control (register bit PCR[SRE]). */ 1468 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) 1469 /* @brief Has passive filter (register bit field PCR[PFE]). */ 1470 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 1471 /* @brief Has drive strength control (register bit PCR[DSE]). */ 1472 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 1473 /* @brief Has separate drive strength register (HDRVE). */ 1474 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 1475 /* @brief Has glitch filter (register IOFLT). */ 1476 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 1477 /* @brief Defines width of PCR[MUX] field. */ 1478 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) 1479 /* @brief Has dedicated interrupt vector. */ 1480 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 1481 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 1482 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) 1483 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 1484 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 1485 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 1486 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 1487 1488 /* PWM module features */ 1489 1490 /* @brief If EflexPWM has module A channels (outputs). */ 1491 #define FSL_FEATURE_PWM_HAS_CHANNELA (1) 1492 /* @brief If EflexPWM has module B channels (outputs). */ 1493 #define FSL_FEATURE_PWM_HAS_CHANNELB (1) 1494 /* @brief If EflexPWM has module X channels (outputs). */ 1495 #define FSL_FEATURE_PWM_HAS_CHANNELX (1) 1496 /* @brief Number of submodules in each EflexPWM module. */ 1497 #define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U) 1498 1499 /* RCM module features */ 1500 1501 /* @brief Has Loss-of-Lock Reset support. */ 1502 #define FSL_FEATURE_RCM_HAS_LOL (1) 1503 /* @brief Has Loss-of-Clock Reset support. */ 1504 #define FSL_FEATURE_RCM_HAS_LOC (1) 1505 /* @brief Has JTAG generated Reset support. */ 1506 #define FSL_FEATURE_RCM_HAS_JTAG (1) 1507 /* @brief Has EzPort generated Reset support. */ 1508 #define FSL_FEATURE_RCM_HAS_EZPORT (0) 1509 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 1510 #define FSL_FEATURE_RCM_HAS_EZPMS (0) 1511 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 1512 #define FSL_FEATURE_RCM_HAS_BOOTROM (0) 1513 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 1514 #define FSL_FEATURE_RCM_HAS_SSRS (1) 1515 /* @brief Has Version ID Register (RCM_VERID). */ 1516 #define FSL_FEATURE_RCM_HAS_VERID (0) 1517 /* @brief Has Parameter Register (RCM_PARAM). */ 1518 #define FSL_FEATURE_RCM_HAS_PARAM (0) 1519 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 1520 #define FSL_FEATURE_RCM_HAS_SRIE (0) 1521 /* @brief Width of registers of the RCM. */ 1522 #define FSL_FEATURE_RCM_REG_WIDTH (8) 1523 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 1524 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 1525 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ 1526 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 1527 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 1528 #define FSL_FEATURE_RCM_HAS_WAKEUP (1) 1529 1530 /* SIM module features */ 1531 1532 /* @brief Has USB FS divider. */ 1533 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) 1534 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ 1535 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) 1536 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ 1537 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) 1538 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ 1539 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) 1540 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ 1541 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) 1542 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ 1543 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) 1544 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ 1545 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) 1546 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ 1547 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) 1548 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ 1549 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) 1550 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ 1551 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) 1552 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ 1553 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) 1554 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ 1555 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) 1556 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ 1557 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) 1558 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ 1559 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) 1560 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ 1561 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0) 1562 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ 1563 #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) 1564 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ 1565 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) 1566 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ 1567 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) 1568 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ 1569 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) 1570 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ 1571 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) 1572 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ 1573 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) 1574 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ 1575 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) 1576 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ 1577 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) 1578 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ 1579 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) 1580 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ 1581 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) 1582 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ 1583 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) 1584 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ 1585 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) 1586 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ 1587 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) 1588 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ 1589 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) 1590 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ 1591 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) 1592 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ 1593 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) 1594 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ 1595 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) 1596 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ 1597 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) 1598 /* @brief Has FTM module(s) configuration. */ 1599 #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) 1600 /* @brief Number of FTM modules. */ 1601 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) 1602 /* @brief Number of FTM triggers with selectable source. */ 1603 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (3) 1604 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ 1605 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) 1606 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ 1607 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) 1608 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ 1609 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) 1610 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ 1611 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) 1612 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ 1613 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) 1614 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ 1615 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) 1616 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ 1617 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4) 1618 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ 1619 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) 1620 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ 1621 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) 1622 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ 1623 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) 1624 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ 1625 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) 1626 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ 1627 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) 1628 /* @brief Has TPM module(s) configuration. */ 1629 #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) 1630 /* @brief The highest TPM module index. */ 1631 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) 1632 /* @brief Has TPM module with index 0. */ 1633 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) 1634 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ 1635 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) 1636 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ 1637 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) 1638 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1639 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) 1640 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ 1641 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) 1642 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1643 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) 1644 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ 1645 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) 1646 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ 1647 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) 1648 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ 1649 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) 1650 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ 1651 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) 1652 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ 1653 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) 1654 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ 1655 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) 1656 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ 1657 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) 1658 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ 1659 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) 1660 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ 1661 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1) 1662 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ 1663 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1) 1664 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ 1665 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) 1666 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ 1667 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) 1668 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ 1669 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) 1670 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ 1671 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) 1672 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ 1673 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) 1674 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ 1675 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) 1676 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ 1677 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) 1678 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ 1679 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) 1680 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ 1681 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) 1682 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ 1683 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) 1684 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ 1685 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (0) 1686 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register ADCOPT). */ 1687 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (2) 1688 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register ADCOPT). */ 1689 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) 1690 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register ADCOPT). */ 1691 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) 1692 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register ADCOPT). */ 1693 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) 1694 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ 1695 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (2) 1696 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ 1697 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (2) 1698 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ 1699 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) 1700 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ 1701 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (2) 1702 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ 1703 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (2) 1704 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ 1705 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) 1706 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ 1707 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) 1708 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ 1709 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) 1710 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ 1711 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) 1712 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ 1713 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) 1714 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ 1715 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) 1716 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ 1717 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) 1718 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ 1719 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) 1720 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ 1721 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) 1722 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ 1723 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) 1724 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ 1725 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) 1726 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ 1727 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1) 1728 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ 1729 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) 1730 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ 1731 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) 1732 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ 1733 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) 1734 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ 1735 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) 1736 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ 1737 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) 1738 /* @brief Has device die ID (register bit field SDID[DIEID]). */ 1739 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) 1740 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ 1741 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) 1742 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ 1743 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) 1744 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ 1745 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) 1746 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ 1747 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) 1748 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ 1749 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) 1750 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ 1751 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) 1752 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ 1753 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) 1754 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ 1755 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) 1756 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ 1757 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) 1758 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ 1759 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) 1760 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ 1761 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) 1762 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ 1763 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) 1764 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ 1765 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) 1766 /* @brief Has miscellanious control register (register MCR). */ 1767 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) 1768 /* @brief Has COP watchdog (registers COPC and SRVCOP). */ 1769 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) 1770 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ 1771 #define FSL_FEATURE_SIM_HAS_COP_STOP (0) 1772 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ 1773 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) 1774 /* @brief Has UIDH registers. */ 1775 #define FSL_FEATURE_SIM_HAS_UIDH (1) 1776 /* @brief Has UIDM registers. */ 1777 #define FSL_FEATURE_SIM_HAS_UIDM (0) 1778 1779 /* SMC module features */ 1780 1781 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 1782 #define FSL_FEATURE_SMC_HAS_PSTOPO (1) 1783 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 1784 #define FSL_FEATURE_SMC_HAS_LPOPO (1) 1785 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 1786 #define FSL_FEATURE_SMC_HAS_PORPO (1) 1787 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 1788 #define FSL_FEATURE_SMC_HAS_LPWUI (0) 1789 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 1790 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) 1791 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 1792 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) 1793 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 1794 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1) 1795 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 1796 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1) 1797 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 1798 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) 1799 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 1800 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (0) 1801 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 1802 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) 1803 /* @brief Has stop submode. */ 1804 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) 1805 /* @brief Has stop submode 0(VLLS0). */ 1806 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) 1807 /* @brief Has stop submode 1(VLLS1). */ 1808 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1) 1809 /* @brief Has stop submode 2(VLLS2). */ 1810 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) 1811 /* @brief Has SMC_PARAM. */ 1812 #define FSL_FEATURE_SMC_HAS_PARAM (0) 1813 /* @brief Has SMC_VERID. */ 1814 #define FSL_FEATURE_SMC_HAS_VERID (0) 1815 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 1816 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 1817 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 1818 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) 1819 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 1820 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) 1821 /* @brief Width of SMC registers. */ 1822 #define FSL_FEATURE_SMC_REG_WIDTH (8) 1823 1824 /* DSPI module features */ 1825 1826 /* @brief Receive/transmit FIFO size in number of items. */ 1827 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) 1828 /* @brief Maximum transfer data width in bits. */ 1829 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) 1830 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ 1831 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) 1832 /* @brief Number of chip select pins. */ 1833 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) 1834 /* @brief Number of CTAR registers. */ 1835 #define FSL_FEATURE_DSPI_CTAR_COUNT (2) 1836 /* @brief Has chip select strobe capability on the PCS5 pin. */ 1837 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) 1838 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 1839 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 1840 /* @brief Has 16-bit data transfer support. */ 1841 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) 1842 /* @brief Has separate DMA RX and TX requests. */ 1843 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1844 1845 /* SYSMPU module features */ 1846 1847 /* @brief Specifies number of descriptors available. */ 1848 #define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (12) 1849 /* @brief Has process identifier support. */ 1850 #define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1) 1851 /* @brief Total number of MPU slave. */ 1852 #define FSL_FEATURE_SYSMPU_SLAVE_COUNT (5) 1853 /* @brief Total number of MPU master. */ 1854 #define FSL_FEATURE_SYSMPU_MASTER_COUNT (4) 1855 1856 /* SCB module features */ 1857 1858 /* @brief L1 ICACHE line size in byte. */ 1859 #define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32) 1860 /* @brief L1 DCACHE line size in byte. */ 1861 #define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32) 1862 1863 /* SysTick module features */ 1864 1865 /* @brief Systick has external reference clock. */ 1866 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) 1867 /* @brief Systick external reference clock is core clock divided by this value. */ 1868 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) 1869 1870 /* UART module features */ 1871 1872 #if defined(CPU_MKV56F1M0VLL24) || defined(CPU_MKV56F512VLL24) 1873 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 1874 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) 1875 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 1876 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 1877 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 1878 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 1879 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1880 #define FSL_FEATURE_UART_HAS_FIFO (1) 1881 /* @brief Hardware flow control (RTS, CTS) is supported. */ 1882 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) 1883 /* @brief Infrared (modulation) is supported. */ 1884 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) 1885 /* @brief 2 bits long stop bit is available. */ 1886 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 1887 /* @brief If 10-bit mode is supported. */ 1888 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) 1889 /* @brief Baud rate fine adjustment is available. */ 1890 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) 1891 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 1892 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 1893 /* @brief Baud rate oversampling is available. */ 1894 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) 1895 /* @brief Baud rate oversampling is available. */ 1896 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) 1897 /* @brief Peripheral type. */ 1898 #define FSL_FEATURE_UART_IS_SCI (0) 1899 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1900 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ 1901 (((x) == UART0) ? (8) : \ 1902 (((x) == UART1) ? (8) : \ 1903 (((x) == UART2) ? (1) : \ 1904 (((x) == UART3) ? (1) : \ 1905 (((x) == UART4) ? (1) : (-1)))))) 1906 /* @brief Supports two match addresses to filter incoming frames. */ 1907 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) 1908 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 1909 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 1910 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 1911 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) 1912 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 1913 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) 1914 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 1915 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) 1916 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1917 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1) 1918 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1919 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1920 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1921 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 1922 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 1923 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) 1924 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1925 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) 1926 /* @brief Has separate DMA RX and TX requests. */ 1927 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1928 #elif defined(CPU_MKV56F1M0VLQ24) || defined(CPU_MKV56F1M0VMD24) || defined(CPU_MKV56F512VLQ24) || defined(CPU_MKV56F512VMD24) 1929 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 1930 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) 1931 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 1932 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 1933 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 1934 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 1935 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1936 #define FSL_FEATURE_UART_HAS_FIFO (1) 1937 /* @brief Hardware flow control (RTS, CTS) is supported. */ 1938 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) 1939 /* @brief Infrared (modulation) is supported. */ 1940 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) 1941 /* @brief 2 bits long stop bit is available. */ 1942 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 1943 /* @brief If 10-bit mode is supported. */ 1944 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) 1945 /* @brief Baud rate fine adjustment is available. */ 1946 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) 1947 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 1948 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 1949 /* @brief Baud rate oversampling is available. */ 1950 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) 1951 /* @brief Baud rate oversampling is available. */ 1952 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) 1953 /* @brief Peripheral type. */ 1954 #define FSL_FEATURE_UART_IS_SCI (0) 1955 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1956 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ 1957 (((x) == UART0) ? (8) : \ 1958 (((x) == UART1) ? (8) : \ 1959 (((x) == UART2) ? (1) : \ 1960 (((x) == UART3) ? (1) : \ 1961 (((x) == UART4) ? (1) : \ 1962 (((x) == UART5) ? (1) : (-1))))))) 1963 /* @brief Supports two match addresses to filter incoming frames. */ 1964 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) 1965 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 1966 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 1967 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 1968 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) 1969 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 1970 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) 1971 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 1972 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) 1973 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1974 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1) 1975 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1976 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1977 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1978 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 1979 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 1980 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) 1981 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1982 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) 1983 /* @brief Has separate DMA RX and TX requests. */ 1984 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1985 #endif /* defined(CPU_MKV56F1M0VLL24) || defined(CPU_MKV56F512VLL24) */ 1986 1987 /* WDOG module features */ 1988 1989 /* @brief Watchdog is available. */ 1990 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 1991 /* @brief Has Wait mode support. */ 1992 #define FSL_FEATURE_WDOG_HAS_WAITEN (1) 1993 1994 /* XBARA module features */ 1995 1996 /* @brief Number of interrupt requests. */ 1997 #define FSL_FEATURE_XBARA_INTERRUPT_COUNT (4) 1998 1999 /* XBARB module features */ 2000 2001 /* @brief Number of interrupt requests. */ 2002 #define FSL_FEATURE_XBARB_INTERRUPT_COUNT (0) 2003 2004 #endif /* _MKV56F24_FEATURES_H_ */ 2005 2006
