1 /* 2 ** ################################################################### 3 ** Version: rev. 2.0, 2024-05-28 4 ** Build: b240621 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2024 NXP 11 ** SPDX-License-Identifier: BSD-3-Clause 12 ** 13 ** http: www.nxp.com 14 ** mail: support@nxp.com 15 ** 16 ** Revisions: 17 ** - rev. 1.0 (2023-11-21) 18 ** Initial version. 19 ** - rev. 2.0 (2024-05-28) 20 ** Rev2 DraftA. 21 ** 22 ** ################################################################### 23 */ 24 25 #ifndef _MIMXRT798S_cm33_core1_FEATURES_H_ 26 #define _MIMXRT798S_cm33_core1_FEATURES_H_ 27 28 /* SOC module features */ 29 30 /* @brief ACMP availability on the SoC. */ 31 #define FSL_FEATURE_SOC_ACMP_COUNT (1) 32 /* @brief AIPS availability on the SoC. */ 33 #define FSL_FEATURE_SOC_AIPS_COUNT (7) 34 /* @brief AXBS availability on the SoC. */ 35 #define FSL_FEATURE_SOC_AXBS_COUNT (6) 36 /* @brief CDOG availability on the SoC. */ 37 #define FSL_FEATURE_SOC_CDOG_COUNT (2) 38 /* @brief CTIMER availability on the SoC. */ 39 #define FSL_FEATURE_SOC_CTIMER_COUNT (3) 40 /* @brief EDMA availability on the SoC. */ 41 #define FSL_FEATURE_SOC_EDMA_COUNT (2) 42 /* @brief FLEXIO availability on the SoC. */ 43 #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) 44 /* @brief GPIO availability on the SoC. */ 45 #define FSL_FEATURE_SOC_GPIO_COUNT (6) 46 /* @brief I3C availability on the SoC. */ 47 #define FSL_FEATURE_SOC_I3C_COUNT (2) 48 /* @brief I2S availability on the SoC. */ 49 #define FSL_FEATURE_SOC_I2S_COUNT (1) 50 /* @brief INPUTMUX availability on the SoC. */ 51 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 52 /* @brief LCDIF availability on the SoC. */ 53 #define FSL_FEATURE_SOC_LCDIF_COUNT (1) 54 /* @brief LPADC availability on the SoC. */ 55 #define FSL_FEATURE_SOC_LPADC_COUNT (1) 56 /* @brief LPI2C availability on the SoC. */ 57 #define FSL_FEATURE_SOC_LPI2C_COUNT (5) 58 /* @brief LPSPI availability on the SoC. */ 59 #define FSL_FEATURE_SOC_LPSPI_COUNT (6) 60 /* @brief LPUART availability on the SoC. */ 61 #define FSL_FEATURE_SOC_LPUART_COUNT (4) 62 /* @brief MIPI_DSI_HOST availability on the SoC. */ 63 #define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (1) 64 /* @brief MRT availability on the SoC. */ 65 #define FSL_FEATURE_SOC_MRT_COUNT (1) 66 /* @brief MU availability on the SoC. */ 67 #define FSL_FEATURE_SOC_MU_COUNT (3) 68 /* @brief OSTIMER availability on the SoC. */ 69 #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) 70 /* @brief PDM availability on the SoC. */ 71 #define FSL_FEATURE_SOC_PDM_COUNT (1) 72 /* @brief PINT availability on the SoC. */ 73 #define FSL_FEATURE_SOC_PINT_COUNT (1) 74 /* @brief PMC availability on the SoC. */ 75 #define FSL_FEATURE_SOC_PMC_COUNT (1) 76 /* @brief RSTCTL1 availability on the SoC. */ 77 #define FSL_FEATURE_SOC_RSTCTL1_COUNT (1) 78 /* @brief RTC availability on the SoC. */ 79 #define FSL_FEATURE_SOC_RTC_COUNT (1) 80 /* @brief SCT availability on the SoC. */ 81 #define FSL_FEATURE_SOC_SCT_COUNT (1) 82 /* @brief SEMA42 availability on the SoC. */ 83 #define FSL_FEATURE_SOC_SEMA42_COUNT (2) 84 /* @brief USBHS availability on the SoC. */ 85 #define FSL_FEATURE_SOC_USBHS_COUNT (2) 86 /* @brief USBHSDCD availability on the SoC. */ 87 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (1) 88 /* @brief USBNC availability on the SoC. */ 89 #define FSL_FEATURE_SOC_USBNC_COUNT (2) 90 /* @brief USBPHY availability on the SoC. */ 91 #define FSL_FEATURE_SOC_USBPHY_COUNT (1) 92 /* @brief USDHC availability on the SoC. */ 93 #define FSL_FEATURE_SOC_USDHC_COUNT (2) 94 /* @brief UTICK availability on the SoC. */ 95 #define FSL_FEATURE_SOC_UTICK_COUNT (1) 96 /* @brief WWDT availability on the SoC. */ 97 #define FSL_FEATURE_SOC_WWDT_COUNT (2) 98 99 /* ACMP module features */ 100 101 /* @brief Has CMP_C3. */ 102 #define FSL_FEATURE_ACMP_HAS_C3_REG (1) 103 /* @brief Has C0 LINKEN Bit */ 104 #define FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT (1) 105 /* @brief Has C0 OFFSET Bit */ 106 #define FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT (0) 107 /* @brief Has C1 INPSEL Bit */ 108 #define FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT (0) 109 /* @brief Has C1 INNSEL Bit */ 110 #define FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT (0) 111 /* @brief Has C1 DACOE Bit */ 112 #define FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT (0) 113 /* @brief Has C1 DMODE Bit */ 114 #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) 115 /* @brief Has C2 RRE Bit */ 116 #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) 117 /* @brief Has C0 HYSTCTR Bit */ 118 #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) 119 /* @brief If support round-robin mode */ 120 #define FSL_FEATURE_ACMP_HAS_NO_ROUNDROBIN_MODE (1) 121 /* @brief If support 3v domain */ 122 #define FSL_FEATURE_ACMP_HAS_NO_3V_DOMAIN (1) 123 /* @brief If support window mode */ 124 #define FSL_FEATURE_ACMP_HAS_NO_WINDOW_MODE (1) 125 /* @brief If support filter mode */ 126 #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) 127 /* @brief Has No C0 SE Bit */ 128 #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (1) 129 130 /* LPADC module features */ 131 132 /* @brief FIFO availability on the SoC. */ 133 #define FSL_FEATURE_LPADC_FIFO_COUNT (2) 134 /* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ 135 #define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (0) 136 /* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ 137 #define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) 138 /* @brief Has differential mode (bitfield CMDLn[DIFF]). */ 139 #define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) 140 /* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ 141 #define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) 142 /* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ 143 #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) 144 /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ 145 #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) 146 /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ 147 #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) 148 /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ 149 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) 150 /* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ 151 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) 152 /* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ 153 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) 154 /* @brief Has internal clock (bitfield CFG[ADCKEN]). */ 155 #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) 156 /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ 157 #define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) 158 /* @brief Has calibration (bitfield CFG[CALOFS]). */ 159 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) 160 /* @brief Has offset trim (register OFSTRIM). */ 161 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (0) 162 /* @brief Has power select (bitfield CFG[PWRSEL]). */ 163 #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (0) 164 /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ 165 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) 166 /* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ 167 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (1) 168 /* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ 169 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (1) 170 /* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ 171 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (1) 172 /* @brief Conversion averaged bitfiled width. */ 173 #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) 174 /* @brief Enable hardware trigger command selection */ 175 #define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) 176 /* @brief Has Trigger status register. */ 177 #define FSL_FEATURE_LPADC_HAS_TSTAT (1) 178 /* @brief Has B side channels. */ 179 #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) 180 /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ 181 #define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) 182 /* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ 183 #define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) 184 /* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ 185 #define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) 186 /* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ 187 #define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) 188 /* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ 189 #define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) 190 /* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ 191 #define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) 192 /* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ 193 #define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) 194 /* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ 195 #define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) 196 /* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ 197 #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) 198 /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ 199 #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) 200 /* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ 201 #define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) 202 /* @brief Buffer size of temperature sensor (CMDHa[LOOP] value to be set in process of calculate the temperature). */ 203 #define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) 204 /* @brief Temperature sensor parameter A (slope). */ 205 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_SLOP (789.2) 206 /* @brief Temperature sensor parameter B (offset). */ 207 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_OFFSET (319.2) 208 /* @brief Temperature sensor parameter ALPHA (Alpha). */ 209 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (11.2) 210 211 /* CDOG module features */ 212 213 /* @brief SOC has no reset driver. */ 214 #define FSL_FEATURE_CDOG_HAS_NO_RESET (1) 215 216 /* CTIMER module features */ 217 218 /* @brief CTIMER has no capture channel. */ 219 #define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) 220 /* @brief CTIMER has no capture 2 interrupt. */ 221 #define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) 222 /* @brief CTIMER capture 3 interrupt. */ 223 #define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) 224 /* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ 225 #define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) 226 /* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ 227 #define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) 228 /* @brief CTIMER Has register MSR */ 229 #define FSL_FEATURE_CTIMER_HAS_MSR (1) 230 231 /* EDMA module features */ 232 233 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 234 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (8) 235 /* @brief If 8 bytes transfer supported. */ 236 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) 237 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 238 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) 239 /* @brief If 16 bytes transfer supported. */ 240 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) 241 /* @brief Has DMA_Error interrupt vector. */ 242 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 243 /* @brief If 64 bytes transfer supported. */ 244 #define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1) 245 /* @brief Has register access permission. */ 246 #define FSL_FEATURE_HAVE_DMA_CONTROL_REGISTER_ACCESS_PERMISSION (1) 247 /* @brief If 128 bytes transfer supported. */ 248 #define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (1) 249 /* @brief If channel clock controlled independently */ 250 #define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) 251 /* @brief If 128 bytes transfer supported. */ 252 #define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1) 253 /* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ 254 #define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (8) 255 /* @brief Has register CH_CSR. */ 256 #define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) 257 /* @brief Has no register bit fields MP_CSR[EBW]. */ 258 #define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) 259 /* @brief Has channel mux */ 260 #define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) 261 /* @brief If dma has common clock gate */ 262 #define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) 263 /* @brief Instance has channel mux */ 264 #define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) 265 /* @brief If dma channel IRQ support parameter */ 266 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) 267 /* @brief Has register CH_SBR. */ 268 #define FSL_FEATURE_EDMA_HAS_SBR (1) 269 /* @brief NBYTES must be multiple of 8 when using scatter gather. */ 270 #define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) 271 /* @brief Has no register bit fields CH_SBR[ATTR]. */ 272 #define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) 273 /* @brief NBYTES must be multiple of 8 when using scatter gather. */ 274 #define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) 275 /* @brief Has register bit field CH_CSR[SWAP]. */ 276 #define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) 277 /* @brief Has register bit fields MP_CSR[GMRC]. */ 278 #define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) 279 /* @brief Instance has register bit field CH_CSR[SWAP]. */ 280 #define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) 281 /* @brief Whether has prot register. */ 282 #define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) 283 /* @brief Has register bit field CH_SBR[INSTR]. */ 284 #define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) 285 /* @brief Whether has MP channel mux. */ 286 #define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) 287 /* @brief Instance has register bit field CH_SBR[INSTR]. */ 288 #define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) 289 /* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ 290 #define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) 291 /* @brief Instance has register CH_MATTR. */ 292 #define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) 293 /* @brief Has register bit field CH_CSR[SIGNEXT]. */ 294 #define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) 295 /* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ 296 #define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) 297 /* @brief Has register bit field TCD_CSR[BWC]. */ 298 #define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) 299 /* @brief Instance has register bit field TCD_CSR[BWC]. */ 300 #define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) 301 /* @brief Has register bit fields TCD_CSR[TMC]. */ 302 #define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) 303 /* @brief Instance has register bit fields TCD_CSR[TMC]. */ 304 #define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) 305 /* @brief Has no register bit fields CH_SBR[SEC]. */ 306 #define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (0) 307 /* @brief edma5 has different tcd type. */ 308 #define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) 309 /* @brief Number of DMA channels with asynchronous request capability. */ 310 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (8) 311 312 /* FLEXIO module features */ 313 314 /* @brief FLEXIO support reset from RSTCTL */ 315 #define FSL_FEATURE_FLEXIO_HAS_RESET (1) 316 /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ 317 #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) 318 /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ 319 #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) 320 /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ 321 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) 322 /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ 323 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) 324 /* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ 325 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) 326 /* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 327 #define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) 328 /* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 329 #define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) 330 /* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ 331 #define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) 332 /* @brief Reset value of the FLEXIO_VERID register */ 333 #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) 334 /* @brief Reset value of the FLEXIO_PARAM register */ 335 #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4100808) 336 /* @brief Flexio DMA request base channel */ 337 #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) 338 /* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ 339 #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) 340 /* @brief Has pin input output related registers */ 341 #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) 342 343 /* GPIO module features */ 344 345 /* @brief Has GPIO attribute checker register (GACR). */ 346 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) 347 /* @brief GPIO registers width */ 348 #define FSL_FEATURE_GPIO_REGISTERS_WIDTH (32) 349 /* @brief Has GPIO version ID register (VERID). */ 350 #define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) 351 /* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ 352 #define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (1) 353 /* @brief Has GPIO port input disable register (PIDR). */ 354 #define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) 355 /* @brief Has GPIO interrupt/DMA request/trigger output selection. */ 356 #define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (1) 357 358 /* I3C module features */ 359 360 /* @brief Has TERM bitfile in MERRWARN register. */ 361 #define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) 362 /* @brief SOC has no reset driver. */ 363 #define FSL_FEATURE_I3C_HAS_NO_RESET (0) 364 /* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ 365 #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) 366 /* @brief Register SCONFIG do not have IDRAND bitfield. */ 367 #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) 368 /* @brief Register SCONFIG has HDROK bitfield. */ 369 #define FSL_FEATURE_I3C_HAS_HDROK (1) 370 /* @brief Has ERRATA_051617. */ 371 #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) 372 /* @brief SOC does not support slave IBI/MR/HJ */ 373 #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) 374 /* @brief Has ERRATA_052086. */ 375 #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) 376 377 /* LCDIF module features */ 378 379 /* @brief LCDIF version. */ 380 #define FSL_FEATURE_LCDIF_VERSION_DC8000 (1) 381 /* @brief Support D/CX Pin polarity */ 382 #define FSL_FEATURE_LCDIF_HAS_DBIX_POLARITY (0) 383 /* @brief Has DBI Type C Option. */ 384 #define FSL_FEATURE_LCDIF_HAS_TYPEC (0) 385 386 /* LPI2C module features */ 387 388 /* @brief Has separate DMA RX and TX requests. */ 389 #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 390 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 391 #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) 392 393 /* LPSPI module features */ 394 395 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 396 #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) 397 /* @brief Has separate DMA RX and TX requests. */ 398 #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 399 /* @brief Has CCR1 (related to existence of registers CCR1). */ 400 #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) 401 /* @brief Has no PCSCFG bit in CFGR1 register. */ 402 #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) 403 /* @brief Has no WIDTH bits in TCR register. */ 404 #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) 405 406 /* LPUART module features */ 407 408 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 409 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 410 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 411 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 412 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 413 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 414 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 415 #define FSL_FEATURE_LPUART_HAS_FIFO (1) 416 /* @brief Has 32-bit register MODIR */ 417 #define FSL_FEATURE_LPUART_HAS_MODIR (1) 418 /* @brief Hardware flow control (RTS, CTS) is supported. */ 419 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) 420 /* @brief Infrared (modulation) is supported. */ 421 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) 422 /* @brief 2 bits long stop bit is available. */ 423 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 424 /* @brief If 10-bit mode is supported. */ 425 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 426 /* @brief If 7-bit mode is supported. */ 427 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) 428 /* @brief Baud rate fine adjustment is available. */ 429 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 430 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 431 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 432 /* @brief Baud rate oversampling is available. */ 433 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 434 /* @brief Baud rate oversampling is available. */ 435 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 436 /* @brief Peripheral type. */ 437 #define FSL_FEATURE_LPUART_IS_SCI (1) 438 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 439 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) 440 /* @brief Supports two match addresses to filter incoming frames. */ 441 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 442 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 443 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) 444 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 445 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 446 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 447 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 448 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 449 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 450 /* @brief Has improved smart card (ISO7816 protocol) support. */ 451 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 452 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 453 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 454 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 455 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 456 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 457 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 458 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 459 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 460 /* @brief Has separate DMA RX and TX requests. */ 461 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 462 /* @brief Has separate RX and TX interrupts. */ 463 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) 464 /* @brief Has LPAURT_PARAM. */ 465 #define FSL_FEATURE_LPUART_HAS_PARAM (1) 466 /* @brief Has LPUART_VERID. */ 467 #define FSL_FEATURE_LPUART_HAS_VERID (1) 468 /* @brief Has LPUART_GLOBAL. */ 469 #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) 470 /* @brief Has LPUART_PINCFG. */ 471 #define FSL_FEATURE_LPUART_HAS_PINCFG (1) 472 /* @brief Belong to LPFLEXCOMM */ 473 #define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) 474 /* @brief Has register MODEM Control. */ 475 #define FSL_FEATURE_LPUART_HAS_MCR (0) 476 /* @brief Has register Half Duplex Control. */ 477 #define FSL_FEATURE_LPUART_HAS_HDCR (0) 478 /* @brief Has register Timeout. */ 479 #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) 480 481 /* MIPI_DSI_HOST module features */ 482 483 /* @brief Does not have DPHY PLL(DPHY_CM) */ 484 #define FSL_FEATURE_MIPI_DSI_HOST_NO_DPHY_PLL (1) 485 /* @brief Support TX ULPS */ 486 #define FSL_FEATURE_MIPI_DSI_HOST_HAS_ULPS (1) 487 /* @brief Has control register to enable or disable TX ULPS */ 488 #define FSL_FEATURE_MIPI_DSI_HOST_HAS_ULPS_CTRL (0) 489 /* @brief Has pixel-link to DPI remap */ 490 #define FSL_FEATURE_MIPI_DSI_HOST_HAS_PXL2DPI (0) 491 /* @brief Has DBI Pixel Format register */ 492 #define FSL_FEATURE_MIPI_DSI_HOST_DBI_HAS_PIXEL_FORMAT (1) 493 /* @brief Has PHY ready status register */ 494 #define FSL_FEATURE_MIPI_DSI_HOST_HAS_PHY_RDY (1) 495 /* @brief Has HS control HS_MODE_ENABLE register */ 496 #define FSL_FEATURE_MIPI_DSI_HOST_HAS_HS_CTRL (1) 497 /* @brief Has bitfield HOST_TURNAROUND[REQUEST_BTA] */ 498 #define FSL_FEATURE_MIPI_DSI_HOST_HAS_BTA_CTRL (1) 499 /* @brief Has separate ULPS control */ 500 #define FSL_FEATURE_MIPI_DSI_HOST_HAS_SEPARATE_ULPS_CTRL (1) 501 502 /* MRT module features */ 503 504 /* @brief number of channels. */ 505 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) 506 507 /* MU module features */ 508 509 /* @brief MU side for current core */ 510 #define FSL_FEATURE_MU_SIDE_B (1) 511 /* @brief MU side for current core */ 512 #define FSL_FEATURE_MU_SIDE_A (1) 513 /* @brief MU supports reset assert interrupt. CIER0[RAIE] or CR[RAIE] or BCR[RAIE]. */ 514 #define FSL_FEATURE_MU_HAS_RESET_ASSERT_INT (0) 515 /* @brief MU supports reset de-assert interrupt. CR[RDIE] or BCR[RDIE]. */ 516 #define FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT (0) 517 /* @brief MU does not support core status. Register CSSR0 or CSR0. */ 518 #define FSL_FEATURE_MU_NO_CORE_STATUS (0) 519 /* @brief MU does not support NMI. Register bit CCR0[NMI]. */ 520 #define FSL_FEATURE_MU_NO_NMI (0) 521 /* @brief MU does not support core event pending. Register bit SR[CEP]. */ 522 #define FSL_FEATURE_MU_NO_CEP (0) 523 /* @brief MU supports Power-Down mode entry interrupt. CIER0[PDIE] */ 524 #define FSL_FEATURE_MU_HAS_PD_INT (0) 525 /* @brief MU supports STOP mode entry interrupt. CIER0[STOPIE] */ 526 #define FSL_FEATURE_MU_HAS_STOP_INT (0) 527 /* @brief MU supports WAIT mode entry interrupt. CIER0[WAITIE] */ 528 #define FSL_FEATURE_MU_HAS_WAIT_INT (1) 529 /* @brief MU supports HALT mode entry interrupt. CIER0[HALTIE] */ 530 #define FSL_FEATURE_MU_HAS_HALT_INT (0) 531 /* @brief MU supports RUN mode entry interrupt. CIER0[RUNIE] */ 532 #define FSL_FEATURE_MU_HAS_RUN_INT (0) 533 /* @brief MU supports hardware reset interrupt. CSSR0[HRIP] or CSR0[HRIP]. */ 534 #define FSL_FEATURE_MU_HAS_SR_HRIP (0) 535 /* @brief MU supports reset interrupt. Register bit SR[MURIP]. */ 536 #define FSL_FEATURE_MU_HAS_SR_MURIP (0) 537 /* @brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */ 538 #define FSL_FEATURE_MU_NO_CLKE (1) 539 /* @brief MU has bit CCR0[RSTH]. */ 540 #define FSL_FEATURE_MU_HAS_RSTH (0) 541 /* @brief MU has bit CCR0[RSTH] by instance. */ 542 #define FSL_FEATURE_MU_HAS_RSTH_BY_INSTANCEn(x) (0) 543 /* @brief MU has bit CCR0[BOOT]. */ 544 #define FSL_FEATURE_MU_HAS_BOOT (0) 545 /* @brief MU has bit CCR0[BOOT] by instance. */ 546 #define FSL_FEATURE_MU_HAS_BOOT_BY_INSTANCEn(x) (0) 547 /* @brief MU supports MU reset, CR[MUR]. */ 548 #define FSL_FEATURE_MU_HAS_MUR (1) 549 /* @brief MU supports hardware reset, CR[HR] or CCR0[HR]. */ 550 #define FSL_FEATURE_MU_HAS_HR (0) 551 /* @brief MU supports hardware reset by instance */ 552 #define FSL_FEATURE_MU_HAS_HR_BY_INSTANCEn(x) (0) 553 /* @brief The number of general purpose interrupts supported by MU. */ 554 #define FSL_FEATURE_MU_GPI_COUNT (4) 555 556 /* PDM module features */ 557 558 /* @brief PDM FIFO offset */ 559 #define FSL_FEATURE_PDM_FIFO_OFFSET (4) 560 /* @brief PDM Channel Number */ 561 #define FSL_FEATURE_PDM_CHANNEL_NUM (8) 562 /* @brief PDM FIFO WIDTH Size */ 563 #define FSL_FEATURE_PDM_FIFO_WIDTH (4) 564 /* @brief PDM FIFO DEPTH Size */ 565 #define FSL_FEATURE_PDM_FIFO_DEPTH (8) 566 /* @brief PDM has RANGE_CTRL register */ 567 #define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1) 568 /* @brief PDM Has Low Frequency */ 569 #define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (0) 570 /* @brief PDM Has DC_OUT_CTRL. */ 571 #define FSL_FEATURE_PDM_HAS_DC_OUT_CTRL (1) 572 /* @brief PDM Has Fixed DC CTRL VALUE. */ 573 #define FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED (1) 574 /* @brief PDM Has no independent error IRQ. */ 575 #define FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ (1) 576 /* @brief PDM has no minimum clkdiv. */ 577 #define FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV (1) 578 /* @brief PDM Has No VADEF Bitfield In PDM VAD0_STAT Register */ 579 #define FSL_FEATURE_PDM_HAS_NO_VADEF (1) 580 /* @brief PDM Has no FIR_RDY Bitfield In PDM STAT Register */ 581 #define FSL_FEATURE_PDM_HAS_NO_FIR_RDY (1) 582 /* @brief PDM Has no DOZEN Bitfield In PDM CTRL_1 Register */ 583 #define FSL_FEATURE_PDM_HAS_NO_DOZEN (0) 584 /* @brief PDM Has DEC_BYPASS Bitfield In PDM CTRL_2 Register */ 585 #define FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS (1) 586 587 /* PINT module features */ 588 589 /* @brief Number of connected outputs */ 590 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (4) 591 592 /* PMC module features */ 593 594 /* @brief Has no OS Timer control register in PMC */ 595 #define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1) 596 597 /* RTC module features */ 598 599 /* @brief Has Tamper Direction Register support */ 600 #define FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION (0) 601 /* @brief Has SUBSECOND_CTRL register. */ 602 #define FSL_FEATURE_RTC_HAS_SUBSECOND (0) 603 /* @brief Has Tamper Queue Status and Control Register support. */ 604 #define FSL_FEATURE_RTC_HAS_TAMPER_QUEUE (0) 605 /* @brief Has RTC subsystem. */ 606 #define FSL_FEATURE_RTC_HAS_SUBSYSTEM (1) 607 /* @brief Has RTC Tamper 23 Filter Configuration Register support */ 608 #define FSL_FEATURE_RTC_HAS_FILTER23_CFG (0) 609 /* @brief Has WAKEUP_MODE bitfile in CTRL2 register. */ 610 #define FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE (1) 611 /* @brief Has CLK_SEL bitfile in CTRL register. */ 612 #define FSL_FEATURE_RTC_HAS_CLOCK_SELECT (0) 613 /* @brief Has CLKO_DIS bitfile in CTRL register. */ 614 #define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE (1) 615 /* @brief Has No Tamper in RTC. */ 616 #define FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE (1) 617 /* @brief Has CPU_LOW_VOLT bitfile in STATUS register. */ 618 #define FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG (1) 619 /* @brief Has RST_SRC bitfile in STATUS register. */ 620 #define FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG (1) 621 /* @brief Has GP_DATA_REG register. */ 622 #define FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG (1) 623 /* @brief Has TIMER_STB_MASK bitfile in CTRL register. */ 624 #define FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK (1) 625 /* @brief Target(slave) instance. */ 626 #define FSL_FEATURE_RTC_IS_SLAVE (1) 627 628 /* SAI module features */ 629 630 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ 631 #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) 632 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ 633 #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (1) 634 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ 635 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) 636 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ 637 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) 638 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ 639 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) 640 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ 641 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) 642 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ 643 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) 644 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ 645 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) 646 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ 647 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) 648 /* @brief Interrupt source number */ 649 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) 650 /* @brief Has register of MCR. */ 651 #define FSL_FEATURE_SAI_HAS_MCR (1) 652 /* @brief Has bit field MICS of the MCR register. */ 653 #define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) 654 /* @brief Has register of MDR */ 655 #define FSL_FEATURE_SAI_HAS_MDR (0) 656 /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ 657 #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) 658 /* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ 659 #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) 660 /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ 661 #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) 662 /* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ 663 #define FSL_FEATURE_SAI_HAS_FIFO (1) 664 /* @brief Support synchronous with another SAI. */ 665 #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) 666 667 /* SCT module features */ 668 669 /* @brief Number of events */ 670 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) 671 /* @brief Number of states */ 672 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) 673 /* @brief Number of match capture */ 674 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) 675 /* @brief Number of outputs */ 676 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) 677 678 /* SEMA42 module features */ 679 680 /* @brief Gate counts */ 681 #define FSL_FEATURE_SEMA42_GATE_COUNT (64) 682 683 /* USBHS module features */ 684 685 /* @brief EHCI module instance count */ 686 #define FSL_FEATURE_USBHS_EHCI_COUNT (2) 687 /* @brief Number of endpoints supported */ 688 #define FSL_FEATURE_USBHS_ENDPT_COUNT (8) 689 /* @brief If the USB controller support eUSB PHY */ 690 #define FSL_FEATURE_USBHS_SUPPORT_EUSBn(x) \ 691 (((x) == USB0) ? (0) : \ 692 (((x) == USB1) ? (1) : (-1))) 693 694 /* USBPHY module features */ 695 696 /* @brief USBPHY contain DCD analog module */ 697 #define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (1) 698 /* @brief USBPHY has register TRIM_OVERRIDE_EN */ 699 #define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) 700 /* @brief USBPHY is 28FDSOI */ 701 #define FSL_FEATURE_USBPHY_28FDSOI (1) 702 703 /* USDHC module features */ 704 705 /* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ 706 #define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) 707 /* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ 708 #define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) 709 /* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ 710 #define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) 711 /* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ 712 #define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) 713 /* @brief USDHC has reset control */ 714 #define FSL_FEATURE_USDHC_HAS_RESET (1) 715 /* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ 716 #define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1) 717 /* @brief If USDHC instance support 8 bit width */ 718 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) 719 /* @brief If USDHC instance support HS400 mode */ 720 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) \ 721 (((x) == USDHC0) ? (1) : \ 722 (((x) == USDHC1) ? (0) : (-1))) 723 /* @brief If USDHC instance support 1v8 signal */ 724 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) 725 /* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ 726 #define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) 727 /* @brief Has no VSELECT bit in VEND_SPEC register */ 728 #define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0) 729 /* @brief Has no VS18 bit in HOST_CTRL_CAP register */ 730 #define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) 731 732 /* UTICK module features */ 733 734 /* @brief UTICK does not support power down configure. */ 735 #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) 736 737 /* WWDT module features */ 738 739 /* @brief WWDT does not support oscillator lock. */ 740 #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) 741 /* @brief WWDT does not support power down configure. */ 742 #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) 743 /* @brief soc has reset. */ 744 #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) 745 746 /* XSPI module features */ 747 748 /* @brief XSPI has IPEDERR flag */ 749 #define FSL_FEATURE_XSPI_HAS_FR_IPEDERRn(x) (0) 750 /* @brief XSPI has BFGENCR ALIGN bit */ 751 #define FSL_FEATURE_XSPI_HAS_BFGENCR_ALIGNn(x) (0) 752 /* @brief XSPI has X16 mode */ 753 #define FSL_FEATURE_XSPI_HAS_X16_MODEn(x) (1) 754 /* @brief Delay Elements in DDR Delay Tap */ 755 #define FSL_FEATURE_XSPI_DLL_REF_VALUE_DDR_DELAY_TAP_NUM (4U) 756 /* @brief Delay Elements in SDR Delay Tap */ 757 #define FSL_FEATURE_XSPI_DLL_REF_VALUE_SDR_DELAY_TAP_NUM (7U) 758 /* @brief Delay Elements in bypass offset */ 759 #define FSL_FEATURE_XSPI_DLL_REF_VALUE_BYPASS_OFFSET_DELAY_ELEMENT_COUNT (0U) 760 /* @brief Bypass delay element coarse */ 761 #define FSL_FEATURE_XSPI_DLL_REF_VALUE_BYPASS_DELAY_ELEMENT_COARSE (7U) 762 /* @brief Bypass delay element fine */ 763 #define FSL_FEATURE_XSPI_DLL_REF_VALUE_BYPASS_DELAY_ELEMENT_FINE (0U) 764 /* @brief Autoupdate frequency threshold */ 765 #define FSL_FEATURE_XSPI_DLL_REF_VALUE_AUTOUPDATE_FREQ_THRESHOLD (130000000UL) 766 /* @brief Reference counts of autoupdate x16 enabled */ 767 #define FSL_FEATURE_XSPI_DLL_REF_VALUE_AUTOUPDATE_X16_ENABLED_REF_COUNTER (2U) 768 /* @brief Reference counts of autoupdate x16 disabled */ 769 #define FSL_FEATURE_XSPI_DLL_REF_VALUE_AUTOUPDATE_X16_DISABLED_REF_COUNTER (1U) 770 /* @brief autoupdate x16 enabled resolution */ 771 #define FSL_FEATURE_XSPI_DLL_REF_VALUE_AUTOUPDATE_X16_ENABLED_RES (6U) 772 /* @brief autoupdate x16 disabled resolution */ 773 #define FSL_FEATURE_XSPI_DLL_REF_VALUE_AUTOUPDATE_X16_DISABLE_RES (4U) 774 /* @brief Delay Elements in autoupdate_t_div16 offset */ 775 #define FSL_FEATURE_XSPI_DLL_REF_VALUE_AUTOUPDATE_T_DIV16_OFFSET_DELAY_ELEMENT_COUNT (0U) 776 /* @brief Delay Elements in autoupdate offset */ 777 #define FSL_FEATURE_XSPI_DLL_REF_VALUE_AUTOUPDATE_OFFSET_DELAY_ELEMENT_COUNT (0U) 778 779 #endif /* _MIMXRT798S_cm33_core1_FEATURES_H_ */ 780 781
