1 /* 2 ** ################################################################### 3 ** Version: rev. 1.0, 2018-06-19 4 ** Build: b230105 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2023 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2018-06-19) 20 ** Initial version. 21 ** 22 ** ################################################################### 23 */ 24 25 #ifndef _MIMXRT685S_cm33_FEATURES_H_ 26 #define _MIMXRT685S_cm33_FEATURES_H_ 27 28 /* SOC module features */ 29 30 /* @brief ACMP availability on the SoC. */ 31 #define FSL_FEATURE_SOC_ACMP_COUNT (1) 32 /* @brief CACHE64_CTRL availability on the SoC. */ 33 #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) 34 /* @brief CACHE64_POLSEL availability on the SoC. */ 35 #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) 36 /* @brief CASPER availability on the SoC. */ 37 #define FSL_FEATURE_SOC_CASPER_COUNT (1) 38 /* @brief CLKCTL0 availability on the SoC. */ 39 #define FSL_FEATURE_SOC_CLKCTL0_COUNT (1) 40 /* @brief CLKCTL1 availability on the SoC. */ 41 #define FSL_FEATURE_SOC_CLKCTL1_COUNT (1) 42 /* @brief CRC availability on the SoC. */ 43 #define FSL_FEATURE_SOC_CRC_COUNT (1) 44 /* @brief CTIMER availability on the SoC. */ 45 #define FSL_FEATURE_SOC_CTIMER_COUNT (5) 46 /* @brief DMA availability on the SoC. */ 47 #define FSL_FEATURE_SOC_DMA_COUNT (2) 48 /* @brief DMIC availability on the SoC. */ 49 #define FSL_FEATURE_SOC_DMIC_COUNT (1) 50 /* @brief FLEXCOMM availability on the SoC. */ 51 #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (10) 52 /* @brief FLEXSPI availability on the SoC. */ 53 #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) 54 /* @brief FREQME availability on the SoC. */ 55 #define FSL_FEATURE_SOC_FREQME_COUNT (1) 56 /* @brief GPIO availability on the SoC. */ 57 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 58 /* @brief SECGPIO availability on the SoC. */ 59 #define FSL_FEATURE_SOC_SECGPIO_COUNT (1) 60 /* @brief HASHCRYPT availability on the SoC. */ 61 #define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) 62 /* @brief I2C availability on the SoC. */ 63 #define FSL_FEATURE_SOC_I2C_COUNT (9) 64 /* @brief I3C availability on the SoC. */ 65 #define FSL_FEATURE_SOC_I3C_COUNT (1) 66 /* @brief I2S availability on the SoC. */ 67 #define FSL_FEATURE_SOC_I2S_COUNT (8) 68 /* @brief INPUTMUX availability on the SoC. */ 69 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 70 /* @brief IOPCTL availability on the SoC. */ 71 #define FSL_FEATURE_SOC_IOPCTL_COUNT (1) 72 /* @brief LPADC availability on the SoC. */ 73 #define FSL_FEATURE_SOC_LPADC_COUNT (1) 74 /* @brief MPU availability on the SoC. */ 75 #define FSL_FEATURE_SOC_MPU_COUNT (1) 76 /* @brief MRT availability on the SoC. */ 77 #define FSL_FEATURE_SOC_MRT_COUNT (1) 78 /* @brief MU availability on the SoC. */ 79 #define FSL_FEATURE_SOC_MU_COUNT (1) 80 /* @brief OCOTP availability on the SoC. */ 81 #define FSL_FEATURE_SOC_OCOTP_COUNT (1) 82 /* @brief OSTIMER availability on the SoC. */ 83 #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) 84 /* @brief OTFAD availability on the SoC. */ 85 #define FSL_FEATURE_SOC_OTFAD_COUNT (1) 86 /* @brief PINT availability on the SoC. */ 87 #define FSL_FEATURE_SOC_PINT_COUNT (1) 88 /* @brief PMC availability on the SoC. */ 89 #define FSL_FEATURE_SOC_PMC_COUNT (1) 90 /* @brief POWERQUAD availability on the SoC. */ 91 #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) 92 /* @brief PUF availability on the SoC. */ 93 #define FSL_FEATURE_SOC_PUF_COUNT (1) 94 /* @brief RSTCTL0 availability on the SoC. */ 95 #define FSL_FEATURE_SOC_RSTCTL0_COUNT (1) 96 /* @brief RSTCTL1 availability on the SoC. */ 97 #define FSL_FEATURE_SOC_RSTCTL1_COUNT (1) 98 /* @brief RTC availability on the SoC. */ 99 #define FSL_FEATURE_SOC_RTC_COUNT (1) 100 /* @brief SCT availability on the SoC. */ 101 #define FSL_FEATURE_SOC_SCT_COUNT (1) 102 /* @brief SEMA42 availability on the SoC. */ 103 #define FSL_FEATURE_SOC_SEMA42_COUNT (1) 104 /* @brief SPI availability on the SoC. */ 105 #define FSL_FEATURE_SOC_SPI_COUNT (9) 106 /* @brief SYSCTL0 availability on the SoC. */ 107 #define FSL_FEATURE_SOC_SYSCTL0_COUNT (1) 108 /* @brief SYSCTL1 availability on the SoC. */ 109 #define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) 110 /* @brief TRNG availability on the SoC. */ 111 #define FSL_FEATURE_SOC_TRNG_COUNT (1) 112 /* @brief USART availability on the SoC. */ 113 #define FSL_FEATURE_SOC_USART_COUNT (8) 114 /* @brief USBHSD availability on the SoC. */ 115 #define FSL_FEATURE_SOC_USBHSD_COUNT (1) 116 /* @brief USBHSDCD availability on the SoC. */ 117 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (1) 118 /* @brief USBHSH availability on the SoC. */ 119 #define FSL_FEATURE_SOC_USBHSH_COUNT (1) 120 /* @brief USBPHY availability on the SoC. */ 121 #define FSL_FEATURE_SOC_USBPHY_COUNT (1) 122 /* @brief USDHC availability on the SoC. */ 123 #define FSL_FEATURE_SOC_USDHC_COUNT (2) 124 /* @brief UTICK availability on the SoC. */ 125 #define FSL_FEATURE_SOC_UTICK_COUNT (1) 126 /* @brief WWDT availability on the SoC. */ 127 #define FSL_FEATURE_SOC_WWDT_COUNT (2) 128 129 /* LPADC module features */ 130 131 /* @brief FIFO availability on the SoC. */ 132 #define FSL_FEATURE_LPADC_FIFO_COUNT (1) 133 /* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ 134 #define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) 135 /* @brief Has differential mode (bitfield CMDLn[DIFF]). */ 136 #define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (1) 137 /* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ 138 #define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (1) 139 /* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ 140 #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (0) 141 /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ 142 #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (0) 143 /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ 144 #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (0) 145 /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ 146 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (0) 147 /* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ 148 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (0) 149 /* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ 150 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (0) 151 /* @brief Has internal clock (bitfield CFG[ADCKEN]). */ 152 #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) 153 /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ 154 #define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) 155 /* @brief Has calibration (bitfield CFG[CALOFS]). */ 156 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) 157 /* @brief Has offset trim (register OFSTRIM). */ 158 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (0) 159 /* @brief Has power select (bitfield CFG[PWRSEL]). */ 160 #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) 161 /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ 162 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) 163 /* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ 164 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) 165 /* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ 166 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) 167 /* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ 168 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) 169 /* @brief Conversion averaged bitfiled width. */ 170 #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) 171 172 /* CACHE64_CTRL module features */ 173 174 /* @brief Cache Line size in byte. */ 175 #define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (32) 176 177 /* CACHE64_POLSEL module features */ 178 179 /* No feature definitions */ 180 181 /* CASPER module features */ 182 183 /* @brief Base address of the CASPER dedicated RAM. */ 184 #define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x40152000u) 185 186 /* ACMP module features */ 187 188 /* @brief Has CMP_C3. */ 189 #define FSL_FEATURE_ACMP_HAS_C3_REG (1) 190 /* @brief Has C0 LINKEN Bit */ 191 #define FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT (1) 192 /* @brief Has C0 OFFSET Bit */ 193 #define FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT (0) 194 /* @brief Has C1 INPSEL Bit */ 195 #define FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT (0) 196 /* @brief Has C1 INNSEL Bit */ 197 #define FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT (0) 198 /* @brief Has C1 DACOE Bit */ 199 #define FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT (0) 200 /* @brief Has C1 DMODE Bit */ 201 #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) 202 /* @brief Has C2 RRE Bit */ 203 #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) 204 205 /* CRC module features */ 206 207 /* @brief Has data register with name CRC */ 208 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 209 210 /* CTIMER module features */ 211 212 /* @brief CTIMER has no capture channel. */ 213 #define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) 214 /* @brief CTIMER has no capture 2 interrupt. */ 215 #define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) 216 /* @brief CTIMER capture 3 interrupt. */ 217 #define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) 218 /* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ 219 #define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) 220 /* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ 221 #define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) 222 /* @brief CTIMER Has register MSR */ 223 #define FSL_FEATURE_CTIMER_HAS_MSR (1) 224 225 /* DMA module features */ 226 227 /* @brief Number of channels */ 228 #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) (33) 229 /* @brief Number of all DMA channels */ 230 #define FSL_FEATURE_DMA_ALL_CHANNELS (66) 231 /* @brief Max Number of DMA channels */ 232 #define FSL_FEATURE_DMA_MAX_CHANNELS (33) 233 /* @brief Align size of DMA descriptor */ 234 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (1024) 235 /* @brief DMA head link descriptor table align size */ 236 #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) 237 238 /* DMIC module features */ 239 240 /* @brief Number of channels */ 241 #define FSL_FEATURE_DMIC_CHANNEL_NUM (8) 242 /* @brief DMIC channel support stereo data */ 243 #define FSL_FEATURE_DMIC_IO_HAS_STEREO_2_4_6 (1) 244 /* @brief DMIC does not support bypass channel clock */ 245 #define FSL_FEATURE_DMIC_IO_HAS_NO_BYPASS (1) 246 /* @brief DMIC channel FIFO register support sign extended */ 247 #define FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND (1) 248 /* @brief DMIC has no IOCFG register */ 249 #define FSL_FEATURE_DMIC_HAS_NO_IOCFG (1) 250 /* @brief DMIC has decimator reset function */ 251 #define FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC (1) 252 /* @brief DMIC has global channel synchronization function */ 253 #define FSL_FEATURE_DMIC_HAS_GLOBAL_SYNC_FUNC (1) 254 255 /* FLEXCOMM module features */ 256 257 /* @brief FLEXCOMM0 USART INDEX 0 */ 258 #define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) 259 /* @brief FLEXCOMM0 SPI INDEX 0 */ 260 #define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) 261 /* @brief FLEXCOMM0 I2C INDEX 0 */ 262 #define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) 263 /* @brief FLEXCOMM0 I2S INDEX 0 */ 264 #define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) 265 /* @brief FLEXCOMM1 USART INDEX 1 */ 266 #define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) 267 /* @brief FLEXCOMM1 SPI INDEX 1 */ 268 #define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) 269 /* @brief FLEXCOMM1 I2C INDEX 1 */ 270 #define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) 271 /* @brief FLEXCOMM1 I2S INDEX 1 */ 272 #define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) 273 /* @brief FLEXCOMM2 USART INDEX 2 */ 274 #define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) 275 /* @brief FLEXCOMM2 SPI INDEX 2 */ 276 #define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) 277 /* @brief FLEXCOMM2 I2C INDEX 2 */ 278 #define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) 279 /* @brief FLEXCOMM2 I2S INDEX 2 */ 280 #define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) 281 /* @brief FLEXCOMM3 USART INDEX 3 */ 282 #define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) 283 /* @brief FLEXCOMM3 SPI INDEX 3 */ 284 #define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) 285 /* @brief FLEXCOMM3 I2C INDEX 3 */ 286 #define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) 287 /* @brief FLEXCOMM3 I2S INDEX 3 */ 288 #define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) 289 /* @brief FLEXCOMM4 USART INDEX 4 */ 290 #define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) 291 /* @brief FLEXCOMM4 SPI INDEX 4 */ 292 #define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) 293 /* @brief FLEXCOMM4 I2C INDEX 4 */ 294 #define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) 295 /* @brief FLEXCOMM4 I2S INDEX 4 */ 296 #define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) 297 /* @brief FLEXCOMM5 USART INDEX 5 */ 298 #define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) 299 /* @brief FLEXCOMM5 SPI INDEX 5 */ 300 #define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) 301 /* @brief FLEXCOMM5 I2C INDEX 5 */ 302 #define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) 303 /* @brief FLEXCOMM5 I2S INDEX 5 */ 304 #define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) 305 /* @brief FLEXCOMM6 USART INDEX 6 */ 306 #define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) 307 /* @brief FLEXCOMM6 SPI INDEX 6 */ 308 #define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) 309 /* @brief FLEXCOMM6 I2C INDEX 6 */ 310 #define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) 311 /* @brief FLEXCOMM6 I2S INDEX 6 */ 312 #define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) 313 /* @brief FLEXCOMM7 USART INDEX 7 */ 314 #define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) 315 /* @brief FLEXCOMM7 SPI INDEX 7 */ 316 #define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) 317 /* @brief FLEXCOMM7 I2C INDEX 7 */ 318 #define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) 319 /* @brief FLEXCOMM7 I2S INDEX 7 */ 320 #define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) 321 /* @brief FLEXCOMM14 SPI(HS_SPI) INDEX 14 */ 322 #define FSL_FEATURE_FLEXCOMM14_SPI_INDEX (14) 323 /* @brief FLEXCOMM15 I2C INDEX 15 */ 324 #define FSL_FEATURE_FLEXCOMM15_I2C_INDEX (15) 325 /* @brief I2S has DMIC interconnection */ 326 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) \ 327 (((x) == FLEXCOMM0) ? (1) : \ 328 (((x) == FLEXCOMM1) ? (0) : \ 329 (((x) == FLEXCOMM2) ? (0) : \ 330 (((x) == FLEXCOMM3) ? (0) : \ 331 (((x) == FLEXCOMM4) ? (0) : \ 332 (((x) == FLEXCOMM5) ? (0) : \ 333 (((x) == FLEXCOMM6) ? (0) : \ 334 (((x) == FLEXCOMM7) ? (0) : \ 335 (((x) == FLEXCOMM14) ? (0) : \ 336 (((x) == FLEXCOMM15) ? (0) : (-1))))))))))) 337 338 /* FLEXSPI module features */ 339 340 /* @brief FlexSPI AHB buffer count */ 341 #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) 342 /* @brief FlexSPI has no MCR0 ARDFEN bit */ 343 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) 344 /* @brief FlexSPI has no MCR0 ATDFEN bit */ 345 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) 346 /* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ 347 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) 348 /* @brief FLEXSPI has no IP parallel mode. */ 349 #define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) 350 /* @brief FLEXSPI has no AHB parallel mode. */ 351 #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) 352 /* @brief FLEXSPI support address shift. */ 353 #define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) 354 355 /* GPIO module features */ 356 357 /* @brief GPIO has interrupts */ 358 #define FSL_FEATURE_GPIO_HAS_INTERRUPT (1) 359 /* @brief GPIO DIRSET and DIRCLR register. */ 360 #define FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR (1) 361 362 /* HASHCRYPT module features */ 363 364 /* @brief hashcrypt has reload feature */ 365 #define FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE (1) 366 367 /* I2S module features */ 368 369 /* @brief I2S support dual channel transfer. */ 370 #define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1) 371 /* @brief I2S has DMIC interconnection. */ 372 #define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (1) 373 374 /* I3C module features */ 375 376 /* @brief Has TERM bitfile in MERRWARN register. */ 377 #define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) 378 /* @brief SOC has no reset driver. */ 379 #define FSL_FEATURE_I3C_HAS_NO_RESET (0) 380 /* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ 381 #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) 382 /* @brief Register SCONFIG do not have IDRAND bitfield. */ 383 #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) 384 /* @brief Register SCONFIG has HDROK bitfield. */ 385 #define FSL_FEATURE_I3C_HAS_HDROK (0) 386 387 /* INPUTMUX module features */ 388 389 /* @brief Number of channels */ 390 #define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) 391 392 /* MRT module features */ 393 394 /* @brief number of channels. */ 395 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) 396 397 /* MU module features */ 398 399 /* @brief MU Has register CCR */ 400 #define FSL_FEATURE_MU_HAS_CCR (0) 401 /* @brief MU Has register SR[RS], BSR[ARS] */ 402 #define FSL_FEATURE_MU_HAS_SR_RS (1) 403 /* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */ 404 #define FSL_FEATURE_MU_HAS_RESET_INT (0) 405 /* @brief MU Has register SR[MURIP] */ 406 #define FSL_FEATURE_MU_HAS_SR_MURIP (0) 407 /* @brief brief MU Has register SR[HRIP] */ 408 #define FSL_FEATURE_MU_HAS_SR_HRIP (0) 409 /* @brief brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */ 410 #define FSL_FEATURE_MU_NO_CLKE (1) 411 /* @brief brief MU does not support NMI, CR[NMI]. */ 412 #define FSL_FEATURE_MU_NO_NMI (1) 413 /* @brief brief MU does not support hold the other core reset. CR[RSTH] or CCR[RSTH]. */ 414 #define FSL_FEATURE_MU_NO_RSTH (1) 415 /* @brief brief MU does not supports MU reset, CR[MUR]. */ 416 #define FSL_FEATURE_MU_NO_MUR (0) 417 /* @brief brief MU does not supports hardware reset, CR[HR] or CCR[HR]. */ 418 #define FSL_FEATURE_MU_NO_HR (1) 419 /* @brief brief MU supports mask the hardware reset. CR[HRM] or CCR[HRM]. */ 420 #define FSL_FEATURE_MU_HAS_HRM (0) 421 422 /* OTFAD module features */ 423 424 /* @brief OTFAD has Security Violation Mode (SVM) */ 425 #define FSL_FEATURE_OTFAD_HAS_SVM_MODE (0) 426 /* @brief OTFAD has Key Blob Processing */ 427 #define FSL_FEATURE_OTFAD_HAS_KEYBLOB_PROCESSING (0) 428 /* @brief OTFAD has interrupt request enable */ 429 #define FSL_FEATURE_OTFAD_HAS_HAS_IRQ_ENABLE (0) 430 /* @brief OTFAD has Force Error */ 431 #define FSL_FEATURE_OTFAD_HAS_FORCE_ERR (0) 432 433 /* PINT module features */ 434 435 /* @brief Number of connected outputs */ 436 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) 437 438 /* PMC module features */ 439 440 /* @brief Has no OS Timer control register in PMC. */ 441 #define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1) 442 443 /* PUF module features */ 444 445 /* @brief PUF need to setup SRAM manually */ 446 #define FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL (1) 447 /* @brief PUF has SHIFT_STATUS register. */ 448 #define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (0) 449 /* @brief PUF has IDXBLK_SHIFT register. */ 450 #define FSL_FEATURE_PUF_HAS_IDXBLK_SHIFT (0) 451 452 /* RTC module features */ 453 454 /* @brief RTC does not support reset from RSTCTL. */ 455 #define FSL_FEATURE_RTC_HAS_NO_RESET (1) 456 457 /* SCT module features */ 458 459 /* @brief Number of events */ 460 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) 461 /* @brief Number of states */ 462 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) 463 /* @brief Number of match capture */ 464 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) 465 /* @brief Number of outputs */ 466 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) 467 468 /* SEMA42 module features */ 469 470 /* @brief Gate counts */ 471 #define FSL_FEATURE_SEMA42_GATE_COUNT (16) 472 473 /* SPI module features */ 474 475 /* @brief SSEL pin count. */ 476 #define FSL_FEATURE_SPI_SSEL_COUNT (4) 477 478 /* TRNG module features */ 479 480 /* No feature definitions */ 481 482 /* USBHSD module features */ 483 484 /* @brief Size of the USB dedicated RAM */ 485 #define FSL_FEATURE_USBHSD_USB_RAM (0x00004000) 486 /* @brief Base address of the USB dedicated RAM */ 487 #define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40140000) 488 /* @brief USBHSD version */ 489 #define FSL_FEATURE_USBHSD_VERSION (300) 490 /* @brief Number of the endpoint in USB HS */ 491 #define FSL_FEATURE_USBHSD_EP_NUM (6) 492 /* @brief The controller doesn't exit HS mode automatically after vbus becomes invalid */ 493 #define FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE (1) 494 495 /* USBHSH module features */ 496 497 /* @brief Size of the USB dedicated RAM */ 498 #define FSL_FEATURE_USBHSH_USB_RAM (0x00004000) 499 /* @brief Base address of the USB dedicated RAM */ 500 #define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40140000) 501 /* @brief USBHSH version */ 502 #define FSL_FEATURE_USBHSH_VERSION (300) 503 /* @brief USBHSH has packet turnaround time-out register */ 504 #define FSL_FEATURE_USBHSH_HAS_TURNAROUND_TIMEOUT (0) 505 506 /* USBPHY module features */ 507 508 /* @brief USBPHY contain DCD analog module */ 509 #define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (1) 510 /* @brief USBPHY has register TRIM_OVERRIDE_EN */ 511 #define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) 512 /* @brief USBPHY is 28FDSOI */ 513 #define FSL_FEATURE_USBPHY_28FDSOI (0) 514 515 /* USDHC module features */ 516 517 /* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ 518 #define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) 519 /* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ 520 #define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) 521 /* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ 522 #define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) 523 /* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ 524 #define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) 525 /* @brief USDHC has reset control */ 526 #define FSL_FEATURE_USDHC_HAS_RESET (1) 527 /* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ 528 #define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) 529 /* @brief If USDHC instance support 8 bit width */ 530 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) 531 /* @brief If USDHC instance support HS400 mode */ 532 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) \ 533 (((x) == USDHC0) ? (1) : \ 534 (((x) == USDHC1) ? (0) : (-1))) 535 /* @brief If USDHC instance support 1v8 signal */ 536 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) 537 /* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ 538 #define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (0) 539 540 /* UTICK module features */ 541 542 /* @brief UTICK does not support power down configure. */ 543 #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) 544 545 /* WWDT module features */ 546 547 /* @brief WWDT does not support oscillator lock. */ 548 #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) 549 /* @brief WWDT does not support power down configure. */ 550 #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) 551 552 #endif /* _MIMXRT685S_cm33_FEATURES_H_ */ 553 554
