1 /* 2 ** ################################################################### 3 ** Version: rev. 1.0, 2018-06-19 4 ** Build: b240521 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2024 NXP 11 ** SPDX-License-Identifier: BSD-3-Clause 12 ** 13 ** http: www.nxp.com 14 ** mail: support@nxp.com 15 ** 16 ** Revisions: 17 ** - rev. 1.0 (2018-06-19) 18 ** Initial version. 19 ** 20 ** ################################################################### 21 */ 22 23 #ifndef _MIMXRT633S_FEATURES_H_ 24 #define _MIMXRT633S_FEATURES_H_ 25 26 /* SOC module features */ 27 28 /* @brief ACMP availability on the SoC. */ 29 #define FSL_FEATURE_SOC_ACMP_COUNT (1) 30 /* @brief CACHE64_CTRL availability on the SoC. */ 31 #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) 32 /* @brief CACHE64_POLSEL availability on the SoC. */ 33 #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) 34 /* @brief CASPER availability on the SoC. */ 35 #define FSL_FEATURE_SOC_CASPER_COUNT (1) 36 /* @brief CLKCTL0 availability on the SoC. */ 37 #define FSL_FEATURE_SOC_CLKCTL0_COUNT (1) 38 /* @brief CLKCTL1 availability on the SoC. */ 39 #define FSL_FEATURE_SOC_CLKCTL1_COUNT (1) 40 /* @brief CRC availability on the SoC. */ 41 #define FSL_FEATURE_SOC_CRC_COUNT (1) 42 /* @brief CTIMER availability on the SoC. */ 43 #define FSL_FEATURE_SOC_CTIMER_COUNT (5) 44 /* @brief DMA availability on the SoC. */ 45 #define FSL_FEATURE_SOC_DMA_COUNT (2) 46 /* @brief DMIC availability on the SoC. */ 47 #define FSL_FEATURE_SOC_DMIC_COUNT (1) 48 /* @brief FLEXCOMM availability on the SoC. */ 49 #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (10) 50 /* @brief FLEXSPI availability on the SoC. */ 51 #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) 52 /* @brief FREQME availability on the SoC. */ 53 #define FSL_FEATURE_SOC_FREQME_COUNT (1) 54 /* @brief GPIO availability on the SoC. */ 55 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 56 /* @brief SECGPIO availability on the SoC. */ 57 #define FSL_FEATURE_SOC_SECGPIO_COUNT (1) 58 /* @brief HASHCRYPT availability on the SoC. */ 59 #define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) 60 /* @brief I2C availability on the SoC. */ 61 #define FSL_FEATURE_SOC_I2C_COUNT (9) 62 /* @brief I3C availability on the SoC. */ 63 #define FSL_FEATURE_SOC_I3C_COUNT (1) 64 /* @brief I2S availability on the SoC. */ 65 #define FSL_FEATURE_SOC_I2S_COUNT (8) 66 /* @brief INPUTMUX availability on the SoC. */ 67 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 68 /* @brief IOPCTL availability on the SoC. */ 69 #define FSL_FEATURE_SOC_IOPCTL_COUNT (1) 70 /* @brief LPADC availability on the SoC. */ 71 #define FSL_FEATURE_SOC_LPADC_COUNT (1) 72 /* @brief MPU availability on the SoC. */ 73 #define FSL_FEATURE_SOC_MPU_COUNT (1) 74 /* @brief MRT availability on the SoC. */ 75 #define FSL_FEATURE_SOC_MRT_COUNT (1) 76 /* @brief MU availability on the SoC. */ 77 #define FSL_FEATURE_SOC_MU_COUNT (1) 78 /* @brief OCOTP availability on the SoC. */ 79 #define FSL_FEATURE_SOC_OCOTP_COUNT (1) 80 /* @brief OSTIMER availability on the SoC. */ 81 #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) 82 /* @brief OTFAD availability on the SoC. */ 83 #define FSL_FEATURE_SOC_OTFAD_COUNT (1) 84 /* @brief PINT availability on the SoC. */ 85 #define FSL_FEATURE_SOC_PINT_COUNT (1) 86 /* @brief PMC availability on the SoC. */ 87 #define FSL_FEATURE_SOC_PMC_COUNT (1) 88 /* @brief POWERQUAD availability on the SoC. */ 89 #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) 90 /* @brief PUF availability on the SoC. */ 91 #define FSL_FEATURE_SOC_PUF_COUNT (1) 92 /* @brief RSTCTL0 availability on the SoC. */ 93 #define FSL_FEATURE_SOC_RSTCTL0_COUNT (1) 94 /* @brief RSTCTL1 availability on the SoC. */ 95 #define FSL_FEATURE_SOC_RSTCTL1_COUNT (1) 96 /* @brief RTC availability on the SoC. */ 97 #define FSL_FEATURE_SOC_RTC_COUNT (1) 98 /* @brief SCT availability on the SoC. */ 99 #define FSL_FEATURE_SOC_SCT_COUNT (1) 100 /* @brief SEMA42 availability on the SoC. */ 101 #define FSL_FEATURE_SOC_SEMA42_COUNT (1) 102 /* @brief SPI availability on the SoC. */ 103 #define FSL_FEATURE_SOC_SPI_COUNT (9) 104 /* @brief SYSCTL0 availability on the SoC. */ 105 #define FSL_FEATURE_SOC_SYSCTL0_COUNT (1) 106 /* @brief SYSCTL1 availability on the SoC. */ 107 #define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) 108 /* @brief TRNG availability on the SoC. */ 109 #define FSL_FEATURE_SOC_TRNG_COUNT (1) 110 /* @brief USART availability on the SoC. */ 111 #define FSL_FEATURE_SOC_USART_COUNT (8) 112 /* @brief USBHSD availability on the SoC. */ 113 #define FSL_FEATURE_SOC_USBHSD_COUNT (1) 114 /* @brief USBHSDCD availability on the SoC. */ 115 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (1) 116 /* @brief USBHSH availability on the SoC. */ 117 #define FSL_FEATURE_SOC_USBHSH_COUNT (1) 118 /* @brief USBPHY availability on the SoC. */ 119 #define FSL_FEATURE_SOC_USBPHY_COUNT (1) 120 /* @brief USDHC availability on the SoC. */ 121 #define FSL_FEATURE_SOC_USDHC_COUNT (2) 122 /* @brief UTICK availability on the SoC. */ 123 #define FSL_FEATURE_SOC_UTICK_COUNT (1) 124 /* @brief WWDT availability on the SoC. */ 125 #define FSL_FEATURE_SOC_WWDT_COUNT (2) 126 127 /* LPADC module features */ 128 129 /* @brief FIFO availability on the SoC. */ 130 #define FSL_FEATURE_LPADC_FIFO_COUNT (1) 131 /* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ 132 #define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) 133 /* @brief Has differential mode (bitfield CMDLn[DIFF]). */ 134 #define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (1) 135 /* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ 136 #define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (1) 137 /* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ 138 #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (0) 139 /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ 140 #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (0) 141 /* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ 142 #define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) 143 /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ 144 #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (0) 145 /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ 146 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (0) 147 /* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ 148 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (0) 149 /* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ 150 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (0) 151 /* @brief Has internal clock (bitfield CFG[ADCKEN]). */ 152 #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) 153 /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ 154 #define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) 155 /* @brief Has calibration (bitfield CFG[CALOFS]). */ 156 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) 157 /* @brief Has offset trim (register OFSTRIM). */ 158 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (0) 159 /* @brief Has Trigger status register. */ 160 #define FSL_FEATURE_LPADC_HAS_TSTAT (0) 161 /* @brief Has power select (bitfield CFG[PWRSEL]). */ 162 #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) 163 /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ 164 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) 165 /* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ 166 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) 167 /* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ 168 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) 169 /* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ 170 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) 171 /* @brief Conversion averaged bitfiled width. */ 172 #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) 173 /* @brief Has B side channels. */ 174 #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) 175 /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ 176 #define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (0) 177 /* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ 178 #define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (0) 179 /* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ 180 #define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (0) 181 /* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ 182 #define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (0) 183 /* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ 184 #define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (0) 185 /* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ 186 #define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (0) 187 /* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ 188 #define FSL_FEATURE_LPADC_HAS_CFG_TRES (0) 189 /* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ 190 #define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (0) 191 /* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ 192 #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (0) 193 /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ 194 #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (1) 195 196 /* CACHE64_CTRL module features */ 197 198 /* @brief Cache Line size in byte. */ 199 #define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (32) 200 201 /* CACHE64_POLSEL module features */ 202 203 /* No feature definitions */ 204 205 /* CASPER module features */ 206 207 /* @brief Base address of the CASPER dedicated RAM. */ 208 #define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x40152000u) 209 210 /* ACMP module features */ 211 212 /* @brief Has CMP_C3. */ 213 #define FSL_FEATURE_ACMP_HAS_C3_REG (1) 214 /* @brief Has C0 LINKEN Bit */ 215 #define FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT (1) 216 /* @brief Has C0 OFFSET Bit */ 217 #define FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT (0) 218 /* @brief Has C0 HYSTCTR Bit */ 219 #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) 220 /* @brief Has C1 INPSEL Bit */ 221 #define FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT (0) 222 /* @brief Has C1 INNSEL Bit */ 223 #define FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT (0) 224 /* @brief Has C1 DACOE Bit */ 225 #define FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT (0) 226 /* @brief Has C1 DMODE Bit */ 227 #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) 228 /* @brief Has C2 RRE Bit */ 229 #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) 230 231 /* CRC module features */ 232 233 /* @brief Has data register with name CRC */ 234 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 235 236 /* CTIMER module features */ 237 238 /* @brief CTIMER has no capture channel. */ 239 #define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) 240 /* @brief CTIMER has no capture 2 interrupt. */ 241 #define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) 242 /* @brief CTIMER capture 3 interrupt. */ 243 #define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) 244 /* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ 245 #define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) 246 /* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ 247 #define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) 248 /* @brief CTIMER Has register MSR */ 249 #define FSL_FEATURE_CTIMER_HAS_MSR (1) 250 251 /* DMA module features */ 252 253 /* @brief Number of channels */ 254 #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) (33) 255 /* @brief Number of all DMA channels */ 256 #define FSL_FEATURE_DMA_ALL_CHANNELS (66) 257 /* @brief Max Number of DMA channels */ 258 #define FSL_FEATURE_DMA_MAX_CHANNELS (33) 259 /* @brief Align size of DMA descriptor */ 260 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (1024) 261 /* @brief DMA head link descriptor table align size */ 262 #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) 263 264 /* DMIC module features */ 265 266 /* @brief Number of channels */ 267 #define FSL_FEATURE_DMIC_CHANNEL_NUM (8) 268 /* @brief DMIC channel support stereo data */ 269 #define FSL_FEATURE_DMIC_IO_HAS_STEREO_2_4_6 (1) 270 /* @brief DMIC does not support bypass channel clock */ 271 #define FSL_FEATURE_DMIC_IO_HAS_NO_BYPASS (1) 272 /* @brief DMIC channel FIFO register support sign extended */ 273 #define FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND (1) 274 /* @brief DMIC has no IOCFG register */ 275 #define FSL_FEATURE_DMIC_HAS_NO_IOCFG (1) 276 /* @brief DMIC has decimator reset function */ 277 #define FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC (1) 278 /* @brief DMIC has global channel synchronization function */ 279 #define FSL_FEATURE_DMIC_HAS_GLOBAL_SYNC_FUNC (1) 280 281 /* FLEXCOMM module features */ 282 283 /* @brief FLEXCOMM0 USART INDEX 0 */ 284 #define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) 285 /* @brief FLEXCOMM0 SPI INDEX 0 */ 286 #define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) 287 /* @brief FLEXCOMM0 I2C INDEX 0 */ 288 #define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) 289 /* @brief FLEXCOMM0 I2S INDEX 0 */ 290 #define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) 291 /* @brief FLEXCOMM1 USART INDEX 1 */ 292 #define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) 293 /* @brief FLEXCOMM1 SPI INDEX 1 */ 294 #define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) 295 /* @brief FLEXCOMM1 I2C INDEX 1 */ 296 #define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) 297 /* @brief FLEXCOMM1 I2S INDEX 1 */ 298 #define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) 299 /* @brief FLEXCOMM2 USART INDEX 2 */ 300 #define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) 301 /* @brief FLEXCOMM2 SPI INDEX 2 */ 302 #define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) 303 /* @brief FLEXCOMM2 I2C INDEX 2 */ 304 #define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) 305 /* @brief FLEXCOMM2 I2S INDEX 2 */ 306 #define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) 307 /* @brief FLEXCOMM3 USART INDEX 3 */ 308 #define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) 309 /* @brief FLEXCOMM3 SPI INDEX 3 */ 310 #define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) 311 /* @brief FLEXCOMM3 I2C INDEX 3 */ 312 #define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) 313 /* @brief FLEXCOMM3 I2S INDEX 3 */ 314 #define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) 315 /* @brief FLEXCOMM4 USART INDEX 4 */ 316 #define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) 317 /* @brief FLEXCOMM4 SPI INDEX 4 */ 318 #define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) 319 /* @brief FLEXCOMM4 I2C INDEX 4 */ 320 #define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) 321 /* @brief FLEXCOMM4 I2S INDEX 4 */ 322 #define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) 323 /* @brief FLEXCOMM5 USART INDEX 5 */ 324 #define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) 325 /* @brief FLEXCOMM5 SPI INDEX 5 */ 326 #define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) 327 /* @brief FLEXCOMM5 I2C INDEX 5 */ 328 #define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) 329 /* @brief FLEXCOMM5 I2S INDEX 5 */ 330 #define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) 331 /* @brief FLEXCOMM6 USART INDEX 6 */ 332 #define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) 333 /* @brief FLEXCOMM6 SPI INDEX 6 */ 334 #define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) 335 /* @brief FLEXCOMM6 I2C INDEX 6 */ 336 #define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) 337 /* @brief FLEXCOMM6 I2S INDEX 6 */ 338 #define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) 339 /* @brief FLEXCOMM7 USART INDEX 7 */ 340 #define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) 341 /* @brief FLEXCOMM7 SPI INDEX 7 */ 342 #define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) 343 /* @brief FLEXCOMM7 I2C INDEX 7 */ 344 #define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) 345 /* @brief FLEXCOMM7 I2S INDEX 7 */ 346 #define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) 347 /* @brief FLEXCOMM14 SPI(HS_SPI) INDEX 14 */ 348 #define FSL_FEATURE_FLEXCOMM14_SPI_INDEX (14) 349 /* @brief FLEXCOMM15 I2C INDEX 15 */ 350 #define FSL_FEATURE_FLEXCOMM15_I2C_INDEX (15) 351 /* @brief I2S has DMIC interconnection */ 352 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) \ 353 (((x) == FLEXCOMM0) ? (1) : \ 354 (((x) == FLEXCOMM1) ? (0) : \ 355 (((x) == FLEXCOMM2) ? (0) : \ 356 (((x) == FLEXCOMM3) ? (0) : \ 357 (((x) == FLEXCOMM4) ? (0) : \ 358 (((x) == FLEXCOMM5) ? (0) : \ 359 (((x) == FLEXCOMM6) ? (0) : \ 360 (((x) == FLEXCOMM7) ? (0) : \ 361 (((x) == FLEXCOMM14) ? (0) : \ 362 (((x) == FLEXCOMM15) ? (0) : (-1))))))))))) 363 364 /* FLEXSPI module features */ 365 366 /* @brief FlexSPI AHB buffer count */ 367 #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) 368 /* @brief FlexSPI has no MCR0 ARDFEN bit */ 369 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) 370 /* @brief FlexSPI has no MCR0 ATDFEN bit */ 371 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) 372 /* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ 373 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) 374 /* @brief FLEXSPI has no IP parallel mode. */ 375 #define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) 376 /* @brief FLEXSPI has no AHB parallel mode. */ 377 #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) 378 /* @brief FLEXSPI support address shift. */ 379 #define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) 380 /* @brief FlexSPI AHB RX buffer size (byte) */ 381 #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) 382 383 /* GPIO module features */ 384 385 /* @brief GPIO has interrupts */ 386 #define FSL_FEATURE_GPIO_HAS_INTERRUPT (1) 387 /* @brief GPIO DIRSET and DIRCLR register. */ 388 #define FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR (1) 389 390 /* HASHCRYPT module features */ 391 392 /* @brief hashcrypt has reload feature */ 393 #define FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE (1) 394 395 /* I2S module features */ 396 397 /* @brief I2S support dual channel transfer. */ 398 #define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1) 399 /* @brief I2S has DMIC interconnection. */ 400 #define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (1) 401 402 /* I3C module features */ 403 404 /* @brief Has TERM bitfile in MERRWARN register. */ 405 #define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) 406 /* @brief SOC has no reset driver. */ 407 #define FSL_FEATURE_I3C_HAS_NO_RESET (0) 408 /* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ 409 #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) 410 /* @brief Register SCONFIG do not have IDRAND bitfield. */ 411 #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) 412 /* @brief Register SCONFIG has HDROK bitfield. */ 413 #define FSL_FEATURE_I3C_HAS_HDROK (0) 414 /* @brief SOC doesn't support slave IBI/MR/HJ. */ 415 #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) 416 /* @brief Has ERRATA_052123. */ 417 #define FSL_FEATURE_I3C_HAS_ERRATA_052123 (1) 418 /* @brief Has no the master write data register for DMA. */ 419 #define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (1) 420 421 /* INPUTMUX module features */ 422 423 /* @brief Inputmux has DMA Request Enable */ 424 #define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) 425 /* @brief Inputmux has channel mux control */ 426 #define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) 427 428 /* MRT module features */ 429 430 /* @brief number of channels. */ 431 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) 432 433 /* MU module features */ 434 435 /* @brief MU Has register CCR */ 436 #define FSL_FEATURE_MU_HAS_CCR (0) 437 /* @brief MU Has register SR[RS], BSR[ARS] */ 438 #define FSL_FEATURE_MU_HAS_SR_RS (1) 439 /* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */ 440 #define FSL_FEATURE_MU_HAS_RESET_INT (0) 441 /* @brief MU Has register SR[MURIP] */ 442 #define FSL_FEATURE_MU_HAS_SR_MURIP (0) 443 /* @brief brief MU Has register SR[HRIP] */ 444 #define FSL_FEATURE_MU_HAS_SR_HRIP (0) 445 /* @brief brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */ 446 #define FSL_FEATURE_MU_NO_CLKE (1) 447 /* @brief brief MU does not support NMI, CR[NMI]. */ 448 #define FSL_FEATURE_MU_NO_NMI (1) 449 /* @brief brief MU does not support hold the other core reset. CR[RSTH] or CCR[RSTH]. */ 450 #define FSL_FEATURE_MU_NO_RSTH (1) 451 /* @brief brief MU does not supports MU reset, CR[MUR]. */ 452 #define FSL_FEATURE_MU_NO_MUR (0) 453 /* @brief brief MU does not supports hardware reset, CR[HR] or CCR[HR]. */ 454 #define FSL_FEATURE_MU_NO_HR (1) 455 /* @brief brief MU supports mask the hardware reset. CR[HRM] or CCR[HRM]. */ 456 #define FSL_FEATURE_MU_HAS_HRM (0) 457 458 /* OTFAD module features */ 459 460 /* @brief OTFAD has Security Violation Mode (SVM) */ 461 #define FSL_FEATURE_OTFAD_HAS_SVM_MODE (0) 462 /* @brief OTFAD has Key Blob Processing */ 463 #define FSL_FEATURE_OTFAD_HAS_KEYBLOB_PROCESSING (0) 464 /* @brief OTFAD has interrupt request enable */ 465 #define FSL_FEATURE_OTFAD_HAS_HAS_IRQ_ENABLE (0) 466 /* @brief OTFAD has Force Error */ 467 #define FSL_FEATURE_OTFAD_HAS_FORCE_ERR (0) 468 469 /* PINT module features */ 470 471 /* @brief Number of connected outputs */ 472 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) 473 474 /* PMC module features */ 475 476 /* @brief Has no OS Timer control register in PMC. */ 477 #define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1) 478 479 /* PUF module features */ 480 481 /* @brief PUF need to setup SRAM manually */ 482 #define FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL (1) 483 /* @brief PUF has SHIFT_STATUS register. */ 484 #define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (0) 485 /* @brief PUF has IDXBLK_SHIFT register. */ 486 #define FSL_FEATURE_PUF_HAS_IDXBLK_SHIFT (0) 487 488 /* RTC module features */ 489 490 /* @brief RTC has no reset control */ 491 #define FSL_FEATURE_RTC_HAS_NO_RESET (1) 492 /* @brief Has SUBSEC Register (register SUBSEC) */ 493 #define FSL_FEATURE_RTC_HAS_SUBSEC (1) 494 495 /* SCT module features */ 496 497 /* @brief Number of events */ 498 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) 499 /* @brief Number of states */ 500 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) 501 /* @brief Number of match capture */ 502 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) 503 /* @brief Number of outputs */ 504 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) 505 506 /* SEMA42 module features */ 507 508 /* @brief Gate counts */ 509 #define FSL_FEATURE_SEMA42_GATE_COUNT (16) 510 511 /* SPI module features */ 512 513 /* @brief SSEL pin count. */ 514 #define FSL_FEATURE_SPI_SSEL_COUNT (4) 515 516 /* TRNG module features */ 517 518 /* No feature definitions */ 519 520 /* USBHSD module features */ 521 522 /* @brief Size of the USB dedicated RAM */ 523 #define FSL_FEATURE_USBHSD_USB_RAM (0x00004000) 524 /* @brief Base address of the USB dedicated RAM */ 525 #define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40140000) 526 /* @brief USBHSD version */ 527 #define FSL_FEATURE_USBHSD_VERSION (300) 528 /* @brief Number of the endpoint in USB HS */ 529 #define FSL_FEATURE_USBHSD_EP_NUM (6) 530 /* @brief The controller doesn't exit HS mode automatically after vbus becomes invalid */ 531 #define FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE (1) 532 533 /* USBHSH module features */ 534 535 /* @brief Size of the USB dedicated RAM */ 536 #define FSL_FEATURE_USBHSH_USB_RAM (0x00004000) 537 /* @brief Base address of the USB dedicated RAM */ 538 #define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40140000) 539 /* @brief USBHSH version */ 540 #define FSL_FEATURE_USBHSH_VERSION (300) 541 /* @brief USBHSH has packet turnaround time-out register */ 542 #define FSL_FEATURE_USBHSH_HAS_TURNAROUND_TIMEOUT (0) 543 544 /* USBPHY module features */ 545 546 /* @brief USBPHY contain DCD analog module */ 547 #define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (1) 548 /* @brief USBPHY has register TRIM_OVERRIDE_EN */ 549 #define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) 550 /* @brief USBPHY is 28FDSOI */ 551 #define FSL_FEATURE_USBPHY_28FDSOI (0) 552 553 /* USDHC module features */ 554 555 /* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ 556 #define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) 557 /* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ 558 #define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) 559 /* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ 560 #define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) 561 /* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ 562 #define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) 563 /* @brief USDHC has reset control */ 564 #define FSL_FEATURE_USDHC_HAS_RESET (1) 565 /* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ 566 #define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) 567 /* @brief If USDHC instance support 8 bit width */ 568 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) 569 /* @brief If USDHC instance support HS400 mode */ 570 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) \ 571 (((x) == USDHC0) ? (1) : \ 572 (((x) == USDHC1) ? (0) : (-1))) 573 /* @brief If USDHC instance support 1v8 signal */ 574 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) 575 /* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ 576 #define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (0) 577 /* @brief Has no VSELECT bit in VEND_SPEC register */ 578 #define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0) 579 /* @brief Has no VS18 bit in HOST_CTRL_CAP register */ 580 #define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) 581 582 /* UTICK module features */ 583 584 /* @brief UTICK does not support power down configure. */ 585 #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) 586 587 /* WWDT module features */ 588 589 /* @brief WWDT does not support oscillator lock. */ 590 #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) 591 /* @brief WWDT does not support power down configure. */ 592 #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) 593 594 #endif /* _MIMXRT633S_FEATURES_H_ */ 595 596
