1 /* 2 ** ################################################################### 3 ** Version: rev. 4.0, 2020-05-18 4 ** Build: b240521 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2024 NXP 11 ** SPDX-License-Identifier: BSD-3-Clause 12 ** 13 ** http: www.nxp.com 14 ** mail: support@nxp.com 15 ** 16 ** Revisions: 17 ** - rev. 1.0 (2019-04-19) 18 ** Initial version. 19 ** - rev. 2.0 (2019-07-22) 20 ** Base on rev 0.7 RM. 21 ** - rev. 3.0 (2020-03-16) 22 ** Base on Rev.A RM. 23 ** - rev. 4.0 (2020-05-18) 24 ** Base on Rev.B RM. 25 ** 26 ** ################################################################### 27 */ 28 29 #ifndef _MIMXRT533S_FEATURES_H_ 30 #define _MIMXRT533S_FEATURES_H_ 31 32 /* SOC module features */ 33 34 /* @brief ACMP availability on the SoC. */ 35 #define FSL_FEATURE_SOC_ACMP_COUNT (1) 36 /* @brief AIPS availability on the SoC. */ 37 #define FSL_FEATURE_SOC_AIPS_COUNT (2) 38 /* @brief CACHE64_CTRL availability on the SoC. */ 39 #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (2) 40 /* @brief CACHE64_POLSEL availability on the SoC. */ 41 #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (2) 42 /* @brief CASPER availability on the SoC. */ 43 #define FSL_FEATURE_SOC_CASPER_COUNT (1) 44 /* @brief CLKCTL0 availability on the SoC. */ 45 #define FSL_FEATURE_SOC_CLKCTL0_COUNT (1) 46 /* @brief CLKCTL1 availability on the SoC. */ 47 #define FSL_FEATURE_SOC_CLKCTL1_COUNT (1) 48 /* @brief CRC availability on the SoC. */ 49 #define FSL_FEATURE_SOC_CRC_COUNT (1) 50 /* @brief CTIMER availability on the SoC. */ 51 #define FSL_FEATURE_SOC_CTIMER_COUNT (5) 52 /* @brief DMA availability on the SoC. */ 53 #define FSL_FEATURE_SOC_DMA_COUNT (2) 54 /* @brief DMIC availability on the SoC. */ 55 #define FSL_FEATURE_SOC_DMIC_COUNT (1) 56 /* @brief FLEXCOMM availability on the SoC. */ 57 #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (17) 58 /* @brief FLEXIO availability on the SoC. */ 59 #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) 60 /* @brief FLEXSPI availability on the SoC. */ 61 #define FSL_FEATURE_SOC_FLEXSPI_COUNT (2) 62 /* @brief FREQME availability on the SoC. */ 63 #define FSL_FEATURE_SOC_FREQME_COUNT (1) 64 /* @brief GPIO availability on the SoC. */ 65 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 66 /* @brief SECGPIO availability on the SoC. */ 67 #define FSL_FEATURE_SOC_SECGPIO_COUNT (1) 68 /* @brief HASHCRYPT availability on the SoC. */ 69 #define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) 70 /* @brief I2C availability on the SoC. */ 71 #define FSL_FEATURE_SOC_I2C_COUNT (15) 72 /* @brief I3C availability on the SoC. */ 73 #define FSL_FEATURE_SOC_I3C_COUNT (2) 74 /* @brief I2S availability on the SoC. */ 75 #define FSL_FEATURE_SOC_I2S_COUNT (14) 76 /* @brief INPUTMUX availability on the SoC. */ 77 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 78 /* @brief IOPCTL availability on the SoC. */ 79 #define FSL_FEATURE_SOC_IOPCTL_COUNT (1) 80 /* @brief LPADC availability on the SoC. */ 81 #define FSL_FEATURE_SOC_LPADC_COUNT (1) 82 /* @brief MPU availability on the SoC. */ 83 #define FSL_FEATURE_SOC_MPU_COUNT (1) 84 /* @brief MRT availability on the SoC. */ 85 #define FSL_FEATURE_SOC_MRT_COUNT (1) 86 /* @brief MU availability on the SoC. */ 87 #define FSL_FEATURE_SOC_MU_COUNT (1) 88 /* @brief OCOTP availability on the SoC. */ 89 #define FSL_FEATURE_SOC_OCOTP_COUNT (1) 90 /* @brief OSTIMER availability on the SoC. */ 91 #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) 92 /* @brief OTFAD availability on the SoC. */ 93 #define FSL_FEATURE_SOC_OTFAD_COUNT (1) 94 /* @brief PINT availability on the SoC. */ 95 #define FSL_FEATURE_SOC_PINT_COUNT (1) 96 /* @brief PMC availability on the SoC. */ 97 #define FSL_FEATURE_SOC_PMC_COUNT (1) 98 /* @brief POWERQUAD availability on the SoC. */ 99 #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) 100 /* @brief PUF availability on the SoC. */ 101 #define FSL_FEATURE_SOC_PUF_COUNT (1) 102 /* @brief RSTCTL0 availability on the SoC. */ 103 #define FSL_FEATURE_SOC_RSTCTL0_COUNT (1) 104 /* @brief RSTCTL1 availability on the SoC. */ 105 #define FSL_FEATURE_SOC_RSTCTL1_COUNT (1) 106 /* @brief RTC availability on the SoC. */ 107 #define FSL_FEATURE_SOC_RTC_COUNT (1) 108 /* @brief SCT availability on the SoC. */ 109 #define FSL_FEATURE_SOC_SCT_COUNT (1) 110 /* @brief SEMA42 availability on the SoC. */ 111 #define FSL_FEATURE_SOC_SEMA42_COUNT (1) 112 /* @brief SMARTDMA availability on the SoC. */ 113 #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) 114 /* @brief SPI availability on the SoC. */ 115 #define FSL_FEATURE_SOC_SPI_COUNT (16) 116 /* @brief SYSCTL0 availability on the SoC. */ 117 #define FSL_FEATURE_SOC_SYSCTL0_COUNT (1) 118 /* @brief SYSCTL1 availability on the SoC. */ 119 #define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) 120 /* @brief TRNG availability on the SoC. */ 121 #define FSL_FEATURE_SOC_TRNG_COUNT (1) 122 /* @brief USART availability on the SoC. */ 123 #define FSL_FEATURE_SOC_USART_COUNT (14) 124 /* @brief USBHSD availability on the SoC. */ 125 #define FSL_FEATURE_SOC_USBHSD_COUNT (1) 126 /* @brief USBHSDCD availability on the SoC. */ 127 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (1) 128 /* @brief USBHSH availability on the SoC. */ 129 #define FSL_FEATURE_SOC_USBHSH_COUNT (1) 130 /* @brief USBPHY availability on the SoC. */ 131 #define FSL_FEATURE_SOC_USBPHY_COUNT (1) 132 /* @brief USDHC availability on the SoC. */ 133 #define FSL_FEATURE_SOC_USDHC_COUNT (2) 134 /* @brief UTICK availability on the SoC. */ 135 #define FSL_FEATURE_SOC_UTICK_COUNT (1) 136 /* @brief WWDT availability on the SoC. */ 137 #define FSL_FEATURE_SOC_WWDT_COUNT (2) 138 139 /* ACMP module features */ 140 141 /* @brief Has CMP_C3. */ 142 #define FSL_FEATURE_ACMP_HAS_C3_REG (1) 143 /* @brief Has C0 LINKEN Bit */ 144 #define FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT (1) 145 /* @brief Has C0 OFFSET Bit */ 146 #define FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT (0) 147 /* @brief Has C0 HYSTCTR Bit */ 148 #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) 149 /* @brief Has C1 INPSEL Bit */ 150 #define FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT (0) 151 /* @brief Has C1 INNSEL Bit */ 152 #define FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT (0) 153 /* @brief Has C1 DACOE Bit */ 154 #define FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT (0) 155 /* @brief Has C1 DMODE Bit */ 156 #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) 157 /* @brief Has C2 RRE Bit */ 158 #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) 159 160 /* LPADC module features */ 161 162 /* @brief FIFO availability on the SoC. */ 163 #define FSL_FEATURE_LPADC_FIFO_COUNT (2) 164 /* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ 165 #define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (1) 166 /* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ 167 #define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) 168 /* @brief Has differential mode (bitfield CMDLn[DIFF]). */ 169 #define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (1) 170 /* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ 171 #define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (1) 172 /* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ 173 #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (0) 174 /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ 175 #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (0) 176 /* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ 177 #define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) 178 /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ 179 #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) 180 /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ 181 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (0) 182 /* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ 183 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (0) 184 /* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ 185 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (0) 186 /* @brief Has internal clock (bitfield CFG[ADCKEN]). */ 187 #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) 188 /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ 189 #define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) 190 /* @brief Has calibration (bitfield CFG[CALOFS]). */ 191 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) 192 /* @brief Has offset trim (register OFSTRIM). */ 193 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (0) 194 /* @brief Has Trigger status register. */ 195 #define FSL_FEATURE_LPADC_HAS_TSTAT (1) 196 /* @brief Has power select (bitfield CFG[PWRSEL]). */ 197 #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) 198 /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ 199 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) 200 /* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ 201 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) 202 /* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ 203 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) 204 /* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ 205 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) 206 /* @brief Conversion averaged bitfiled width. */ 207 #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) 208 /* @brief Has B side channels. */ 209 #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) 210 /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ 211 #define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) 212 /* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ 213 #define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) 214 /* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ 215 #define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (0) 216 /* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ 217 #define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) 218 /* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ 219 #define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) 220 /* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ 221 #define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) 222 /* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ 223 #define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) 224 /* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ 225 #define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) 226 /* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ 227 #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) 228 /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ 229 #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) 230 231 /* CACHE64_CTRL module features */ 232 233 /* @brief Cache Line size in byte. */ 234 #define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (32) 235 236 /* CACHE64_POLSEL module features */ 237 238 /* No feature definitions */ 239 240 /* CASPER module features */ 241 242 /* @brief Base address of the CASPER dedicated RAM. */ 243 #define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x40202000u) 244 245 /* CRC module features */ 246 247 /* @brief Has data register with name CRC */ 248 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 249 250 /* CTIMER module features */ 251 252 /* @brief CTIMER has no capture channel. */ 253 #define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) 254 /* @brief CTIMER has no capture 2 interrupt. */ 255 #define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) 256 /* @brief CTIMER capture 3 interrupt. */ 257 #define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) 258 /* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ 259 #define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) 260 /* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ 261 #define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) 262 /* @brief CTIMER Has register MSR */ 263 #define FSL_FEATURE_CTIMER_HAS_MSR (1) 264 265 /* DMA module features */ 266 267 /* @brief Number of channels */ 268 #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) (37) 269 /* @brief Number of all DMA channels */ 270 #define FSL_FEATURE_DMA_ALL_CHANNELS (74) 271 /* @brief Max Number of DMA channels */ 272 #define FSL_FEATURE_DMA_MAX_CHANNELS (37) 273 /* @brief Align size of DMA descriptor */ 274 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (1024) 275 /* @brief DMA head link descriptor table align size */ 276 #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) 277 278 /* DMIC module features */ 279 280 /* @brief Number of channels */ 281 #define FSL_FEATURE_DMIC_CHANNEL_NUM (8) 282 /* @brief DMIC channel support stereo data */ 283 #define FSL_FEATURE_DMIC_IO_HAS_STEREO_2_4_6 (1) 284 /* @brief DMIC does not support bypass channel clock */ 285 #define FSL_FEATURE_DMIC_IO_HAS_NO_BYPASS (1) 286 /* @brief DMIC channel FIFO register support sign extended */ 287 #define FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND (1) 288 /* @brief DMIC has no IOCFG register */ 289 #define FSL_FEATURE_DMIC_HAS_NO_IOCFG (1) 290 /* @brief DMIC has decimator reset function */ 291 #define FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC (1) 292 /* @brief DMIC has global channel synchronization function */ 293 #define FSL_FEATURE_DMIC_HAS_GLOBAL_SYNC_FUNC (1) 294 295 /* FLEXCOMM module features */ 296 297 /* @brief FLEXCOMM0 USART INDEX 0 */ 298 #define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) 299 /* @brief FLEXCOMM1 USART INDEX 1 */ 300 #define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) 301 /* @brief FLEXCOMM2 USART INDEX 2 */ 302 #define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) 303 /* @brief FLEXCOMM3 USART INDEX 3 */ 304 #define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) 305 /* @brief FLEXCOMM4 USART INDEX 4 */ 306 #define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) 307 /* @brief FLEXCOMM5 USART INDEX 5 */ 308 #define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) 309 /* @brief FLEXCOMM6 USART INDEX 6 */ 310 #define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) 311 /* @brief FLEXCOMM7 USART INDEX 7 */ 312 #define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) 313 /* @brief FLEXCOMM14 SPI(HS_SPI) INDEX 14 */ 314 #define FSL_FEATURE_FLEXCOMM14_SPI_INDEX (14) 315 /* @brief FLEXCOMM15 I2C INDEX 15 */ 316 #define FSL_FEATURE_FLEXCOMM15_I2C_INDEX (15) 317 /* @brief FLEXCOMM16 SPI(HS_SPI) INDEX 16 */ 318 #define FSL_FEATURE_FLEXCOMM16_SPI_INDEX (16) 319 /* @brief FLEXCOMM8 USART INDEX 8 */ 320 #define FSL_FEATURE_FLEXCOMM8_USART_INDEX (8) 321 /* @brief FLEXCOMM9 USART INDEX 9 */ 322 #define FSL_FEATURE_FLEXCOMM9_USART_INDEX (9) 323 /* @brief FLEXCOMM10 USART INDEX 10 */ 324 #define FSL_FEATURE_FLEXCOMM10_USART_INDEX (10) 325 /* @brief FLEXCOMM11 USART INDEX 11 */ 326 #define FSL_FEATURE_FLEXCOMM11_USART_INDEX (11) 327 /* @brief FLEXCOMM12 USART INDEX 12 */ 328 #define FSL_FEATURE_FLEXCOMM12_USART_INDEX (12) 329 /* @brief FLEXCOMM13 USART INDEX 13 */ 330 #define FSL_FEATURE_FLEXCOMM13_USART_INDEX (13) 331 /* @brief FLEXCOMM0 SPI INDEX 0 */ 332 #define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) 333 /* @brief FLEXCOMM1 SPI INDEX 1 */ 334 #define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) 335 /* @brief FLEXCOMM2 SPI INDEX 2 */ 336 #define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) 337 /* @brief FLEXCOMM3 SPI INDEX 3 */ 338 #define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) 339 /* @brief FLEXCOMM4 SPI INDEX 4 */ 340 #define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) 341 /* @brief FLEXCOMM5 SPI INDEX 5 */ 342 #define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) 343 /* @brief FLEXCOMM6 SPI INDEX 6 */ 344 #define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) 345 /* @brief FLEXCOMM7 SPI INDEX 7 */ 346 #define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) 347 /* @brief I2S has DMIC interconnection */ 348 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) \ 349 (((x) == FLEXCOMM14) ? (0) : \ 350 (((x) == FLEXCOMM15) ? (0) : \ 351 (((x) == FLEXCOMM16) ? (0) : \ 352 (((x) == FLEXCOMM0) ? (1) : \ 353 (((x) == FLEXCOMM1) ? (0) : \ 354 (((x) == FLEXCOMM2) ? (0) : \ 355 (((x) == FLEXCOMM3) ? (0) : \ 356 (((x) == FLEXCOMM4) ? (0) : \ 357 (((x) == FLEXCOMM5) ? (0) : \ 358 (((x) == FLEXCOMM6) ? (0) : \ 359 (((x) == FLEXCOMM7) ? (0) : \ 360 (((x) == FLEXCOMM8) ? (0) : \ 361 (((x) == FLEXCOMM9) ? (0) : \ 362 (((x) == FLEXCOMM10) ? (0) : \ 363 (((x) == FLEXCOMM11) ? (0) : \ 364 (((x) == FLEXCOMM12) ? (0) : \ 365 (((x) == FLEXCOMM13) ? (0) : (-1)))))))))))))))))) 366 /* @brief FLEXCOMM8 SPI INDEX 8 */ 367 #define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) 368 /* @brief FLEXCOMM9 SPI INDEX 9 */ 369 #define FSL_FEATURE_FLEXCOMM9_SPI_INDEX (9) 370 /* @brief FLEXCOMM10 SPI INDEX 10 */ 371 #define FSL_FEATURE_FLEXCOMM10_SPI_INDEX (10) 372 /* @brief FLEXCOMM11 SPI INDEX 11 */ 373 #define FSL_FEATURE_FLEXCOMM11_SPI_INDEX (11) 374 /* @brief FLEXCOMM12 SPI INDEX 12 */ 375 #define FSL_FEATURE_FLEXCOMM12_SPI_INDEX (12) 376 /* @brief FLEXCOMM13 SPI INDEX 13 */ 377 #define FSL_FEATURE_FLEXCOMM13_SPI_INDEX (13) 378 /* @brief FLEXCOMM0 I2C INDEX 0 */ 379 #define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) 380 /* @brief FLEXCOMM1 I2C INDEX 1 */ 381 #define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) 382 /* @brief FLEXCOMM2 I2C INDEX 2 */ 383 #define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) 384 /* @brief FLEXCOMM3 I2C INDEX 3 */ 385 #define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) 386 /* @brief FLEXCOMM4 I2C INDEX 4 */ 387 #define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) 388 /* @brief FLEXCOMM5 I2C INDEX 5 */ 389 #define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) 390 /* @brief FLEXCOMM6 I2C INDEX 6 */ 391 #define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) 392 /* @brief FLEXCOMM7 I2C INDEX 7 */ 393 #define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) 394 /* @brief FLEXCOMM8 I2C INDEX 8 */ 395 #define FSL_FEATURE_FLEXCOMM8_I2C_INDEX (8) 396 /* @brief FLEXCOMM9 I2C INDEX 9 */ 397 #define FSL_FEATURE_FLEXCOMM9_I2C_INDEX (9) 398 /* @brief FLEXCOMM10 I2C INDEX 10 */ 399 #define FSL_FEATURE_FLEXCOMM10_I2C_INDEX (10) 400 /* @brief FLEXCOMM11 I2C INDEX 11 */ 401 #define FSL_FEATURE_FLEXCOMM11_I2C_INDEX (11) 402 /* @brief FLEXCOMM12 I2C INDEX 12 */ 403 #define FSL_FEATURE_FLEXCOMM12_I2C_INDEX (12) 404 /* @brief FLEXCOMM13 I2C INDEX 13 */ 405 #define FSL_FEATURE_FLEXCOMM13_I2C_INDEX (13) 406 /* @brief FLEXCOMM0 I2S INDEX 0 */ 407 #define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) 408 /* @brief FLEXCOMM1 I2S INDEX 1 */ 409 #define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) 410 /* @brief FLEXCOMM2 I2S INDEX 2 */ 411 #define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) 412 /* @brief FLEXCOMM3 I2S INDEX 3 */ 413 #define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) 414 /* @brief FLEXCOMM4 I2S INDEX 4 */ 415 #define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) 416 /* @brief FLEXCOMM5 I2S INDEX 5 */ 417 #define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) 418 /* @brief FLEXCOMM6 I2S INDEX 6 */ 419 #define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) 420 /* @brief FLEXCOMM7 I2S INDEX 7 */ 421 #define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) 422 /* @brief FLEXCOMM8 I2S INDEX 8 */ 423 #define FSL_FEATURE_FLEXCOMM8_I2S_INDEX (8) 424 /* @brief FLEXCOMM9 I2S INDEX 9 */ 425 #define FSL_FEATURE_FLEXCOMM9_I2S_INDEX (9) 426 /* @brief FLEXCOMM10 I2S INDEX 10 */ 427 #define FSL_FEATURE_FLEXCOMM10_I2S_INDEX (10) 428 /* @brief FLEXCOMM11 I2S INDEX 11 */ 429 #define FSL_FEATURE_FLEXCOMM11_I2S_INDEX (11) 430 /* @brief FLEXCOMM12 I2S INDEX 12 */ 431 #define FSL_FEATURE_FLEXCOMM12_I2S_INDEX (12) 432 /* @brief FLEXCOMM13 I2S INDEX 13 */ 433 #define FSL_FEATURE_FLEXCOMM13_I2S_INDEX (13) 434 435 /* FLEXIO module features */ 436 437 /* @brief FLEXIO support reset from RSTCTL */ 438 #define FSL_FEATURE_FLEXIO_HAS_RESET (1) 439 /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ 440 #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) 441 /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ 442 #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) 443 /* @brief Has pin input output related registers */ 444 #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) 445 /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ 446 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) 447 /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ 448 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) 449 /* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ 450 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) 451 /* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 452 #define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) 453 /* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 454 #define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) 455 /* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ 456 #define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) 457 /* @brief Reset value of the FLEXIO_VERID register */ 458 #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) 459 /* @brief Reset value of the FLEXIO_PARAM register */ 460 #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x10100808) 461 /* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ 462 #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) 463 464 /* FLEXSPI module features */ 465 466 /* @brief FlexSPI AHB buffer count */ 467 #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) 468 /* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ 469 #define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (1) 470 /* @brief FlexSPI has no MCR0 ARDFEN bit */ 471 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) 472 /* @brief FlexSPI has no MCR0 ATDFEN bit */ 473 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) 474 /* @brief FlexSPI DMA needs multiple DES to transfer */ 475 #define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) 476 /* @brief FlexSPI uses min DQS delay */ 477 #define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (1) 478 /* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ 479 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) 480 /* @brief FLEXSPI has no IP parallel mode. */ 481 #define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) 482 /* @brief FLEXSPI has no AHB parallel mode. */ 483 #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) 484 /* @brief FLEXSPI support address shift. */ 485 #define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) 486 /* @brief FlexSPI has no FLSHCR4 WMENB bit */ 487 #define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (1) 488 /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ 489 #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) 490 /* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ 491 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (1) 492 /* @brief Has Errata 051426 */ 493 #define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (1) 494 /* @brief FlexSPI AHB RX buffer size (byte) */ 495 #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) \ 496 (((x) == FLEXSPI0) ? (1024) : \ 497 (((x) == FLEXSPI1) ? (2048) : (-1))) 498 499 /* GPIO module features */ 500 501 /* @brief GPIO has interrupts */ 502 #define FSL_FEATURE_GPIO_HAS_INTERRUPT (1) 503 /* @brief GPIO DIRSET and DIRCLR register. */ 504 #define FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR (1) 505 506 /* HASHCRYPT module features */ 507 508 /* @brief hashcrypt has reload feature */ 509 #define FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE (1) 510 511 /* I2S module features */ 512 513 /* @brief I2S support dual channel transfer. */ 514 #define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1) 515 /* @brief I2S has DMIC interconnection. */ 516 #define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (1) 517 518 /* I3C module features */ 519 520 /* @brief Has TERM bitfile in MERRWARN register. */ 521 #define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) 522 /* @brief SOC has no reset driver. */ 523 #define FSL_FEATURE_I3C_HAS_NO_RESET (0) 524 /* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ 525 #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) 526 /* @brief Register SCONFIG do not have IDRAND bitfield. */ 527 #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) 528 /* @brief Register SCONFIG has HDROK bitfield. */ 529 #define FSL_FEATURE_I3C_HAS_HDROK (0) 530 /* @brief SOC doesn't support slave IBI/MR/HJ. */ 531 #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) 532 /* @brief Has ERRATA_051617. */ 533 #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (1) 534 /* @brief Has ERRATA_052123. */ 535 #define FSL_FEATURE_I3C_HAS_ERRATA_052123 (1) 536 /* @brief Has no the master write data register for DMA. */ 537 #define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) 538 539 /* INPUTMUX module features */ 540 541 /* @brief Inputmux has DMA Request Enable */ 542 #define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) 543 /* @brief Inputmux has channel mux control */ 544 #define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (1) 545 546 /* MRT module features */ 547 548 /* @brief number of channels. */ 549 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) 550 551 /* MU module features */ 552 553 /* @brief MU side for current core */ 554 #define FSL_FEATURE_MU_SIDE_A (1) 555 /* @brief MU Has register CCR */ 556 #define FSL_FEATURE_MU_HAS_CCR (0) 557 /* @brief MU Has register SR[RS], BSR[ARS] */ 558 #define FSL_FEATURE_MU_HAS_SR_RS (1) 559 /* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */ 560 #define FSL_FEATURE_MU_HAS_RESET_INT (1) 561 /* @brief MU Has register SR[MURIP] */ 562 #define FSL_FEATURE_MU_HAS_SR_MURIP (0) 563 /* @brief brief MU Has register SR[HRIP] */ 564 #define FSL_FEATURE_MU_HAS_SR_HRIP (0) 565 /* @brief brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */ 566 #define FSL_FEATURE_MU_NO_CLKE (1) 567 /* @brief brief MU does not support NMI, CR[NMI]. */ 568 #define FSL_FEATURE_MU_NO_NMI (1) 569 /* @brief brief MU does not support hold the other core reset. CR[RSTH] or CCR[RSTH]. */ 570 #define FSL_FEATURE_MU_NO_RSTH (1) 571 /* @brief brief MU does not supports MU reset, CR[MUR]. */ 572 #define FSL_FEATURE_MU_NO_MUR (0) 573 /* @brief brief MU does not supports hardware reset, CR[HR] or CCR[HR]. */ 574 #define FSL_FEATURE_MU_NO_HR (1) 575 /* @brief brief MU supports mask the hardware reset. CR[HRM] or CCR[HRM]. */ 576 #define FSL_FEATURE_MU_HAS_HRM (0) 577 578 /* OTFAD module features */ 579 580 /* @brief OTFAD has Security Violation Mode (SVM) */ 581 #define FSL_FEATURE_OTFAD_HAS_SVM_MODE (0) 582 /* @brief OTFAD has Key Blob Processing */ 583 #define FSL_FEATURE_OTFAD_HAS_KEYBLOB_PROCESSING (0) 584 /* @brief OTFAD has interrupt request enable */ 585 #define FSL_FEATURE_OTFAD_HAS_HAS_IRQ_ENABLE (0) 586 /* @brief OTFAD has Force Error */ 587 #define FSL_FEATURE_OTFAD_HAS_FORCE_ERR (0) 588 589 /* PINT module features */ 590 591 /* @brief Number of connected outputs */ 592 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) 593 594 /* PMC module features */ 595 596 /* @brief Has no OS Timer control register in PMC. */ 597 #define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1) 598 599 /* PUF module features */ 600 601 /* @brief PUF need to setup SRAM manually */ 602 #define FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL (1) 603 /* @brief PUF has SHIFT_STATUS register. */ 604 #define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (0) 605 /* @brief PUF has IDXBLK_SHIFT register. */ 606 #define FSL_FEATURE_PUF_HAS_IDXBLK_SHIFT (0) 607 608 /* RTC module features */ 609 610 /* @brief RTC has no reset control */ 611 #define FSL_FEATURE_RTC_HAS_NO_RESET (1) 612 /* @brief Has SUBSEC Register (register SUBSEC) */ 613 #define FSL_FEATURE_RTC_HAS_SUBSEC (1) 614 615 /* SCT module features */ 616 617 /* @brief Number of events */ 618 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) 619 /* @brief Number of states */ 620 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) 621 /* @brief Number of match capture */ 622 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) 623 /* @brief Number of outputs */ 624 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) 625 626 /* SECGPIO module features */ 627 628 /* @brief GPIO has interrupts */ 629 #define FSL_FEATURE_SECGPIO_HAS_INTERRUPT (1) 630 /* @brief GPIO DIRSET and DIRCLR register. */ 631 #define FSL_FEATURE_SECGPIO_DIRSET_AND_DIRCLR (1) 632 633 /* SEMA42 module features */ 634 635 /* @brief Gate counts */ 636 #define FSL_FEATURE_SEMA42_GATE_COUNT (16) 637 638 /* SPI module features */ 639 640 /* @brief SSEL pin count. */ 641 #define FSL_FEATURE_SPI_SSEL_COUNT (4) 642 643 /* TRNG module features */ 644 645 /* @brief Need configure default frequency minimum value */ 646 #define FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM (1) 647 /* @brief The user configured frequency minimum value */ 648 #define FSL_FEATURE_TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM_VALUE (0) 649 650 /* USBHSD module features */ 651 652 /* @brief Size of the USB dedicated RAM */ 653 #define FSL_FEATURE_USBHSD_USB_RAM (0x00004000) 654 /* @brief Base address of the USB dedicated RAM */ 655 #define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40140000) 656 /* @brief USBHSD version */ 657 #define FSL_FEATURE_USBHSD_VERSION (300) 658 /* @brief Number of the endpoint in USB HS */ 659 #define FSL_FEATURE_USBHSD_EP_NUM (6) 660 /* @brief The controller doesn't exit HS mode automatically after vbus becomes invalid */ 661 #define FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE (1) 662 663 /* USBHSH module features */ 664 665 /* @brief Size of the USB dedicated RAM */ 666 #define FSL_FEATURE_USBHSH_USB_RAM (0x00004000) 667 /* @brief Base address of the USB dedicated RAM */ 668 #define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40140000) 669 /* @brief USBHSH version */ 670 #define FSL_FEATURE_USBHSH_VERSION (300) 671 /* @brief USBHSH has packet turnaround time-out register */ 672 #define FSL_FEATURE_USBHSH_HAS_TURNAROUND_TIMEOUT (0) 673 674 /* USBPHY module features */ 675 676 /* @brief USBPHY contain DCD analog module */ 677 #define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (1) 678 /* @brief USBPHY has register TRIM_OVERRIDE_EN */ 679 #define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) 680 /* @brief USBPHY is 28FDSOI */ 681 #define FSL_FEATURE_USBPHY_28FDSOI (0) 682 683 /* USDHC module features */ 684 685 /* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ 686 #define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) 687 /* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ 688 #define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) 689 /* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ 690 #define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) 691 /* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ 692 #define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) 693 /* @brief USDHC has reset control */ 694 #define FSL_FEATURE_USDHC_HAS_RESET (1) 695 /* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ 696 #define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) 697 /* @brief If USDHC instance support 8 bit width */ 698 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) 699 /* @brief If USDHC instance support HS400 mode */ 700 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) \ 701 (((x) == USDHC0) ? (1) : \ 702 (((x) == USDHC1) ? (0) : (-1))) 703 /* @brief If USDHC instance support 1v8 signal */ 704 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) 705 /* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ 706 #define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (0) 707 /* @brief Has no VSELECT bit in VEND_SPEC register */ 708 #define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0) 709 /* @brief Has no VS18 bit in HOST_CTRL_CAP register */ 710 #define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) 711 712 /* UTICK module features */ 713 714 /* @brief UTICK does not support power down configure. */ 715 #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) 716 717 /* WWDT module features */ 718 719 /* @brief WWDT does not support oscillator lock. */ 720 #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) 721 /* @brief WWDT does not support power down configure. */ 722 #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) 723 724 #endif /* _MIMXRT533S_FEATURES_H_ */ 725 726
